Scribd
Upload
3 views

c_bits, assemble!_2025

The document outlines a competition event titled 'Bits, Assemble!' where teams of up to two participants will be assessed on their understanding of low-level computer instructions and assembly instruction sets. Participants can bring a binder and calculators to aid in a written test consisting of various question types related to numerical systems, logical operations, finite state machines, and instruction set architectures. Scoring will be based on the accuracy of responses, with sample questions provided to illustrate the types of problems competitors may encounter.

Uploaded by

murtazaazm065
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
3 views

c_bits, assemble!_2025

The document outlines a competition event titled 'Bits, Assemble!' where teams of up to two participants will be assessed on their understanding of low-level computer instructions and assembly instruction sets. Participants can bring a binder and calculators to aid in a written test consisting of various question types related to numerical systems, logical operations, finite state machines, and instruction set architectures. Scoring will be based on the accuracy of responses, with sample questions provided to illustrate the types of problems competitors may encounter.

Uploaded by

murtazaazm065
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Bits, Assemble!

1. DESCRIPTION: Participants will be assessed on their understanding of low-level computer


instructions, assembly instruction sets, and their basic digital implementations.
A TEAM OF UP TO: 2 APPROXIMATE TIME: 50 minutes
2. EVENT PARAMETERS:
a. Each team may bring one three-ring binder of any size containing information in any
form and from any source attached using the available rings. Sheet protectors,
lamination, tabs and labels are permitted. Participants may remove information or
pages for their use during any part of the event.
b. Each team may bring up to 2 calculators of any type.
3. THE COMPETITION:
a. Teams will be given a minimum of 40 minutes to complete a written test consisting of
multiple choice, true-false, calculation, or code writing problems given a certain
instruction set.
b. Due to the large variance in instruction sets, if the exam includes questions that
require the writing of assembly instructions in a specific architecture, the Event
Supervisor is strongly recommend to provide the instruction set in its entirety, both
two weeks prior to the tournament in an email to coaches and in the test booklet,
including how the instructions are encoded.
c. The test must consist of questions from solely the following areas, ensuring that at
least two (2) questions/parts/subparts are about topics from each section.
i. Numerical systems (Binary, Hexadecimal, Octal, Decimal, etc.), their use cases,
conversion between them, and realization of bits.
ii. Binary representations of numbers in computers (two’s complement, one’s
complement, sign and magnitude, floating point, fixed point, etc.).
iii. Logical operations (i.e. boolean operations) including (but not limited to) truth
tables, Karnaugh maps, and Boolean algebra and their idealized transistor
realizations.
iv. Finite State Machines (FSMs), their related diagrams and tables (state tables,
transition diagrams, etc.), their use cases, and the process for implementation.
v. Registers, their use in assembly programming, their physical implementations
(including latches, gates, etc.), memory locations, and memory accesses
vi. Common Instruction Set Architectures (ISAs), their structure (including
concepts of completeness), and binary decoding of instructions.
vii. The use of a specific ISA to complete simple coding exercises/problems.
viii. (Division C Only) Interrupts and Interrupt Service Routines (ISRs), including
the use of the stack.
ix. (Division C Only) Conversion of low level instructions (C) into assembly (and
the reverse), including the effect of different optimization levels

4. SCORING:
a. Highest score wins.
b. Points will be awarded for the quality and accuracy of responses.
c. Selected questions may be used as tiebreakers.
5. SAMPLE QUESTIONS:
a. Convert (decimal) 10 to binary, hexadecimal. How many bits are needed to represent
this number?
b. Convert (decimal) -10 to sign and magnitude binary, 1’s complement binary, and 2’s
complement binary.
c. Simplify F=A !B C+A to the simplest equivalent boolean expression and complete the
truth table for F.
d. Draw the CMOS implementation of an inverter (ie, NOT) using a pair of ideal
transistors.
e. Draw a FSM with the minimum states that, given a binary sequence as its inputs,
outputs the remainder when the number of ones up to a point in the sequence is
divided by 3. Draw the state table for this FSM.
f. Draw a D-Latch using only basic logic gates.
g. How many bits are needed in the address for a computer architecture with 2000
memory locations? What is stored at these addresses?
h. Encode the instruction ADD, R1, R1, #2 to binary assuming that this instruction uses
x86 encoding.
i. Write a simple subroutine to find the difference of two numbers which are placed in
R0 and R1 and stores the answer in R2. Assume that the numbers are stored in 2’s
complement. Use the LC-3 ISA provided to structure your instructions.
j. Write a simple subroutine to sum the values of a null-terminated array (ie, the array is
marked as complete in memory when a value of 0x0 is reached). Use the ARM ISA
provided to structure your instructions. Hint: Use the BEQ loop statement.
k. Describe, using the provided FSM for the data path of the LC3’s interrupt sequence,
how the LC3 ensures the proper operation of interrupted instructions, even when
ISRs change condition bits.
l. Given the following snippet of C code, predict the generated binary instructions of a
compiler with high optimization and low optimization.

You might also like