S. S.

Education Trust’s

S. G. BALEKUNDRI
INSTITUTE OF TECHNOLOGY
[Affiliated to Visvesvaraya Technological University (VTU), Belagavi, Karnataka]

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

B.E - VII Semester

2022-23 [ODD SEMESTER]

VLSI LABORATORY MANUAL

[As per Choice Based Credit System (CBCS) scheme 18ECL77]

Prepared by Approved by

Prof. Narayan A.Badiger, Asst. Professor Dr. Suresh Akkole

Prof. Soumya H, Asst. Professor Head of the Department

Mr. Vijay Mulimani, Lab Instructor

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 Institution Vision

To Impart Quality Education with Human Values and emerge as of one of the
Nation’s Leading Institutions in the field of Technical Education and Research.

Institution Mission

• Strive to encourage ideas, talents and value systems.

• Guide students to be successful in the endeavor with moral and ethical

values.

• Build relation with Industries and National Laboratories to support in the

field of Engineering and Technology.

• Inculcate a thirst for knowledge in students and help them to achieve

Academic Excellence and Placement.

• Train and develop the faculty to achieve Professional, Organizational

Objectives, and excel in Research and Development.

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 Department Vision
To be the department of Electronics and Communication Engineering striving hard
to develop responsive teaching–learning methodology, research and employable
skills in allied fields by empowering students to become globally competent and
socially responsible citizens.

Department Mission

M1: To develop an active learning environment that ensures participation of

students in both curricular as well as co-curricular activities.

M2: To foster research, innovation and creativity amongst students.

M3: To encourage development of entrepreneurial skills.

M4: To inculcate, amongst students, team-spirit, leadership qualities, positive

attitude and effective communication skills to solve societal needs.

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 Program Educational Objectives (PEOs)
PEO1: Be successful in their professional career, higher studies and research by
providing contextually relevant academics environment.

PEO2: Be committed citizens with social and professional concern.

PEO3: Demonstrate leadership qualities and managerial skills in heterogeneous

globally.

PEO4: Be independent lifelong learns to keep the pace of technological change and
industry expectations.

Program Specific Outcomes (PSOs)

PSO1: Apply the concepts of the VLSI, signals processing, Embedded systems,
Communication and Networking in the design and Implementation of
application-oriented engineering systems.

PSO2: Solve engineering problems using Hardware and Software tools and develop
excellent communication skills alongside.

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 Program Outcomes as defined by NBA
(POs)

Engineering Graduates will be able to:

• Engineering knowledge: Apply the knowledge of mathematics, science,
engineering fundamentals, and an engineering specialization to thesolution
of complex engineering problems.
• Problem analysis: Identify, formulate, review research literature, and
analyze complex engineering problems reaching substantiated conclusions
using first principles of mathematics, natural sciences, and engineering
sciences.
• Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that meet
the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
• Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis
and interpretation of data, and synthesis of the information to provide valid
conclusions.
• Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
• The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineeringpractice.
• Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and
demonstrate the knowledge of, and need for sustainable development.
• Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
• Individual and team work: Function effectively as an individual, and asa
member or leader in diverse teams, and in multidisciplinary settings.

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• Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such as,
being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear
instructions.
• Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply
these to one’s own work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
• Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest
context of technological change.

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 Course Objectives
This course will enable students to:

• Design, model, simulate and verify CMOS digital circuits

• Design layouts and perform physical verification of CMOS digital circuits
• Perform ASIC design flow and understand the process of synthesis, synthesis
constraints and evaluating the synthesis reports to obtain optimum gate level net list.
• Perform RTL-GDSII flow and understand the stages in ASIC design.

Course Outcomes
At the end of the course, the students will be able to

C407.1: Design i) CMOS Inverter ii) NAND gate iii) Common Source amplifier with given
specifications and analyze parameters.

C407.2: Design a two stage operational amplifier with the given specifications and analyze
various parameters.

C407.3: Construct a Verilog code for the counters and adder circuits and verify their test
bench .

C407.4: Synthesize verilog code for UART and ALU design.

C407.5: Construct a verilog code for Sequential circuits and verify their test bench.

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 Mapping of CO-PO-PSO
Program Specific
Course Program Outcomes (POs) Outcomes (PSOs)
Outcomes
(CO)

PO12
PO10

PO11
PO1

PO8
PO7
PO4

PO6

PO9
PO2

PO3

PO5
PSO1 PSO2

1 1 2 1 2 - - 1 1 1 - 1 1 1
C407.1

1 1 2 1 2 - -- 1 1 1 -- 1 1 1
C407.2

1 1 2 1 2 - - 1 1 1 - 1 1 1
C407.3

1 1 2 1 2 - - 1 1 1 - 1 1 1
C407.4

1 1 2 1 2 - - 1 1 1 - 1 1 1
C407.5

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 Do’s and Don’ts in the Laboratory

Do’s
• Do log off the computer when you finish the work.

• Bring observation, manual, pen etc, with you.

• Do ask the staff for assistance if you need help.

• You should be in time in lab.

• Do keep your voice low when speaking to others in the lab.

• All users of the laboratory are to follow the directions of the faculty.

• Before leaving lab, you should save your work, collect your belongings.

Don’ts
• Do not eat or drink in the laboratory

• Do not use pen drive or similar kind devices without permission.

• Do not take your baggage inside

• Do not change computer preference settings or endeavor to hack into

unauthorized areas

• Do not install any programs without the faculty permission.

• Do not create any user accounts without faculty permission.

• Avoid stepping on electrical wires or any other computer cables.

• Do not touch, connect or disconnect any plug or cable without your lecturer/
laboratory technician’s permission

• Do not misbehave in the computer laboratory.

• Don’t use chat rooms, online games or multiuser domains.

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 LIST OF EXPERIMENTS

Part – A
Analog Design
Use any VLSI design tools to carry out the experiments, use library files and
technology files below 180 nm.

1. a) Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology. Carry out the
following:
a. Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and time
period of 20ns and plot the input voltage and output voltage of designed inverter?
b. From the simulation results compute tpHL, tpLH and td for all three geometrical settings of width?
c. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter?

1. b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

2. a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that of CMOS
inverter computed in experiment 1. Verify the functionality of NAND gate and also find out the delay
td for all four possible combinations of input vectors. Table the results. Increase the drive strength to
2X and 4X and tabulate the results.

2. b) Draw layout of NAND with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

3. a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its
transient response and AC response? Measures the Unity Gain Bandwidth (UGB), amplification factor
by varying transistor geometries, study the impact of variation in width to UGB.

3. b) Draw layout of common source amplifier, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

4. a) Capture schematic of two-stage operational amplifier and measure the following:

a. UGB
b. dB bandwidth
c. Gain margin and phase margin with and without coupling capacitance
d. Use the op-amp in the inverting and non-inverting configuration and verify its functionality
e. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the stage wise
transistor geometries and record the observations.

4. b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in
180/90/45 nm technology), choose appropriate transistor geometries as per the results obtained in 4.a.
Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post layout
simulations, compare the results with pre-layout simulations. Record the observations.

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 Part - B
Digital Design
Carry out the experiments using semi-custom design flow or ASIC design flow,
use technology library 180/90/45nm and below
Note: The experiments can also be carried out using FPGA design flow, it is
required to set appropriate constraints in FPGA advanced synthesis options

1. Write Verilog code for 4-bit up/down asynchronous reset counter and carry out the following:
a. Verify the functionality using test bench
b. Synthesize the design by setting area and timing constraint. Obtain the gate level netlist, and find the
critical path and maximum frequency of operation. Record the area requirement in terms of number of
cells required and properties of each cell in terms of driving strength, power and area requirement.
c. Perform the above for 32-bit up/down counter and identify the critical path,

2. Write verilog code for 4-bit adder and verify its functionality using test bench. Synthesize
the design by setting proper constraints and obtain the net list. From the report generated
identify critical path, maximum delay, total number of cells, power requirement and total area
required. Change the constraints and obtain optimum synthesis results.

3. Write verilog code for UART and carry out the following:
a. Perform functional verification using test bench
b. Synthesize the design targeting suitable library and by setting area and timing constraints
c. For various constrains set, tabulate the area, power and delay for the synthesized netlist
d. Identify the critical path and set the constraints to obtain optimum gate level netlist with
suitable constraints

4. Write verilog code for 32-bit ALU supporting four logical and four arithmetic operations,
use case statement and if statement for ALU behavioral modeling.
a. Perform functional verification using test bench
b. Synthesize the design targeting suitable library by setting area and timing constraints
c. For various constrains set, tabulate the area, power and delay for the synthesized netlist
d. Identify the critical path and set the constraints to obtain optimum gate level netlist with suitable
constraints

Compare the synthesis results of ALU modeled using IF and CASE statements.

5. Write verilog code for Latch and Flip-flop, Synthesize the design and compare the synthesis report
(D, SR, JK).

6. For the synthesized netlist carry out the following for any two above experiments:
a. Floor planning (automatic), identify the placement of pads
b. Placement and Routing, record the parameters such as no. of layers used for routing, flip method for
placement of standard cells, placement of standard cells, routes of power and ground, and routing of
standard cells
c. Physical verification and record the LVS and DRC reports
d. Perform Back annotation and verify the functionality of the design
e. Generate GDSII and record the number of masks and its color composition

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GENERAL NOTES

Before starting to work on a design, create a Workspace (Folder) for the project individually.

WORK SPACE CREATION:

Make a right click on the Desktop and select the option “New Folder” as shown in Figure - 1.

Figure – 1: Workspace Creation

Name the folder (for example: VTU_LAB_EXP) and click on “Create” as shown in
Figure -2.

Figure – 2: Name the Folder

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Figure – 3: Open the folder

INITIALISING csh & SOURCING cshrc:

Make a right click and select “Open in Terminal” as shown in Figure - 4.

Figure – 4: Open in Terminal

Type the command “csh” to initialize shell and source the “cshrc” file with the command
“source /home/install/cshrc”. “cshrc” file will provide the details of the installation directory
of the Cadence Tools.

Figure – 5: “csh” and “source /home/install/cshrc” commands

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INVOKING VIRTUOSO:
After sourcing the “cshrc” file, click on “Enter” on the keyboard. The welcome screen with
the text “Welcome to Cadence Tools Suite” can be seen as shown in Figure - 5.

Figure - 6: Welcome screen

Invoke virtuoso using the command “virtuoso &” or “virtuoso” as shown in Figure – 7 and
click on “Enter” in the keyboard.

Figure - 7: Command to invoke “virtuoso”

The Virtuoso “Command Interpreter Window (CIW)” can be seen as shown in Figure - 8.

Figure – 8: Command Interpreter Window (CIW)

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LAB – 01: CMOS INVERTER

Objective:
(a) Capture the Schematic of a CMOS Inverter with Load Capacitance of 0.1 pF and set
the Widths of Inverter with
(i) WN = WP
(ii) WN = 2 WP
(iii) WN = WP / 2
and Length at selected Technology. Carry out the following:
1. Set the Input Signal to a pulse with Rise Time, Fall Time of 1 ps and Pulse Width
of 10 ns, Time Period of 20 ns and plot the input voltage and output voltage of the
designed Inverter
2. From the Simulation Results, compute tpHL, tpLH and tPD for all the three geometrical
settings of Width
3. Tabulate the results of delay and find the best geometry for minimum delay for
CMOS Inverter

Solution:
(a) Schematic Capture of CMOS Inverter

CREATE A LIBRARY:
To create a New Library, select “Tools → Library Manager” from the top menu as shown
in Figure – 1.1.

Figure – 1.1: Tools → Library Manager

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The Cadence Library Manager shows up as in Figure – 1.2.

Figure – 1.2: Library Manager

Select “File → New → Library” from the top menu as shown in Figure – 1.3.

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 Figure – 1.3: File → New → Library

A “New Library” window will show up as in Figure – 1.4. Name the Library (for eg:
VTU_LAB_MANUAL_180nm) and click on “OK”.

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 Figure – 1.4: Name the Library

Select “Technology File..” tab that keeps blinking at the bottom of the screen as shown in
Figure – 1.5 to map the New Library to a technology node based on the specification.

Figure – 1.5: “Technology File..” Tab

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Click on the tab and “Technology File for New Library” window can be seen as in Figure –
1.6. Select “Attach to an existing technology library” and click on “OK”.

Figure – 1.6: Technology File for New Library form

From the list of available Technology Libraries, select the respective Technology Node as
shown in Figure – 1.7 (for example: gpdk180) and click on “OK”.

Figure – 1.7: Technology Node Selection

The New Library can be verified from the Library Manager under “Library” column as shown
in Figure – 1.8.

Figure – 1.8: New Library included to Library Manager

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CREATE A CELLVIEW:
To create a Cellview within a Library, select the respective library as shown in Figure – 1.9.

Figure – 1.9: Select the Library

Select File → New → Cell View as shown in Figure – 1.10.

Figure – 1.10: File → New → Cell View

A “New File” window can be seen as shown in Figure – 1.11.

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 Figure – 1.11: “New File” Window

Name the Cell and click on “OK”. A blank “Virtuoso Schematic Editor L Editing” window
can be seen as shown in Figure – 1.12.

Figure – 1.12: Virtuoso Schematic Editor

(i) SCHEMATIC CAPTURE FOR THE CMOS INVERTER

To complete the Schematic for a CMOS Inverter with WN = WP, components have to be
included to the blank Virtuoso Schematic Editor window. These components are called
Instances. The procedure to include the components to the Schematic are given below.

ADD AN INSTANCE:
Select “Create → Instance” as in Figure – 1.13 (or) use the bind key ‘I’ (or) the icon as in
Figure – 1.13.

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 Create Instance

Figure – 1.13: Create → Instance

The “Add Instance” form can be seen as shown in Figure – 1.14.

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 Figure – 1.14: “Add Instance” Window

Click on the drop down close to the Browse option as shown in Figure – 1.14. Select the
Technology Node from the list of libraries. Similarly, click on the drop down next to Cell and
select the required device from the list. For the CMOS Inverter circuit, PMOS and NMOS
transistors are required. The parameters for the devices as given in the requirement are
considered as in Table – 1, Table – 2 and Table – 3.
Table – 1: Length and Width of NMOS and PMOS Transistors for the condition WN = WP
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 850 n
Length, L = 180 n
gpdk180 Pmos Width, WP = 850 n
Length, L = 180 n

Table – 2: Length and Width of NMOS and PMOS Transistors for the condition
WN = 2 * WP
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 Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 850 n
Length, L = 180 n
gpdk180 Pmos Width, WP = 1.7 u
Length, L = 180 n
Table – 3: Length and Width of NMOS and PMOS Transistors for the condition
WN = WP / 2
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 850 n
Length, L = 180 n
gpdk180 Pmos Width, WP = 425 n
Length, L = 180 n

Type the parameters and click on “Hide”. The device can be seen as shown in Figure – 1.15.

Figure – 1.15: Instance after Selection

Make a left mouse click to place it on the Schematic Editor. The device after placement on the
Schematic Editor can be seen as shown in Figure – 1.16. Similarly, other components can be
instantiated.

Figure – 1.16: Instance after left mouse click

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ADD PIN:
To include pins to the schematic, select “Create → Pin” from the top menu (or) use the bind
key ‘P’ (or) use the icon from the top menu as shown in Figure – 1.17.

Create Pin

Figure – 1.17: Create → Pin

The “Create Pin” window pops up as shown in Figure – 1.18.

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 Figure – 1.18: Create Pin window

Name the pins by separating them with “space”, choose its direction and click on “Hide” as
shown in Figure – 1.19(a) and Figure – 1.19(b).

Figure – 1.19(a): Naming the Input Pins Figure – 1.19(b): Naming the Output Pins

The pins are visualized on the Schematic Editor as shown in Figure – 1.20.

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 Figure – 1.20: Pins after left mouse click on “Hide”

Place the pins on the Schematic Editor using a left mouse click and the pins after placement
can be visualized as shown in Figure – 1.21.

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 Pin → Before Placement

Pin → After Placement

Figure – 1.21: Pins Before and After Placement

Use the bind key “R” to rotate the pins and it can be done either before or after Pin Placement.
The direction of the pins before and after rotation are shown in Figure – 1.22.

Pins → After Rotation

Pins → Before Rotation

Figure – 1.22: Pins Before and After Rotation

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The Schematic Editor window after pin placement is shown in Figure – 1.23.

Figure – 1.23: Schematic Editor after pin placement

ADD WIRE:
For connecting the pins and the terminals, click on “Create → Wire” from the top menu (or)
use the bind key ‘W’ (or) the icon from the top menu as shown in Figure – 1.24.

Create Wire

Figure – 1.24: Create → Wire

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Use the left mouse click to start / complete the wire from one terminal / pin to another. The
complete Schematic after connecting the pins and terminals for all the three conditions WN =
WP, WN = 2 * WP, WN = WP / 2 is shown in Figure – 1.25(a), 1.25(b) and 1.25(c) respectively.

Figure – 1.25(a): WN = WP Figure – 1.25(b): WN = 2 * WP

Figure – 1.25(c): WN = WP / 2

CHECK AND SAVE THE DESIGN:

It is mandatory to save the design before we move ahead to the Simulation and there are two
options, “Save” and “Check and Save” as in Figure – 1.26.

Check and Save Save

Figure – 1.26: “Check and Save” and “Save” option

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“Save” option saves the design as it is and “Check and Save” option checks for discontinuities like
floating net or terminal and provides the “error” or “warning” messages accordingly and then saves
the design. Sample message can be seen in the “Command Interpreter Window” as shown in
Figure – 1.27.

Figure – 1.27: Message after selecting “Check and Save”

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 SYMBOL CREATION:
A Symbol view is very important in a design process to make use of a Schematic in a hierarchy.
To create a symbol, select “Create → Cellview → From Cellview” from the top menu as
shown in Figure – 1.28.

Figure – 1.28: Create → Cellview → From Cellview

Verify the Library Name, Cell Name, From View Name, To View Name, etc., as shown in
Figure – 1.29 and Click on “OK

Figure – 1.29: “Cellview From Cellview” window

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The “Symbol Generation Options” window can be seen as shown in Figure – 1.30.

Figure – 1.30: “Symbol Generation Options” window

The pin location on the symbol can be fixed using the options Left Pins, Right Pins, Top Pins
and Bottom Pins. Assign the pins and click on ‘OK’ as shown in Figure – 1.31.

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 Figure – 1.31: “Symbol Generation Options” window

The “Virtuoso Symbol Editor” window pops up with a default symbol based on the Pin
Assignment as shown in Figure – 1.32.

Create Circle Create Polygon Create Ellipse Create Line Create Arc

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 Drawing To

Figure – 1.32: “Virtuoso Symbol Editor” window with default symbol

SYMBOL MODIFICATION:
The symbol can be modified using the drawing tools from the top menu as shown in Figure –
1.32.
To modify the symbol, remove the inner rectangle (green), highlighted in Figure – 1.33(a). To
remove the inner rectangle (green), place the mouse pointer within and make a left mouse click
to select the entire rectangle as shown in Figure – 1.33(b). Click on ‘Delete’ in the keyboard to
remove the rectangle as shown in Figure – 1.33(c).

Figure – 1.33(a) Figure – 1.33(b) Figure – 1.33(c)

Figure – 1.33(a): Inner Rectangle Highlighted, Figure – 1.33(b): Inner Rectangle
Selected, Figure – 1.33(c): Inner Rectangle Deleted

Since the focus is to design an Inverter, to create a triangle, use the “Create Line” option as
shown in Figure – 1.32. Use the same procedure as “wiring the schematic” to create the triangle.

The symbol, after creating the triangle can be seen as shown in the Figure – 1.34.

Figure – 1.34: Symbol after creating the Triangle

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To create a bubble, use “Create Circle” option as shown in Figure – 1.32, place the mouse
pointer
at the center between the ‘Triangle’ and the ‘Output Pin’, make a left mouse click and expand
the circle and make a left mouse click to fix its size as shown in Figure – 1.35. Click on “Check
and Save” option to ‘Save’ the symbol

Figure – 1.35: Customized Symbol of an Inverter

(1) TEST CIRCUIT FOR SIMULATION:

The Test Circuit can be created using the symbol created in the previous section. To create a
test circuit, create a “New Cellview” with a different “Cell Name” as shown in Figure – 1.36.

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Figure – 1.36: New Cellview for Test Circuit

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Use the “Add Instance” option, select the respective Library, Cell and View as in Figure –
1.37 to instantiate the symbol.

Figure – 1.37: Symbol Instantiation for the Test Circuit

The remaining devices to be included on the Schematic and its properties are given below in
Table - 4.
Table – 4: Properties of vdc, vpulse, cap and gnd
Library Name Cell Name Comments / Properties
analogLib Vdc DC voltage = 1.8 V
analogLib Vpulse Voltage 1 = 0 V, Voltage 2 = 1.8 V,
Period = 20n s, Delay time = 10n s, Rise
time = 1p s, Fall time = 1p s, Pulse width
= 10n s
analogLib Cap Capacitance = 100f F
analogLib Gnd

The screenshot of the device properties for the instances vdc, vpulse, cap and gnd are shown in
Figure – 1.38, Figure – 1.39, Figure – 1.40 and Figure – 1.41. The complete Test Schematic
after wiring is shown in Figure – 1.42.

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Figure – 1.38: Instantiating “vdc”

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Figure – 1.39: Instantiating “vpulse”

Figure – 1.40: Instantiating “cap”

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 Figure – 1.41: Instantiating “gnd”

The complete circuit after instantiating all the devices and interconnections is shown in Figure
– 1.42.

Figure – 1.42: Complete Test Schematic

To Label the nets, click on “L” in the keyboard. The “Create Wire Name” window pops up
as shown in Figure – 1.43. Name the nets, different net names can be mentioned at the same
instance of time by separating them with “Spaces”, same net names can also be repeated as per
the requirement and click on “Hide” as shown in Figure – 1.44.

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Figure – 1.43: Create Wire Name Window Figure – 1.44: Wire Names

The “Wire Name before placement” can be seen in Figure – 1.45. The “Dot” just under the
wire name has to be placed over the “wire” and make a left mouse click to fix it. The “Placed
Wire Name” can be seen in Figure – 1.45.

Placed Wire Name “Dot” on the wire name

Wire Name before placement

Figure – 1.45: Wire Name before and after its Placement

The complete schematic after placing all the wire names is shown in Figure – 1.46. “Check
and Save” the Test Schematic.

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 Figure – 1.46: Complete Test Schematic

FUNCTIONAL SIMULATION WITH SPECTRE:

To simulate the design and perform the DC Analysis and Transient Analysis for the CMOS
Inverter, click on “Launch → ADE L” from the top menu of the Test Schematic Cellview as
shown in Figure – 1.47.

Figure – 1.47: Launch → ADE L

The “ADE L” window pops up as shown in Figure – 1.48.

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 Figure – 1.48: ADE L Window

Before running the simulation, check for the Simulator and Model Libraries.

SELECTING THE SIMULATOR:

To select the Simulator, click on “Setup → Simulator/Directory/Host” as shown in Figure –
1.49.

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 Figure – 1.49: Setup → Simulator/Directory/Host..

The “Choosing Simulator/Directory/Host” window pops up. Select “Simulator → Spectre”

and click on “OK” as shown in Figure – 1.50.

Figure – 1.50: Simulator → Spectre

SELECTING THE MODEL LIBRARIES AND PROCESS CORNERS:

The Model Libraries and Process Corners are important to run the simulation.

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To select the “.scs” file with respect to the technology node, select “Setup → Model
Libraries” as shown in Figure – 1.51.

Figure – 1.51: Setup → Model Libraries

The “spectre0: Model Library Setup” window pops up as shown in Figure – 1.52.

Figure – 1.52: “spectre0: Model Library Setup” Window

Select the respective “.scs” file and make a double click under “Section” to select the
processing corner of interest using a Left Mouse Click on the drop down and click on “OK” as
shown in Figure – 1.53.

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 Figure – 1.53: “.scs” file and Processing Corner Selection

SELECTING THE ANALYSIS:

To select the analysis required to be performed on the Test Circuit, select “Analyses →
Choose” from the top menu in the ADE L window as shown in Figure – 1.54.

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 Figure – 1.54: Analyses → Choose

The “Choose Analyses – ADE L” window pops up as shown in Figure – 1.55.

48
 Figure – 1.55: “Choosing Analysis – ADE L” Window

TRANSIENT ANALYSIS:
To set up a “Transient Analysis”, select “tran”, mention the “Stop Time” (for example:
100n), select “Accuracy Defaults” (for example: moderate), click on “Apply” and click on
“OK” as shown in Figure – 1.56.

Figure – 1.56: Setup for Transient Analysis

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The selected analysis and the arguments can be seen under the “Analyses” tab in the ADE L
window as shown in Figure – 1.57.

Figure – 1.57: Chosen Analysis in the ADE L window

DC ANALYSIS:
To set up a “DC Analysis”, select “dc” and enable “Save DC Operating Point” as shown in
Figure – 1.58.

Figure – 1.58: Select “dc”

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Enable “Component Parameter”, click on “Select Component” as shown in Figure – 1.59.

Figure – 1.59: Enable “Component Parameter”

Select the “vpulse” source from the Test Schematic as shown in Figure – 1.60.

Figure – 1.60: Selecting “vpulse” from the Test Schematic

51
Select “DC Voltage” from the list of parameters as shown in the “Select Component
Parameter” window and click on “OK” as shown in Figure – 1.61.

Figure – 1.61: “Select Component Parameter” window

From the “Sweep Range” option, select “Start-Stop” and mention the “Start” value as “0”
and “Stop” value as “1.8”, click on “Apply” and click on “OK” as shown in the Figure – 1.62.

52
 Figure – 1.62: Mention the Sweep Range

The ADE L window is now updated as shown in Figure – 1.63.

53
 Figure – 1.63: Updated ADE L window

SELECTING THE SIGNALS TO BE PLOTTED:

To select the signals to be plotted, select “Outputs → Setup” from the ADE L window as
shown in Figure – 1.64.

Figure – 1.64: Outputs → Setup

The “Setting Outputs – ADE L” window pops up as shown in Figure – 1.65.

54
 Figure – 1.65: Setting Outputs – ADE L window

Click on “From Design” as shown in the Figure – 1.65. This brings back the Test Schematic
as shown in Figure – 1.66.

Net “IN” Net “OUT”

Figure – 1.66: Select the Net “IN” and Net “OUT”

Select the Input Net “IN” and the Output Net “OUT” as shown in Figure – 1.66. The selected
Nets will be listed under “Table of Outputs” in the “Setting Outputs – ADE L” window as
shown in Figure – 1.67. Click on “OK”.

Figure – 1.67: Updated “Setting Outputs” window

55
The “Outputs” column in the “ADE L” window will be updated as shown in Figure – 1.68.

Figure – 1.68: “Outputs” in ADE L window

RUNNING THE SIMULATION:

To run the simulation, click on “Simulation → Netlist and Run” from ADE L window as
shown in Figure – 1.69.

56
 Figure – 1.69: Simulation → Netlist and Run

The simulated waveforms can be seen on the “Virtuoso Visualization and Analysis XL”
window as shown in Figure – 1.70.

Figure – 1.70: Simulated waveforms

57
The Input and Output Signals can be split up by selecting “Graph → Split All Strips” as in
Figure – 1.71.

Figure – 1.71: Graph → Split All Strips

SAVING THE ADE L STATE:

To save the current ADE L state, click on “Session → Save State” as shown in Figure – 1.72.

Figure – 1.72: Session → Save State

58
The “Saving State – ADE L” window pops up. Select the “Save State Option → Cellview”
and click on “OK” as shown in Figure – 1.73.

Figure – 1.73: Saving State

The Test Schematic and the State can be seen in the Library Manager as shown in Figure –
1.74.

59
 Figure – 1.74: Test Schematic and State in Library Manager

OPEN THE SAVED ADE L STATE:

To open the saved state, click on “Session → Load State” as shown in Figure – 1.75.

Figure – 1.75: Session → Load State

60
The “Loading State – ADE L” window pops up. Select the “Load State Option → Cellview”
and click on “OK” as shown in Figure – 1.76.

Figure – 1.76: “Loading State – ADE L” window

The Saved ADE L state is loaded as shown in Figure – 1.77.

Figure – 1.77: Reloaded ADE L State

61
CALCULATION OF tpHL, tpLH AND tPD:
To calculate the Propagation Delay (𝑡𝑃𝐷), the formula used is
(𝑡𝑝𝐿𝐻 + 𝑡𝑝𝐻𝐿)
𝑡𝑃𝐷 =
2
where, 𝑡𝑝𝐿𝐻 → Low – High Propagation Delay and 𝑡𝑝𝐻𝐿 → High – Low Propagation Delay.
To calculate 𝑡𝑝𝐿𝐻 and 𝑡𝑝𝐻𝐿 use the Calculator option from the “Virtuoso (R) Visualization
and Analysis” window. So, select “Tools → Calculator” or click on the icon as shown in
Figure – 1.78.

“Calculator” option

Figure – 1.78: Tools → Calculator

The “Virtuoso (R) Visualization and Analysis XL calculator” window pops up as shown in
Figure – 1.79.

62
 Figure – 1.79: Virtuoso (R) Visualization and Analysis XL calculator window

“Enable → Wave” and “Disable → Clip” as shown in Figure – 1.80.

Figure – 1.80: “Enable → Wave” and “Disable → Clip”

Select “delay” from the “Function Panel” as shown in Figure – 1.80. The “Function Panel”
gets updated as shown in Figure – 1.81.

63
 Figure – 1.81: Updated Function Panel

Place the cursor in “Signal 1”, select the signal “IN” from the waveform window as shown in
Figure – 1.82.

64
 Figure – 1.82: Selecting “IN” signal from the waveform

Similarly, place the cursor in “Signal 2” and select the “OUT” signal. The Function Panel gets
updated as shown in Figure – 1.83.

Evaluate the Buffer and display the results in a table

Figure – 1.83: “Signal 2” and other parameter selection

65
The value of “Switching Potential” should be mentioned under “Threshold Value 1” and
“Threshold Value 2”.

Note:
What is Switching Potential?
Switching Potential is defined as the value of Input Voltage for which the Output
Voltage is equal to the Input Voltage.

How to obtain the value of Switching Potential?

To obtain the Switching Potential, use the “intersect” option from the Function Panel,
select the “Signal 1” and “Signal 2” from the DC Analysis waveform window, click
on “Apply”, click on “OK” and click on “Evaluate the buffer and display the results
in a table” icon as shown in Figure – 1.83 to obtain the value.

Select “Edge Number 1” and “Edge Number 2” as “2” (for example). Select “Edge Type 1
→ falling” and “Edge Type 2 → rising” to obtain the value of “𝒕𝒑𝑳𝑯” and “Edge Type 1 →
rising” and “Edge Type 2 → falling” to obtain the value of “𝒕𝒑𝑯𝑳”.
After the above mentioned selections, click on “Apply” and click on “OK” to see the “Buffer”
window in the calculator getting updated as shown in Figure – 1.84.

Updated Buffer

Figure – 1.84: Updated Buffer

Click on the icon “Evaluate the buffer and display the results in a table” as shown in Figure
– 1.83 to obtain the value of 𝒕𝒑𝑯𝑳 / 𝒕𝒑𝑳𝑯. Use the formula mentioned above to obtain the 𝒕𝑷𝑫.

66
Obtain the values of 𝒕𝒑𝑯𝑳, 𝒕𝒑𝑳𝑯 and 𝒕𝑷𝑫 for all the three geometrical settings of Width.

(2) TABULATED VALUES OF DELAY:

The results of 𝒕𝒑𝑯𝑳, 𝒕𝒑𝑳𝑯 and 𝒕𝑷𝑫 for all the required geometrical settings are tabulated below
in Table – 5.
Table – 5: Values of 𝒕𝒑𝑯𝑳, 𝒕𝒑𝑳𝑯 and 𝒕𝑷𝑫 for different geometries

40
(b) Layout of CMOS Inverter with 𝑊𝑃 =
𝑊𝑁 20

Objective:
40
To draw the Layout of CMOS Inverter with 𝑊𝑃 = using optimum Layout Methods. Verify
𝑊𝑁 20
for DRC and LVS, extract the Parasitics and perform the Post-Layout Simulations, compare
the results with Pre-Layout Simulations and record the observations.
SCHEMATIC CAPTURE:
Create a New Library, Create a Cellview and instantiate the required devices through “Create
→ Instance” option. The parameter for PMOS and NMOS Transistors are listed in Table – 6
shown below.
Table – 6: Parameters for NMOS and PMOS Transistors
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 20 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 40 u
Length, L = 180 n

Follow the techniques demonstrated in Lab – 01 to complete the Schematic. The completed
CMOS Inverter circuit is shown in Figure – 1.85.

67
 𝟒𝟎
Figure – 1.85: Schematic for CMOS Inverter with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

The symbol for the CMOS Inverter is shown in Figure – 1.86.

𝟒𝟎
Figure – 1.86: Symbol for CMOS Inverter with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

Create a New Cellview and capture the Test Schematic using the symbol shown in Figure –
1.86. The Test Schematic is shown in Figure – 1.87.

68
 𝟒𝟎
Figure – 1.87: Test Schematic for CMOS Inverter with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

The parameters for “vdc”, “vpulse” and the “capacitor” are the same as shown in Table – 4.
Check and Save the design.
SIMULATION:
Launch the ADE L window from the Test Circuit, setup the Simulator, Model Libraries and
the Process Corner as shown in Figure – 1.50, Figure – 1.52 and Figure – 1.53.
Setup the DC Analysis and Transient Analysis through the “Choose → Analysis” option and
the parameters are the same as shown in Figure – 1.56, Figure – 1.58 and Figure – 1.62.
Select the signals to be plotted and the updated ADE L window is shown in Figure – 1.88.

69
 Figure – 1.88: Updated ADE L window

The signals plotted as a result of Transient Analysis is shown in Figure – 1.89.

𝟒𝟎
Figure – 1.89: Transient Analysis for CMOS Inverter with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

70
Similarly, the signals plotted after DC Analysis are shown in Figure – 1.90.

𝟒𝟎
Figure – 1.90: DC Analysis for CMOS Inverter with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

VALUES OF 𝒕𝒑𝑯𝑳, 𝒕𝒑𝑳𝑯 AND 𝒕𝑷𝑫:

Obtain the values of 𝒕𝒑𝑯𝑳, 𝒕𝒑𝑳𝑯 and 𝒕𝑷𝑫 by referring to “CALCULATION OF tpHL, tpLH
AND tPD” in the previous section. The values are tabulated as shown in Table – 7. 𝟒𝟎
Table – 7: Values of 𝒕𝒑 , 𝒕𝒑 and 𝒕 for CMOS Inverter with 𝑾𝑷 =
𝑯𝑳 𝑳𝑯 𝑷𝑫 𝑾𝑵 𝟐𝟎

71
 𝟒𝟎
LAYOUT FOR CMOS INVERTER WITH 𝐖𝐏 = :
𝐖𝐍 𝟐𝟎
From the Virtuoso Schematic Editor as shown in Figure – 1.85, select “Launch → Layout
XL” as shown in Figure – 1.91.

Figure – 1.91: Launch → Layout XL

The “Startup Option” window pops up as shown in Figure – 1.92. Select “Layout → Create
New” and “Configuration → Automatic” and click on “OK”.

Figure – 1.92: Startup Option

72
The “New File” window pops up. Verify the Library Name and Cell Name. “View” and “Type”
should be “layout”. Click on “OK” as shown in Figure – 1.93.

Figure – 1.93: New File window

The “Virtuoso Layout Suite XL Editing” window pops up as shown in Figure – 1.94. Click
on “F” to fit the cross wire to the center of the Virtuoso Layout Editor.

73
 Figure – 1.94: Virtuoso Layout Suite XL Editing

Note:
We have created a Template for gpdk180.
To instantiate all the devices from the Virtuoso Schematic Editor, select “Connectivity →
Generate → All From Source” as shown in Figure – 1.95.

74
 Figure – 1.95: Connectivity → Generate → All From Source

The “Generate Layout” window pops up. Click on “OK” as shown in Figure – 1.96.

Figure – 1.96: Generate Layout window

The Virtuoso Layout Editor gets updated as shown in Figure – 1.97.

75
 Figure – 1.97: Updated Virtuoso Layout Editor

To view the terminals of the devices, click on “Shift + F” and the devices in the Virtuoso
Layout Editor gets updated as shown in Figure – 1.98.

PR – Boundary
PR → Placement & Routing

Figure – 1.98: Updated devices after “Shift + F”

76
The blue colored box that is seen in the Layout is the PR – Boundary (PR → Placement and
Routing). Since the devices have to be fixed within the size of the Template, the properties of
NMOS and PMOS transistors have to be changed.
To change the device properties, select the device using a Left Mouse Click (for eg: NMOS
transistor) and it gets highlighted as shown in Figure – 1.99.

NMOS Transistor getting

highlighted after a Left
Mouse Click

Figure – 1.99: NMOS Transistor after Left Mouse Click

To edit the device properties, use a Right Mouse Click and select “Properties” as shown in
Figure – 1.100 (or) use the bind key “Q”.

Figure – 1.100: Select “Properties” after a Right Mouse Click

The “Edit Instance Properties” window pops up as shown in Figure – 1.101.

77
 Figure – 1.101: Edit Instance Properties window

Click on “Parameter” tab to visualize the parameters of the selected device (for example:
NMOS transistor) like Length, Multiplier, Total Width, Finger Width, Fingers and most
importantly Bodytie Type as shown in Figure – 1.102. Initially, the “Bulk” won’t be included
to the layout view of Transistors and the “Bodytie Type” option helps in including that.

78
 Figure – 1.102: Parameter tab before update

The Parameter tab after updating the values is shown in Figure – 1.103.

79
 Figure – 1.103: Parameter tab after updating the values for NMOS transistor

In order to fix the device within the Template, the parameter “Finger → 20” and “Finger
Width → 1u” are changed but the “Total Width” should remain the same. The “Bodytie Type
→ Integrated” option will have the Bulk terminal integrated to the Source terminal of the
device on the left side “Left Tap” of the device. Click on “OK” and the device gets updated
as shown in Figure – 1.104.

Figure – 1.104: Updated NMOS Transistor

Similarly, the parameters for the PMOS transistors are given as “Finger → 20”, “Finger
Width → 2u” and “Bodytie Type → Integrated”. The updated parameter tab is shown in
Figure – 1.105.

80
 Figure – 1.105: Parameter tab after updating the values for PMOS transistor

Click on “OK” and the device gets updated as shown in Figure – 1.106.

Figure – 1.106: Updated PMOS Transistor

To have an idea of the interconnections, select the layout using “Ctrl + A”. The entire layout
gets highlighted as shown in Figure – 1.107.

Figure – 1.107: Selecting the layout using “Ctrl + A”

81
Select “Connectivity → Incomplete Nets → Show/Hide Selected..” as shown in Figure –
1.108.

Figure – 1.108: Connectivity → Incomplete Nets → Show/Hide Selected..

The layout gets updated as shown in Figure – 1.109. The lines visible in the layout are called
the Rat Lines. These lines give an idea about the missing interconnections in the layout.

Rat Lines

Figure – 1.109: Layout with Rat Lines

82
Use the bind key “P” for the interconnections. After the click on “P” in the keyboard, if the
mouse pointer is taken close to the terminals in the transistor, it gets highlighted as shown in
Figure – 1.110.

Terminal getting highlighted

Figure – 1.110: Terminal getting highlighted

Use Left Mouse Click to start the interconnection from the terminal as shown in Figure – 1.111.
The option “Rectangle” with bind key “R” can also be used for interconnections. In case of
“Rectangle” option, select the respective layer from the “Layer Palette” as shown in Figure –
1.110 and then click on “R” in the keyboard, use Left Mouse Click to draw the respective
layers. Similarly, use the option “Shift + P” to create “Polygon” which is useful in creating the
layers in different shapes other than Rectangle and Square.

83
 Figure – 1.111: Start of Interconnection after Left Mouse Click

Use the Left Mouse Click at the point where the interconnection has to end. The layout is
updated as shown in Figure – 1.112.

84
 Figure – 1.112: Layout after the interconnections

Repeat the steps to complete the remaining connections in the layout.

For interconnections between two different layers, use a “Via”. Via has to be selected according
to the layers present at the Start and End of the interconnections. To include a Via in the layout,
select “Create → Via” as shown in Figure – 1.113.

Figure – 1.113: Create → Via

The “Create Via” window pops up as shown in Figure – 1.114.

85
 Figure – 1.114: Create Via window

The required Via can be selected through the “Via Definition” option as shown in Figure –
1.114. Click on the drop down and select the required Via. For example, in the CMOS Inverter
design, the Input pin “A_IN” is of Metal 1 layer and it has to be connected to the Gate terminal
of PMOS and NMOS Transistors which is a Poly layer. So, from the Via Definition,
M1_POLY1 is selected as shown in Figure – 1.114. Click on “Hide” to visualize the Via on
the Virtuoso Layout Editor as shown in Figure – 1.115. Use a Left Mouse Click to place the
Via.

M1_POLY1 Via

Figure – 1.115: Selected Via

86
Use the bind key “P” to complete the connections between the Input Pin and Via and between
Via and Gate Terminal of the transistor. The completed layout can be visualized as shown in
Figure – 1.116(a).

Figure – 1.116(a): Completed Layout

With the Template shown, the layout can be visualized as shown in Figure – 1.116(b).

Figure – 1.116(b): Completed Layout with Template

Click on “File → Save” to Save the layout.

PHYSICAL VERIFICATION WITH ASSURA:
Physical Verification involves DRC (Design Rule Check) and LVS (Layout versus Schematic)
checks on the layout. These checks are performed using Assura.
TECHNOLOGY LIBRARY (assura_tech.lib) MAPPING:
To map the library file, select “Assura → Technology..” as shown in Figure – 1.117.

87
 Figure – 1.117: Assura → Technology..

`The “Assura Technology Lib Select” window pops up as shown in Figure – 1.118.
Browse

Figure – 1.118: Assura Technology Lib Select

Click on “Browse” option as shown in Figure – 1.118. The “File Selector” window pops up
as shown in Figure – 1.11

88
 Figure – 1.119: File Selector window

Click on the “Browse” as shown in Figure – 1.119 to select the file “assura_tech.lib” from the
location “/home/install/FOUNDRY/analog/180nm/ ”. Once a double-mouse click in done on
“assura_tech.lib”, the path gets completed as shown in Figure – 1.120. Click on “OK”.

Figure – 1.120: Assura Technology Lib Select window after file selection

DRC (DESIGN RULE CHECK):

To run DRC check using Assura, select “Assura → Run DRC” as shown in Figure – 1.121.

89
 Figure – 1.121: Assura → Run DRC

The “Run Assura DRC” window pops up as shown in Figure – 1.122.

90
 Figure – 1.122: Run Assura DRC window

Check for the “Layout Design Source”, mention a “Run Name” (it can be any name) and
select “Technology → gpdk180” from the drop down and click on “OK” as shown in Figure
– 1.122. The “Progress” window pops up as shown in Figure – 1.123.

Figure – 1.123: “Progress” window

Once the DRC check is over, we get the DRC check completion window as shown in Figure –
1.124.

91
 Figure – 1.124: DRC Check completion window

Click on “Yes” to get the results of DRC Check as shown in Figure – 1.125.

Figure – 1.125: Result of DRC Check if the layout is DRC clean

In case of errors, the error information will be shown. If the error is selected, it points out the
issue which has to be reworked on the layout. Once done, Save the layout and re-run the DRC
check to make sure that the layout is DRC clean.

LVS (LAYOUT VERSUS SCHEMATIC):

To run the LVS check using Assura, select “Assura → Run LVS” as shown in Figure – 1.126.

92
 Figure – 1.126: Assura → Run LVS

The “Run Assura LVS” window pops up as shown in Figure – 1.127.

Figure – 1.127: Run Assura LVS window

93
Check for the correctness of the Schematic and Layout to be compared in the “Schematic
Design Source” and the “Layout Design Source”, mention a “Run Name” (it can be any
name but avoid space) and select the Technology (for example: gpdk180) as shown in Figure
– 136. Click on “OK”. The progress of “LVS” check can be seen as shown in Figure – 137.

Figure – 1.128: LVS “Progress” window

After the LVS check gets completed, the “Run: “1_lvs”” window pops up. In case of violations
in LVS check, the total number of violations can be seen as shown in Figure – 1.129. Since
there are no violations, it shows as “0”.

Figure – 1.129: “Run: “1_lvs”” window

94
Click on “Yes” to see the result in the “LVS Debug” window as shown in Figure – 1.130.

Figure – 1.130: “LVS Debug” window

Since the design is LVS clean, the message “Schematic and Layout Match” can be seen. In
case of violations, the respective messages are listed out.
QRC (RC / PARASITIC EXTRACTION):
The tool used for Parasitic Extraction process is “Quantus”. Select “Assura → Run Quantus”
as shown in Figure – 1.131 to invoke the tool and enter the “Quantus (Assura) Parasitic
Extraction Run Form”.

95
 Figure – 1.131: Quantus (Assura) Parasitic Extraction Run Form

Click on the “Setup” tab, check for “Technology → gpdk180” and select “Output →
Extracted View” as shown in Figure – 1.131. Click on “Extraction” tab and the options can
be seen as shown in Figure – 1.132.

96
 Figure – 1.132: “Extraction” Tab

Select “Extraction Type → RC” and the other options like “R only”, “C only” and others can
be checked as per the requirements. Select the “Ref Node → VSS” and click on “OK” as
shown in Figure – 1.132. The “Quantus Progress Form” can be seen as shown in Figure –
1.133.

Figure – 1.133: Quantus Progress Form

97
After Extraction, the “Quantus Run” form pops up with the “av_extracted” file’s location as
shown in Figure – 1.134.

Figure – 1.134: Quantus Run form

The details of Extracted Parasitics are available with the av_extracted view and the file can be
opened from the Library Manager as shown in Figure – 1.135.

Figure – 1.135: “av_extracted” view from Library Manager

Double Click on “av_extracted” view to see the Extracted View of the layout as shown in
Figure – 1.136.

Figure – 1.136: Extracted View

98
Use the Mouse Scroller to “Zoom In” and “Zoom out” in order to view the parasites as shown
in Figure – 1.137.

Figure – 1.137: Parasitic Resistance (presistor) after Zoom In

To check out the values of these Parasitic Resistance, click on “Shift + F”. By zooming in
further, the values can be checked out as shown in Figure – 1.138.

Figure – 1.138: Value of Parasitic Resistance

The impact of these parasitic devices can be checked out through the Backannotation (Post
Layout Simulation) process.

99
BACKANNOTATION (POST LAYOUT SIMULATION):
To run the Post Layout Simulation, the extracted Parasitics have to be imported into the Test
Schematic. So, a New Configuration has to be created.
To create a “New Configuration” select the Cell which has the Test Schematic and select its
“Schematic” view as shown in Figure – 1.139.

Figure – 1.139: Selecting the “Schematic” view

Click on “File → New → Cell View” as shown in Figure – 1.140.

100
 Figure – 1.140: File → New → Cell View

The “New File” window pops up. Select the “Type → config” from the drop down as
shown in Figure – 1.141. Soon as the “Type → config” is selected, “View → config” and
in “Application”, “Open with → Hierarchy Editor” gets updated. Click on “OK”.

Figure – 1.141: “New File” window

The “New Configuration” window pops up as shown in Figure – 1.142. Click on “Use
Template”.

101
 Figure – 1.142: “New Configuration” window

The “Use Template” window pops up as shown in Figure –

1.143.

Figure – 1.143: Use Template window

Click on the drop down and select “Name → Spectre”, the name of the Simulator and
click on“OK” as shown in Figure – 1.144.

102
 Figure – 1.144: Name → Spectre

The updated “New Configuration” window pops up as shown in Figure – 1.145.

Figure – 1.145: New Configuration window

The “Top Cell → View → Schematic” has to be selected using the drop down as shown in
Figure – 1.145. The “New Configuration” window gets updated as shown in Figure – 1.146.

103
 Figure – 1.146: Top Cell → View → Schematic

Click on “OK” and the “Virtuoso Hierarchy Editor: New Configuration” window pops up
as shown in Figure – 1.147.

Figure – 1.147: Virtuoso Hierarchy Editor: New Configuration window

104
two types of views, “Table View” and “Tree View” can be seen. Select “Tree View” as
shown in Figure – 1.147, the instance “I0” which is the Instance number of the Symbol with
which we had created the Test Schematic can be seen.
Select the Instance “I0” as shown in Figure – 1.148, make a Right Click, select “Set Instance
View → av_extracted”.

Figure – 1.148: Set Instance View → av_extracted

Click on the “ + “ sign before the instance “I0” to see the imported parasitics as shown in Figure
– 1.149.

Figure – 1.149: Imported Parasitics

105
Click on the “Save” option, click on “Open” to bring back the Test Schematic as shown in
Figure – 1.150.

Figure – 1.150: Test Schematic

To verify if the parasitics are imported, double click on the Inverter symbol, the “Descend”
window pops up as shown in Figure – 1.151. Check if “View → av_extracted” and select
“Open in → new tab” and click on “OK”

106
 Figure – 1.151: Descend window

This should open the av_extracted view as we had seen in Figure -1.139 in a new tab as shown
in Figure – 1.152.

Figure – 1.152: av_extracted view in a new tab

107
Click on “Launch → ADE L” and select “Session → Load State” to open the Saved State as
shown in Figure – 1.153.

Figure – 1.153: Saved State

Re-run the Simulation and check for the waveforms of Transient Analysis and DC Analysis as
shown in Figure – 1.154.

Figure – 1.154: Waveforms of Transient Analysis and DC Analysis

108
Using the Calculator, obtain the Switching Potential, 𝑡𝑝𝐻𝐿 , 𝑡𝑝𝐿𝐻 and 𝑡𝑃𝐷. The results are
tabulated in Table – 8. 𝟒𝟎
Table – 8: Values of 𝒕𝒑 , 𝒕𝒑 and 𝒕 for CMOS Inverter with 𝑾𝑷 =
𝑯𝑳 𝑳𝑯 𝑷𝑫 𝑾𝑵 𝟐𝟎

109
LAB – 02: 2 – INPUT CMOS NAND GATE

Objective:
(a) Capture the Schematic of a 2 – input CMOS NAND Gate having similar delay as that
of CMOS Inverter computed in Lab – 01. Verify the functionality of the NAND Gate
and also find out the delay for all the four possible combinations of input vectors.
Tabulate the results. Increase the drive strength to 2X and 4X and tabulate the results.
40
(b) Draw the layout of NAND with 𝑊𝑃 = , use optimum layout methods. Verify DRC
𝑊𝑁 20
and LVS, extract the parasitics and perform the post layout simulation, compare the
results with pre layout simulations. Record the observations.

Solution – (a):
SCHEMATIC CAPTURE:
Following the techniques demonstrated in Lab – 01, Create a New Library using the option
“File → New → Library”, create a New Cell View upon selecting the newly created library
using the option “File → New → Cell View” and instantiate the required devices using the
“Create → Instance” option.
The device parameters are listed in Table – 9.
Table – 9: Width and Length of NMOS and PMOS Transistors for CMOS NAND Gate
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 1.7 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 1.275 u
Length, L = 180 n

Similarly, the device parameters for the 2 – input CMOS NAND Gate with drive strength 2
and drive strength 4 are listed in Table – 10 and Table – 11.
Table – 10: Width and Length of NMOS and PMOS Transistors for CMOS NAND Gate
with Drive Strength “2”
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 3.4 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 2.55 u
Length, L = 180 n

Table – 11: Width and Length of NMOS and PMOS Transistors for CMOS NAND Gate
with Drive Strength “4”
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 6.8 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 5.1 u
Length, L = 180 n

The completed Schematic for all the three dimensions are shown in Figure – 2.1, Figure – 2.2
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and Figure – 2.3.

Figure – 2.1: Schematic Capture of 2 – input CMOS NAND Gate (NAND2X1)

Figure – 2.2: Schematic Capture of 2 – input CMOS NAND Gate with drive strength 2
(NAND2X2)

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 Figure – 2.3: Schematic Capture of 2 – input CMOS NAND Gate with drive strength 2
(NAND2X4)

The symbol for the CMOS NAND Gate is shown in Figure – 2.4.

Figure – 2.4: Symbol of 2 – input NAND Gate

FUNCTIONAL SIMULATION:
Using the symbol created, build the Test Schematic. Create a New Cell View, instantiate the
symbol of 2 – input NAND Gate, DC Voltage Source, Capacitance and Ground, connect the
using wires. Create two input pins for the circuit A and B and connect them to the input of the

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NAND gate as shown in Figure – 2.5. Repeat the same procedure for creating the Test
Schematic for the 2 – input CMOS NAND Gate with drive strength 2 and drive strength 4.

Figure – 2.5: Test Schematic for 2 – input CMOS NAND Gate

Launch ADE L, select “Setup → Stimuli” as shown in Figure – 2.6 to give the required
sequence of inputs to pins A an

Figure – 2.6: Setup → Stimuli

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The “Setup Analog Stimuli” window pops up as shown in Figure – 2.7.

Figure – 2.7: Setup Analog Stimuli window

Select “Stimulus Type → Inputs” and the input pins A and B get listed out as shown in Figure
– 2.7. Select any one of the Inputs, click on “Enabled” and select “Function → bit”.
Mention the value of voltages for “Logic 0” and “Logic 1” in “One value → 1.8” and “Zero
value → 0”.
Consider the values of Rise time, Fall time and Period similar to that considered in Lab – 01.
Select “Source type → bit”, “Pattern Parameter data → 11001001”, “Pattern Parameter
rptstart → 1”, “Pattern Parameter rpttimes → 0” and “Trigger → Internal”, click on
“Apply” to “Turn ON” the input and click on “OK”.
Select the type of Analysis to be performed on the 2 – input CMOS NAND Gate.
Select the Input and Output Signals to be plotted.
The ADE L window gets updated as shown in Figure – 2.8.
Run the Simulation to check for the functionality of the NAND Gate.

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 Figure – 2.8: Updated ADE L window

The Simulated waveforms can be seen as shown in Figure – 2.9.

Figure – 2.9: Transient Analysis of 2 – input CMOS NAND Gate

The delay values are obtained using the “Calculator” option as demonstrated in Lab – 01. The
results are tabulated as shown in Table – 12.
Table – 12: Values of Delay for 2 – input CMOS NAND2X1, NAND2X2 and NAND 2X4

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Solution – (b):
SCHEMATIC CAPTURE:
Following the techniques demonstrated in Lab – 01, Create a New Library, a New Cell View
and instantiate the devices as per the Schematic of 2 – input CMOS NAND Gate.
The device parameters for the NMOS and PMOS Transistors are listed in Table – 13.
𝟒𝟎
Table – 13: Device parameters for 2 – input CMOS NAND Gate with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 20 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 40 u
Length, L = 180 n

The Schematic as per the dimensions of NMOS and PMOS transistors listed above is shown in
Figure – 2.10.

𝟒𝟎
Figure – 2.10: Schematic for 2 – input CMOS NAND with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

Symbol for the Schematic in Figure – 2.10 is shown in Figure – 2.11.

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 𝟒𝟎
Figure – 2.11: Symbol for 2 – input CMOS NAND with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

FUNCTIONAL SIMULATION:
The Test Schematic for the functionality check of the 2 – input CMOS NAND Gate is shown
in Figure – 2.12.

𝟒𝟎
Figure – 2.12: Test Schematic for 2 – input CMOS NAND with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

The ADE L window after choosing the Analysis and the Signals to be plotted is shown in
Figure – 2.13.

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 Figure – 2.13: Updated ADE L window

The waveforms after simulation is shown in Figure – 2.14.

𝟒𝟎
Figure – 2.14: Simulated Waveforms for 2 – input CMOS NAND with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

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The values of delay elements are tabulated in Table – 14.
𝟒𝟎
Table – 14: Delay Elements for 2 – input CMOS NAND Gate with 𝑾𝑷 = (Pre Layout
𝑾𝑵 𝟐𝟎
Simulation)

LAYOUT:
Follow the techniques demonstrated in Lab – 01 to open the Layout Editor, import the devices
from the Schematic, place the devices as per the requirement and complete the routing. The
completed layout can be seen as shown in Figure – 2.15.

𝟒𝟎
Figure – 2.15: Layout for 2 – input CMOS NAND Gate with 𝑾𝑷 =
𝑾𝑵 𝟐𝟎

DRC:
To check for the DRC violations, browse the “assura_tech.lib” file, select “Assura → Run
DRC”, verify the Layout Design Source, mention a “Run Name”, select “Technology →
gpdk180” and click on “OK” as demonstrated in Lab – 01.

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LVS:
To check for the LVS violations, select “Assura → Run LVS”, verify the Schematic Design
Source and the Layout Design Source, mention a “Run Name”, select “Technology →
gpdk180” and click on “OK” as demonstrated in Lab – 01.
QRC:
To extract the Parasitics, select “Assura → Quantus”, select “Technology → gpdk180”,
“Output → Extracted View” from the “Setup” option, select “Extraction Type → RC” and
“Ref Node → VSS” from the “Extraction” and click on “OK” as demonstrated in Lab – 01.
The result can be checked from the Library Manager.
BACKANNOTATION:
Import the parasitics into the Test Schematic and re-run the simulation to check their impact
by calculating the delay elements as demonstrated in Lab – 01.
The values of delay are shown in Table – 15.
𝟒𝟎
Table – 15: Delay Elements for 2 – input CMOS NAND Gate with 𝑾𝑷 = (Post Layout
𝑾𝑵 𝟐𝟎
Simulation)

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LAB – 03: COMMON SOURCE AMPLIFIER WITH PMOS CURRENT MIRROR
LOAD

Objective:
(a) Capture the Schematic of a Common Source Amplifier with PMOS Current Mirror
Load and find its Transient Response and AC Response. Measure the UGB and
Amplification Factor by varying transistor geometries, study the impact of variation in
width to UGB.
(b) Draw the layout of Common Source Amplifier, use optimum layout methods. Verify
DRC and LVS, extract the parasitics and perform the post layout simulation, compare
the results with pre layout simulations. Record the observations.

Solution – (a):
SCHEMATIC CAPTURE:
Following the techniques demonstrated in Lab – 01, Create a New Library using the option
“File → New → Library”, create a New Cell View upon selecting the newly created library
using the option “File → New → Cell View” and instantiate the required devices using the
“Create → Instance” option.
The device parameters are listed in Table – 16.
Table – 16: Width and Length of NMOS and PMOS Transistors
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 6 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 8.85 u
Length, L = 180 n

The completed Schematic is shown in Figure – 3.1.

Figure – 3.1: Schematic of Common Source Amplifier with PMOS Current Mirror Load

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The symbol for the Common Source Amplifier with PMOS Current Mirror Load is shown in
Figure – 3.2.

Figure – 3.2: Symbol of Common Source Amplifier with PMOS Current Mirror Load

FUNCTIONAL SIMULATION:
Using the symbol created, build the Test Schematic. Create a New Cell View, instantiate the
symbol of Common Source Amplifier with PMOS Current Mirror Load, DC Voltage Source,
Current Source, AC Voltage Source, Capacitance, Resistance and Ground, connect the using
wires.

Figure – 3.3: Test Schematic for 2 – input CMOS NAND Gate

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The parameters for remaining devices are shown in Table – 17.

Library Name Cell Name Comments / Properties

analogLib vdc DC voltage = 3.3 V (VDD)
analogLib vdc DC voltage = VBIAS_N V (Vin)
analogLib isin DC current = 100u A (Vbias_P)
analogLib vsin AC Magnitude = 1 V, Amplitude = 10u V,
Frequency = 10K Hz (Vin)
analogLib cap Capacitance = 500f F
analogLib res Resistance = 10u Ohms
analogLib gnd
Table – 17: Parameters for the devices used in Test Schematic

Launch ADE L, import the design variables, mention the values and select the Transient
Analysis, DC Analysis and AC Analysis, mention the parameters and choose the signals to be
plotted as shown in Figure – 3.4.

Figure – 3.4: Updated ADE L window

The Simulated waveforms can be seen as shown in Figure – 3.5 and Figure – 3.6.

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 Figure – 3.5: Transient Analysis

Figure – 3.6: AC Analysis

To measure the Gain and Unity Gain Bandwidth, go back to the ADE L window, select
“Results → Direct Plot → AC Magnitude & Phase” as shown in Figure – 3.7.

The Test Schematic window pops up, select the output net as shown in Figure – 3.8 and click
on “Esc” key on the keyboard.
The waveform can be seen as shown in Figure – 3.9. The marker placed on the low frequency
part of the response gives the DC Gain, use the bind key “M” to place the marker.
Place a horizontal cursor at “0 dB” and the crossing frequency gives the Unity Gain Bandwidth
(UGB) as shown in Figure 3.9.

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Figure – 3.7: Results → Direct Plot → AC Magnitude & Phase

Figure – 3.8: Selecting Output Net from the Test Schemati

Figure – 3.9: Gain and Phase plot

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Solution – (b):
LAYOUT:
Follow the techniques demonstrated in Lab – 01 to open the Layout Editor, import the devices
from the Schematic, place the devices as per the requirement and complete the routing. The
completed layout can be seen as shown in Figure – 3.10.

Figure – 3.10: Layout for Common Source Amplifier with PMOS Current Mirror Load

DRC:
To check for the DRC violations, browse the “assura_tech.lib” file, select “Assura → Run
DRC”, verify the Layout Design Source, mention a “Run Name”, select “Technology →
gpdk180” and click on “OK” as demonstrated in Lab – 01.
LVS:
To check for the LVS violations, select “Assura → Run LVS”, verify the Schematic Design
Source and the Layout Design Source, mention a “Run Name”, select “Technology →
gpdk180” and click on “OK” as demonstrated in Lab – 01.
QRC:
To extract the Parasitics, select “Assura → Quantus”, select “Technology → gpdk180”,
“Output → Extracted View” from the “Setup” option, select “Extraction Type → RC” and
“Ref Node → VSS” from the “Extraction” and click on “OK” as demonstrated in Lab – 01.
The result can be checked from the Library Manager.
BACKANNOTATION:
Import the parasitics into the Test Schematic and re-run the simulation to check their impact
by calculating the delay elements as demonstrated in Lab – 01.

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LAB – 04: 2 – STAGE OPERATIONAL AMPLIFIER

Objective:
(a) Capture the Schematic of a 2 – Stage Operational Amplifier and measure the following:
1. UGB
2. dB Bandwidth
3. Gain Margin and Phase Margin with and without coupling capacitance
4. Use the Op-Amp in the Inverting and Non-Inverting configuration and verify its
functionality
5. Study the UGB, 3 dB Bandwidth, Gain and Power Requirement in Op-Amp by
varying the stage wise transistor geometries and record the observations
(b) Draw the layout of 2 – stage Operational Amplifier with the maximum transistor width
set to 300 (in 180 / 90/ 45n m Technology), choose appropriate transistor geometries as
per the results obtained in 4(a). Use optimum layout methods. Verify DRC and LVS,
extract the parasitics and perform the post layout simulation, compare the results with
pre layout simulations. Record the observations.

Solution – (a):
SCHEMATIC CAPTURE:
Create a New Library, select the Technology Node as “gpdk045” (Technology Node used for
this demonstration is 45 nm), Create a New Cell View, instantiate the devices as demonstrated
in Lab – 01. Use the “Sideways” option as shown in Figure – 4.1 to flip the Transistor.

Figure – 4.1: “Sideways” option to flip the Figure – 4.1(a): Figure – 4.1(b):
Transistors Before and After selecting “Sideways”

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The Transistors before and after flipping are shown in Figure – 4.1(a) and Figure – 4.1(b). The
dimensions of all the devices are given in Table – 18 as shown below.
Table – 18: Device Parameters for 2 – Stage Operational Amplifier
Library Name Transistor Cell Name Comments /
Properties
gpdk045 M0, M1 pmos2v Width, W = 465 n
Length, L = 150 n
gpdk045 M3, M4 nmos2v Width, W = 490 n
Length, L = 150 n
gpdk045 M5, M7 nmos2v Width, W = 1.09 u
Length, L = 150 n
gpdk045 M2 pmos2v Width, W = 10 u
Length, L = 150 n
gpdk045 M6 nmos2v Width, W = 6.88 u
Length, L = 150 n
gpdk045 M8 pmoscap2v Calculated
Parameter =
Capacitance
Capacitance =
250.043 f

The completed Schematic as per the dimensions mentioned in Table – 18 is shown in Figure –
4.2.

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 Figure – 4.2: Schematic of 2 – Stage Operational Amplifier

The Symbol created according to the Techniques demonstrated in Lab – 01 is shown in Figure
– 4.3.

Figure – 4.3: Symbol for 2 – Stage Operational Amplifier

FUNCTIONAL SIMULATION USING ADE EXPLORER AND ASSEMBLER:

To test the functionality of Operational Amplifier, build a Test Schematic using the Symbol
that was created as shown in Figure – 4.3. Create a New Cell View, instantiate the symbol.
Instantiate the other devices required for testing the circuit, mention the device parameters as
shown in Table – 19.
Table – 19: Device Parameters for 2 – Stage Operational Amplifier Test Schematic
Library Name Cell Name Comments / Properties
analogLib vdc DC voltage = vdd V
analogLib vdc DC voltage = vss V

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analogLib vpulse Voltage 1 = vdc + 0.3 V, Voltage 2 = vdc -
0.3 V, Period = 10u s, Rise time = 10p s,
Fall time = 10p s
analogLib idc DC current = ibias A
analogLib cap Capacitance = CL F
analogLib gnd

The Test Schematic after completion of all the interconnections can be seen as shown in Figure
– 4.4.

Figure – 4.4: Test Schematic for 2 – Stage Operational Amplifier

The specification that has to be achieved on simulating the design are as follows:
• Slew Rate >= 50 MV/s
• DC Open Loop Gain >= 60 dB (1000 V/V)
• Unity Gain Bandwidth >= 50 MHz
• Output Offset <= ± 10 mV
• Settling Time <= 50 ns
The steps to be carried out are listed below:
Step – 1:
Select “Launch → ADE Explorer” as shown in Figure – 4.5.

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 Figure – 4.5: Launch → ADE Explorer

The “Launch ADE Explorer” window pops up, select “Create New View” and click on “OK”
as shown in Figure – 4.6.

Figure – 4.6: “Launch ADE Explorer” window

The “Create new ADE Explorer view” window pops up as shown in Figure – 4.7. Select the
Cell View Name, “Open in → new tab” and click on “OK”.

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 Figure – 4.7: “Create new ADE Explorer view” window

The “Virtuoso ADE Explorer Editing” window pops up as shown in Figure – 4.8.

Figure – 4.8: “Virtuoso ADE Explorer Editing” window

Select “Setup → Model Libraries” as shown in Figure – 4.9.

Figure – 4.9: Setup → Model Libraries

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The “spectre1: Model Library Setup” window pops up as shown in Figure – 4.10. Select the
respective “.scs” file and the process corner as “tt”. Click on “OK”

Figure – 4.10: “spectre1: Model Library Setup” window

To analyze the circuit through Transient Analysis and AC Analysis, select “Click to add
analysis” just below the “Analyses” option in the “Setup” window as shown in Figure – 4.11.

Figure – 4.11: Analyses → Click to add analysis

The “Choosing Analyses – ADE Explorer” window pops up as shown in Figure – 4.12. Select
the “tran” for the “Transient Analysis” and “dc” for the “DC Analysis”.
The ADE Explorer window gets updated as shown in Figure – 4.13.
Mention the values for the Design Variables defined in the Schematic of the 2 – Stage
Operational Amplifier.

133
The defined values for the respective Design Variables are given in Table – 20. The Design
Variables along with the values in ADE Explorer window is shown in Figure – 4.13.

Figure – 4.12: “Choosing Analyses – ADE Explorer” window

Analyses

Design Variables

Figure – 4.13: Updated ADE Explorer

Name of the Variable Value
CL 1p

134
 ibias 10u
vdc 1
vdd 2
vss 0
Table – 20: Design Variables and its Values

To specify the outputs for the simulation, select “Tools → Calculator” as shown in Figure –
4.14.

Figure – 4.14: Tools → Calculator

The “Virtuoso Visualization & Analysis XL calculator” window pops up as shown in Figure
– 4.15.

135
 Figure – 4.15: “Virtuoso Visualization & Analysis XL calculator” window

Select “vt” as shown in Figure – 4.15. The Test Schematic pops up as shown in Figure – 4.16.
Select the output net “OUT” from the Schematic and the Buffer window in the Calculator gets
updated as shown in Figure – 4.17.

Select the Output Net

Figure – 4.16: Test Schematic

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 Buffer window Send buffer expression to ADE Outputs

Figure – 4.17: Updated Buffer window

Click on “Send buffer expression to ADE Outputs” option to get the expression from the
Buffer window into ADE Explorer as shown in Figure – 4.18.

Figure – 4.18: Updated ADE Explorer

Initially, the “Name” column would be blank, use the left mouse click to rename (for eg:
vout_tran). Similarly, select “vt” again, to select the input net “IN” and then select “vdc” from
the calculator, select the input net and the output net from the Test Schematic, rename it for
easier identification. The updated ADE Explorer can be seen as shown in Figure – 4.19.

Figure – 4.19: Updated ADE Explorer

Click on the “Upward Arrow” just before the Test Circuit name in the Setup tab to invoke the
ADE Assembler as shown in Figure – 4.20. The ADE Assembler allows multiple tests to be
simulated on the same environment.

137
 Figure – 4.20: ADE Assembler invoked

Figure – 4.21: Create Test Copy

Expand “Tests” and use the left mouse click to select the Test Circuit and use the right mouse
click to select “Create Test Copy” as shown in Figure – 4.21.
Use a left mouse click to select the “Copied Test” (for eg: FDP_45_opamp_org:Op_amp_
tran_test:1:1) as shown in Figure – 4.22. Left mouse click again to rename it to
FDP_45_opamp_org:Op_amp_ ac_test:1 as shown in Figure – 4.22.

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 Figure – 4.22: Copied Test

Left mouse click again to rename it to FDP_45_opamp_org:Op_amp_ ac_test:1 as shown in

Figure – 4.23.

Figure – 4.23: Renamed Test

To verify the selected design for “ac” test, right mouse click on the test and select “Design” as
shown in Figure – 4.24.
The “Choose Design – ADE Assembler” window pops up as shown in Figure – 4.25.
Select the Library, Cell Name, “View Name → Schematic” and click on “OK”.
Select all the tests related to “ac” from the “Outputs Setup” and delete them.
Select the “ac” test from the “Data View” window, expand, select “Analyses” and remove the
“tran” and “dc” analysis that were copied.
The updated ADE Assembler window is shown in Figure – 4.26.

139
 Figure – 4.24: Select “Design” option

Figure – 4.25: Select the “Op_amp_ac” Cell Name

Figure – 4.26: Updated ADE Assembler

140
Select “Click to add analysis” option from the Analyses option to select the “ac” analysis for
the Test Schematic. The parameters are shown in Figure – 4.27.

Figure – 4.27: “ac” analysis

Click on “Apply”, click on “OK” to see the ADE Assembler updated as shown in Figure –
4.28.

141
 Figure – 4.28: Updated ADE Assembler with “ac” analysis

Expand the “Design Variables”, add “vac” as the variable and “100m” as its value by selecting
the “Click to add variable” option. The updated Design Variables are shown in Figure – 4.29.

Figure – 4.29: Updated Design Variables

Select “Tools → Calculator” and select the “ac” analysis test circuit as shown in Figure –
4.30.

Figure – 4.30: Selecting “ac” test from calculator

Select “vf” which accesses voltage over frequency and select the output net from the Test
Schematic. The updated Buffer can be seen in Figure – 4.31.

142
 Figure – 4.31: Updated Buffer after “vf” and output net selection

Similarly, select the input net from the Test Schematic. The buffer and stack gets updated as
shown in Figure – 4.32.

Figure – 4.32: Updated Buffer and Stack

Click on “ / “ from the keypad as shown in Figure – 4.32. The expression in the Buffer gets
updated as shown in Figure – 4.33.

143
 Figure – 4.33: Updated Buffer and Stack
Select “dB20” from the Function Panel, the expression in buffer gets updated as shown in
Figure – 4.34.

Figure – 4.34: Updated Buffer after selecting “dB20”

This expression calculates the Gain in dB for the Amplifier. Click on “Send buffer expression
to ADE Outputs”. Rename the expression and the updated ADE Assembler can be seen as
shown in Figure – 4.35.

Run Simulation

Figure – 4.35: Expression from the Calculator

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Click on “Run Simulation” option as shown in Figure – 4.35 to simulate the design. The ADE
Assembler after simulation is shown in Figure – 4.36.

Figure – 4.36: ADE Assembler after simulation

Select “Options → Plotting/Printing” as shown in Figure – 4.37.

Figure – 4.37: Options → Plotting/Printing

The “ADE Assembler Plotting/Printing Options” window pops up as shown in Figure – 4.38.
Select “Plotting Option → Auto” and uncheck “Plot Scalar Expressions”, click on “OK” as
shown in Figure – 4.38.

145
 Figure – 4.38: ADE Assembler Plotting/Printing Options” window

Click on “Plot All” to see the waveforms as shown in Figure – 4.39.

Plot All

Figure – 4.39: “Plot All” option

146
The plotted waveforms can be visualized in the “Virtuoso Visualization & Analysis XL”
window as shown in Figure – 4.40.

Figure – 4.40: Plotted Waveforms

Select “Measurements → Transient Measurement” as shown in Figure – 4.41.

Figure – 4.41: Measurements → Transient Measurement

The Slew Rate can be checked out as shown in Figure – 4.42.

To calculate the Settling Time, consider the time the wave takes to reach and stay between (+/-
1%) of its final value in comparison with the initial value. This is calculated as follows:
Lower Bound = 99 % * (1.3 V – 0.7 V) + 0.7 V = 1.294 V
Upper Bound = 101 % * (1.3 V – 0.7 V) + 0.7 V = 1.306 V
Right Mouse click on X-axis properties, “Independent Axis Properties for time” window
pops up as shown in Figure – 4.43.

147
Figure – 4.42: Transient Measurement tab

148
 Figure – 4.43: “Independent Axis Properties for time” window

Select the “Scale” tab, select “Mode → Manual”, mention Axis Limits “Minimum → 4.98u
s”, “Maximum → 5.04u s” and Divisions “Minor → 10”, “Major → 30”, click on “OK” as
shown in Figure – 4.43. This will isolate the edges that are to be analyzed as shown in Figure
– 4.44.

Figure – 4.44: Isolated Waveforms

149
Use left mouse click and drag and drop to combine the waveforms as shown in Figure – 4.45.

To Enable / Disable Visibility

Figure – 4.45: Combined Waveforms

Use the bind key “M” to setup a Marker at the required time instance as shown in Figure –
4.46.

Figure – 4.46: Waveform with Marker

Use the bind key “H” to setup horizontal cursors at 1.294 V and 1.306 V as shown in Figure –
4.47.

150
 Figure – 4.47: Horizontal cursors at 1.294 V and 1.306 V

Use the zooming options to zoom-in and zoom-out as and when required. Setup a marker on
the lower horizontal cursor as shown in Figure – 4.48.

Figure – 4.48: Marker on the 2nd horizontal cursor

The difference between the timing instances gives the Settling Time as 12.5n s.
Without closing the waveform window, open the “maestro” in the ADE Assembler.
For this simulation, the output dc value is 1.298 V and the input dc value is 1.3 V.
The difference gives the DC Offset (1.298 V – 1.3 V = 2m V).
From the AC Analysis curve, set the marker on the low frequency portion of the signal as
shown in Figure – 4.49.
The marker reading gives the DC Open Loop Gain which is 50.98 dB.
Setup a horizontal cursor at 0 dB as shown in Figure – 4.50. The point of intersection of the
cursor with the AC Analysis curve gives the Unity Gain Bandwidth.
The Unity Gain Bandwidth is measured as 84.51M Hz.

151
 Figure – 4.49: DC Open Loop Gain – 50.98 dB

Figure – 4.50: Unity Gain Bandwidth – 84.51M Hz

152
GENERATING THE EXPRESSIONS:
To improve productivity, create reusable expressions rather than using the measurements from
waveforms.
To generate the expressions, open the “Outputs Setup” tab from ADE Assembler, click on
“Add new output” as shown in Figure – 4.51.

Add new output

Figure – 4.51: “Add new output” option

Select “FDP_45_opamp_org:Op_amp_tran_test → Expression” as shown in Figure – 4.52.

Figure – 4.52: FDP_45_opamp_org:Op_amp_tran_test → Expression

153
 Open expression builder

Figure – 4.53: Open expression builder

For the new expression, click on the “Details” column and click on “Open expression
builder” as shown in Figure – 4.53.
Type “Slew” and the auto-completion can be seen. Select “slewRate” as shown in Figure –
4.54.

Figure – 4.54: “slewRate” auto-completion

Scroll down and select “vout_tran”, it points to the next parameter. Mention the values and
the completed expression can be seen as shown in Figure – 4.55.

154
 Slew Rate Expression

Figure – 4.55: Completed expression

The values for the remaining parameters are given below:

initialValue - 1.3
initalValueType - nil
finalValue - 0.7
finalValueType - nil

percentLow - 20
percentHigh - 80
numberOfOccurences - nil
sweepName - time
Click on the “closing parenthesis” to complete the expression. Click on the “Green” colored
tick mark to update the expression in the “Details” tab as shown in Figure – 4.56.

Figure – 4.56: Expression updated in ADE Assembler

Mention a “Name” for the created expression as shown in Figure – 4.57.

155
 Figure – 4.57: Naming the expression

Similarly, include the expression for Settling Time. After completion, ADE Assembler is
updated as shown in Figure – 4.58.

Figure – 4.58: ADE Assembler updated with Settling Time

The expression for DC Offset is shown in Figure – 4.59.

Figure – 4.59: DC Offset

The expression for dissipated power is shown in Figure – 4.60. After typing “ 2 * ”, select
“IDC” from the list (“2” → Total Supply voltage range applied on the op-amp). Click on
“Select from design” and select the top pin of the “DC Voltage Source” instantiated for
“VDD”.

156
 Figure – 4.60: Dissipated Power

To include the expression for DC Gain and Bandwidth, select the AC Analysis and mention
the expressions. The expression for Bandwidth is shown in Figure – 4.61.

Figure – 4.61: Bandwidth

The expression for DC Gain is shown in Figure – 4.62.

Figure – 4.62: DC Gain

After defining all the expressions, the ADE Assembler gets updated as shown in Figure – 4.63

Figure – 4.63: Updated ADE Assembler with expressions

157
Go back to the “Results” tab in the “maestro” and click on “Re-evaluates results using
current settings from the outputs setup table or with partial simulation data” option as
shown in Figure – 4.64 to re-simulate the expressions and evaluate the data.

Figure – 4.64: Evaluated Results after re-simulation

Slew Rate and Power Dissipation are seen as negative values after re-simulation. To get the
positive values, change the expression on the Outputs Setup as shown in Figure – 4.65.

Figure – 4.65: Modified expressions to get positive values

Specifications can be mentioned as shown in Figure – 4.66

Figure – 4.66: Specifications

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After re-evaluation, the results can be seen as shown in Figure – 4.67.

Figure – 4.67: Results after re-evaluation

GAIN MARGIN AND PHASE MARGIN:

The Schematic for measuring the Gain Margin and Phase Margin is shown in Figure – 4.68.

Figure – 4.68: Schematic for Gain Margin and Phase Margin measurement

The “iprobe” (available in “analogLib”) acts as a signal source for the stability analysis.
Create a Test Copy for the Stability Analysis as shown in Figure – 4.69.

Figure – 4.69: Test Creation for Stability Analysis

159
 Browse “Design → Op_amp_tran_test_gm_pm” as shown in Figure – 4.70.

Figure – 4.70: Design Selection

se “stb” through “Analyses → Click to add analysis → Choosing Analyses – ADEAssembler”. The
parameters are shown in Figure – 4.71.

160
Figure – 4.71: “stb” selection and its parameters

161
Click on the “downward arrow” just before the test name as shown in Figure – 4.72 to go
back to the ADE Explorer.

Go back to ADE Explorer

Figure – 4.72: Click on downward arrow

The ADE Explorer window pops up as shown in Figure – 4.7

Figure – 4.73: ADE Explorer

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 Click on “Simulation → Netlist and Run” similar to the selection in ADE L window. After
the simulation, select “Results → Direct Plot → Main Form” as shown in Figure – 4.74. The
“Direct Plot Form” pops up as shown in Figure – 4.75. Click on “Stability Summary” to
print the values of Gain Margin and Phase Margin. Click on “Plot” to plot the graph.

Figure – 4.74: Results → Direct Plot → Main Form

Figure – 4.75: Direct Plot Form and Stability Summary with Gain Margin and PhaseMargin

163
LAYOUT:
Follow the techniques demonstrated in Lab – 01 to open the Layout Editor, import the devices
from the Schematic, place the devices as per the requirement and complete the routing. The
completed layout can be seen as shown in Figure – 4.76.

Figure – 4.76: Layout for 2 – Stage Operational Amplifier

DRC:
To check for the DRC violations, browse the “assura_tech.lib” file, select “Assura → Run
DRC”, verify the Layout Design Source, mention a “Run Name”, select “Technology →
gpdk045” and click on “OK” as demonstrated in Lab – 01.
LVS:
To check for the LVS violations, select “Assura → Run LVS”, verify the Schematic Design
Source and the Layout Design Source, mention a “Run Name”, select “Technology →
gpdk045” and click on “OK” as demonstrated in Lab – 01.
QRC:
To extract the Parasitics, select “Assura → Quantus”, select “Technology → gpdk180”,
“Output → Extracted View” from the “Setup” option, select “Extraction Type → RC” and
“Ref Node → VSS” from the “Extraction” and click on “OK” as demonstrated in Lab – 01.
The result can be checked from the Library Manager.
BACKANNOTATION:
Import the parasitics into the Test Schematic and re-run the simulation to check their impact
by calculating the delay elements as demonstrated in Lab – 01.

164
APPENDIX – 1: CHANGING BACKGROUND COLOR IN VIRTUOSO SCHEMATIC
EDITOR
To change the background color for the Virtuoso Schematic Editor, select “Options → User
Preferences” from the Command Interpreter Window as shown in Figure – a.

Figure – a: Options → User Preferences

The “User Preferences” window pops up as shown in Figure – b.

Figure – b: User Preferences window

165
Click on “Default Editor Background Color” as shown in Figure – b. The “Select Color”
window pops up as shown in Figure – c.

Figure – c: Select Color window

Select the Screen Color of interest and click on “OK” as shown in Figure – c.

Figure – d: Updated User Preferences window

The updated “User Preferences” window can be seen as shown in Figure – d. Click on
“Apply” and click on “OK”.
The updated “Virtuoso Schematic Editor L Editing” window can be seen as shown in Figure
166
Figure – e: Updated Virtuoso Schematic Editor L Editing window

167
LIST OF LAB EXPERIMENTS

Exp. Name of the Experiment Page

No. No.
1 4Bit UP/DOWN Counter Asynchronous Reset Counter 3
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the Gate Level Netlist by setting Area and Timing Constraints and
also find the Critical Path and Maximum Frequency of Operation
• Perform the above for 32Bit UP/DOWN Counter
2 4Bit Adder 20
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the netlist.
• From the report generated identify Critical path, Maximum delay, Total
number of cells, Power requirement and Total area required
3 UART 25
• Write Verilog Code
• Verify the Functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing
constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
4 32Bit ALU Supporting 4-Logical and 4-Arithmetic operations, using case and if 34
statement for ALU Behavioral Modeling
• Write Verilog Code
• Verify functionality using Test-bench
• Synthesize the design targeting suitable library and by setting area and timing
constraints
• Tabulate the Area, Power and Delay for the Synthesized netlist
• Identify Critical path
5 Latch and Flip-Flop 40
• Synthesize the design and compare the synthesis report (D, SR. JK)
6 For synthesized netlist carry out the following: 45
• Floor planning
• Placement and Routing
• Record the parameters such as no. of metal layers used for routing, flip
method for placement of standard cells
• Physical Verification and record the DRC and LVS reports
• Generate GDSII and record the no. of mask and its colour compositon

168
 Lab 1 : 4-bit Up/Down Counter
Aim: To write a verilog code for 4bit up/down asynchronous rest counter and its test-bench for
verification.
• Synthesizing the design by setting area and timing constraint and analyse reports.
• Finding the critical path and maximum frequency of operations
• Recording the power, area requirement and properties of each cell in terms of driving
strength.

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

• An up/down counter is a digital counter which can be set to count either from 0 to
MAX_VALUE or MAX_VALUE to 0.
• The direction of the count(mode) is selected using a single bit input. The module has 3
inputs - clk, reset which is active high and a UpOrDown mode input. The output is Counter
which is 4 bit in size.
• When Up mode is selected, counter counts from 0 to 15 and then again from 0 to 15.
• When Down mode is selected, counter counts from 15 to 0 and then again from 15 to 0.
• Changing mode doesn't reset the Count value to zero.
• You have to apply high value to reset, to reset the Counter output.

M1. Creating a Work space :

• In Desktop Create a folder to do the digital design flow. Right click in the Desktop and
select New Folder as shown in Figure1.2
• It will create a folder like below and name it as Cadence_Digital_Labs

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 Figure no. 1.2: New Folder Creation

Figure no. 1.3: Naming the Folder

Note: Give folder name without any space

• Create a new sub-Directory for the Design and open a terminal from
the Sub-Directory.

Figure no. 1.4: Creating and Naming the Sub-Directory

170
M2. Creating Source Codes

• In the Terminal, type gedit <filename>.v or <filename>.vhdl depending on the HDL

Language you are to use (ex: 4b_up_downCount.v).
• A Blank Document opens up into which the following source code can be typed down.

Note : File name should be with HDL Extension

Verilog code for 4-Bit Up-Down Counter:

//Defining a Timescale for Precision
`timescale 1ns/1ps
//Defining Module
module counter(clk,rst,m,count);
//Defining Inputs and Outputs (4bit)
input clk,rst,m;
output reg [3:0]count;
//The Block is executed when EITHER of positive edge of clock
//Both are independent events or Neg Edge of Rst arrives
always@(posedge clk or negedge rst)
begin
if(!rst)
count=0;
if(m)
count=count+1;
else
count=count-1;
end
endmodule

• Use Save option or Ctrl+S to save the code or click on the save option from the top most
right corner and close the text file.

Creating Test bench:

• Similarly, create your test bench using gedit <filename_tb>.v or <filename_tb>.vhdl to open
a new blank document (4bup_down_count_tb.v).

Test-bench code for 4-Bit Up-Down Counter:

`timescale 1ns/1ps // Creating Time Scale as in Source Code
module counter_test; // Defining Module Name without Port List
reg clk, rst,m; // Defining I/P as Registers [to Hold Values]
wire [3:0] count; // Defining O/P as Wires [To Probe Waveforms]

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Initial
begin
clk=0; // Initializing Clock and Reset
rst=0;#25; // All O/P is 4’b0000 from t=0 to t=25ns.
Rst=1; // Up-Down counting is allowed at posedge clk
end
initial
begin
m=1; // Condition for Up-Count
#600 m=0; // Condition for Down-Count
rst=0;#25;
rst=1;
#500 m=0;
end
counter counter1(clk,m,rst, count); // Instantiation of Source Code
always #5 clk=~clk; // Inverting Clk every 5ns
initial
#1400 $finish; // Finishing Simulation at t=1400ns
endmodule

• Click on the Save option and it will look like the below window and then close the file

Figure No.1.5: Verilog and Tesbench file for 4bit updown counter

172
M3. Functional Simulation:

• Invoke the cadence environment by type the below commands

◦ csh (Invokes C-Shell)
◦ source /home/install/cshrc (mention the path of the tools)
◦ (The path of cshrc could vary depending on the installation destination as /home/install/
or /home etc.)
• After this you can see the window like below

Figure No.1.6: Invoke the Cadence Environment

• To Launch Simulation tool

◦ linux:/> nclaunch -new& // “-new” option is used for invoking NCVERILOG for
the first time for any design
◦ linux:/> nclaunch& // On subsequent calls to NCVERILOG

• It will invoke the nclaunch window for functional simulation we can compile,elaborate and
simulate it using Multistep

173
 Figure No.1.7: Setting Multi-step simulation

• Select Multiple Step and then select “Create cds.lib File” as shown in below figure
• Click the cds.lib file and save the file by clicking on Save option

174
 Figure No.1.8: cds.lib file Creation

• Save cds.lib file and select the correct option for cds.lib file format based on the HDL
Language and Libraries used.
• Select “Don’t include any libraries (verilog design)” from “New cds.lib file” and click on
“OK” as in below figure
◦ We are simulating verilog design without using any libraries

• A Click “OK” in the “nclaunch: Open Design Directory” window as shown in below figure

175
• A ‘NCLaunch window’ appears as in Figure
• Left side you can see the HDL files. Right side of the window has worklib and snapshots
directories listed.
• Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

Figure
no1.10.:

Nclaunch Window

176
To perform the function simulation, the following three steps are involved Compilation, Elaboration
and Simulation.

Step 1: Compilation:– Process to check the correct Verilog language syntax and usage

Inputs: Supplied are Verilog design and test bench codes

Outputs: Compiled database created in mapped library if successful, generates report else error
reported in log file

Steps for compilation:

1. Create work/library directory (most of the latest simulation tools creates automatically)

2. Map the work to library created (most of the latest simulation tools creates automatically)

3. Run the compile command with compile options

i.e Cadence IES command for compile: ncverilog +access+rwc -compile design.v

• Left side select the file and in Tools : launch verilog compiler with current selection will get
enable. Click it to compile the code
• Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation

Figure no1.11: Compilation launch option

• After compilation it will come under worklib you can see in right side window.

177
 Figure no1.12: Compiled database in worklib

• Select the test bench and compile it. It will come under worklib. Under Worklib you can see
the module and testbench.

Figure no1.13: Compiled testbench database in worklib

The cds.lib file is an ASCII text file. It defines which libraries are accessible and where they are
located. It contains statements that map logical library names to their physical directory paths. For
this Design, you will define a library called “worklib”

178
Step 2: Elaboration:– To check the port connections in hierarchical design
Inputs: Top level design / test bench Verilog codes

Outputs: Elaborate database updated in mapped library if successful, generates report else error
reported in log file

Steps for elaboration – Run the elaboration command with elaborate options

1. It builds the module hierarchy

2. Binds modules to module instances

3. Computes parameter values

4. Checks for hierarchical names conflicts

5. It also establishes net connectivity and prepares all of this for simulation

Figure no1.14:
Elaboration launch option

• After elaboration
the file will come
under snapshot.
Select the test
bench and
elaborate it.

179
 Figure no1.15: Simulation launch option

Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the
output behaviour

Inputs: Compiled and Elaborated top level module name

Outputs: Simulation log file, waveforms for debugging

Simulation allow to dump design and test bench signals into a waveform

Steps for simulation – Run the simulation command with simulator options

180
Figure no1.16: Simulation Waveform Window

181
 b) Synthesize the design using Constraints and analyse reports, critical path and
Max Operating Frequency.

Step 1: Getting Started

• Make sure you close out all the Incisive tool windows first.
• Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

• In your terminal type “gedit counter_top.sdc” to create an SDC File if you do not have one.
• The SDC File must contain the following commands;

i. create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

ii. set_clock_transition -rise 0.1 [get_clocks "clk"]
iii. set_clock_transition -fall 0.1 [get_clocks "clk"]
iv. set_clock_uncertainty 0.01 [get_ports "clk"]
v. set_input_delay -max 0.8 [get_ports "rst"] -clock [get_clocks "clk"]
vi. set_output_delay -max 0.8 [get_ports "count"] -clock [get_clocks "clk"]
vii. set_input_transition 0.12 [all_inputs]
viii. set_load 0.15 [all_outputs]
ix. set_max_fanout 30.00 [current_design]

i→ Creates a Clock named “clk” with Time Period 2ns and On Time from t=0 to t=1.
ii, iii → Sets Clock Rise and Fall time to 100ps.
iv → Sets Clock Uncertainty to 10ps.
v, vi → Sets the maximum limit for I/O port delay to 1ps.

182
Step 3 : Performing Synthesis

• The Liberty files are present in the below path,

/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/

• The Available technology nodes are 180nm ,90nm and 45nm.

• In the terminal, initialise the tools with the following commands if a new terminal is being
used.
◦ csh
◦ source /home/install/cshrc
• The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
• The Following are commands to proceed,

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl counter.v
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Effort level to medium for generic, mapping
and optimization
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > counter_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > counter_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > counter_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > counter_netlist.v //Creates readable Netlist File
15. write_sdc > counter_sdc.sdc //Creates Block Level SDC

183
Synthesis RTL Schematic :

184
Commands 1-5 are intended for Synthesis process while 11-15 for Generating reports and Outputs.

Note :-
1) report_timing gives you the path with highest failing slack where
Setup Slack = Required Time – Arrival Time.

2) Worst Setup Slack ==> Highest Arrival time ==> Highest Propagation Delay.

3) Maximum Clock Frequency = 1/ (Max Data Path Delay – Min Clock Path Delay + Tsetup)

All the Information can be gathered from report_timing.

4) The Cells given in the netlist can be checked in the .lib files for their properties.

c) Compilation, Simulation and Synthesis of 32-bit Up/Down Counter.

Source Code :

`timescale 1ns/1ps //Defining a Timescale for Precision

module counter(clk,rst,m,count); //Defining Module and Port List
input clk,rst,m; //Defining Inputs
output reg [31:0]count; //Defining 4-bit Output as Reg type
always@(posedge clk or negedge rst) //The Block is executed when
begin //EITHER of positive edge of clock
if(!rst) //or Neg Edge of Rst arrives
count=0; // Both are independent events
if(m)
count=count+1;
else
count=count-1;
end
endmodule

Test Bench :

`timescale 1ns/1ps //Creating Time Scale as in Source Code

module counter_test; //Defining Module Name without Port List
reg clk, rst,m; //Defining I/P as Registers [to Hold Values]
wire [31:0] count; //Defining O/P as Wires [To Probe Waveforms]

185
initial
begin
clk=0; //Initializing Clock and Reset
rst=0;#25; //All O/P is 4’b0000 from t=0 to t=25ns.
rst=1; //Up-Down counting is allowed at posedge clk
end
initial
begin
m=1; //Condition for Up-Count
#600 m=0; //Condition for Down-Count
rst=0;#25;
rst=1;
#500 m=0;
end
counter counter1(clk,m,rst, count); //Instantiation of Source Code
always #5 clk=~clk; //Inverting Clk every 5ns
initial
#1400 $finish; //Finishing Simulation at t=1400ns
endmodule

Waveform :

The procedure for Simulation and Synthesis remains same as mentioned

earlier.

186
 Lab 2 : 4-Bit Adder

Aim: To write a verilog code for 4bit adder and verify the functionality using Test bench.
• Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total area
requirement.

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

A full adder is a combinational circuit that performs the arithmetic sum of three input bits
Ai, addend Bi and carry in C in from the previous adder. Its results contain the sum Si and the carry
out, C out to the next stage. So to design a 4-bit adder circuit we start by designing the 1 –bit full
adder then connecting the four 1-bit full adders to get the 4-bit adder as shown in the diagram
below. For the 1-bit full adder, the design begins by drawing the Truth Table for the three input and
the corresponding output SUM and CARRY.

Fig: Diagram and truth table of full adder

Fig: Diagram of 4 Bit Adder

187
Creating a Work space :
• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.
a) Verify the Functionality
• Three Codes shall be written for implementation of 4-bit Adder as follows,
◦ fa.v → Single Bit 3-Input Full Adder [Sub-Module / Function]
◦ fa_4bit.v → Top Module for Adding 4-bit Inputs.
◦ fa_test.v → Test bench

Source Code – fa.v :-

module full_adder( A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) | (CIN&(A^B));
endmodule

Source Code – fa_4bit.v :-

module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,[3:0] B,C0;
output [3:0] S,C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

Test Bench – fa_test.v :-

module test_4_bit;

reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;
wire C4;
four_bit_adder dut(A,B,C0,S,C4);
initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end
initial
#50 $finish;
endmodule

188
Waveform :

b) Synthesis and Report/Output Analysis

Step 1: Getting Started

• Make sure you close out all the Incisive tool windows first.
• Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

• As the Full Adder Program does not contain any Clock, SDC can be skipped as an Input if
you wish to, else you could include only Area Constraints in form of commands during
synthesis such as,
set_dont_use *XL (Indicating not to use Larger Cells)

Step 3 : Performing Synthesis

• The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
• The Available technology nodes are 180nm ,90nm and 45nm.
• In the terminal, initialise the tools with the following commands if a new terminal is being
used.
◦ csh
◦ source /home/install/cshrc
• The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
• The Following are commands to proceed,

189
 1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {4bi_adder.v} //Reading multiple Verilog Files
3. elaborate
4. set_top_module four_bit_adder //Differentiating Top & Sub Module
5. set_dont_use *XL //Dont Use Cells with High Driving Strength
6. set_db syn_generic_effort medium //Setting effort medium
7. set_db syn_map_effort medium
8. set_db syn_opt_effort medium
9. syn_generic
10. syn_map
11. syn_opt
//Performing Synthesis Mapping and Optimisation
12. report_timing -unconstrained > adder_timing.rep
//Generates Timing report for worst datapath and dumps into file
//-unconstrained is to be given as no timing constraints are given
13. report_area > adder_area.rep
//Generates Synthesis Area report and dumps into a file
14. report_power > adder_power.rep
//Generates Power Report [Pre-Layout]
15. write_hdl > adder_netlist.v //Creates readable Netlist File
16. write_sdc > adder_sdc.sdc //Creates Block Level SDC
17. report_qor > adder_qor.rpt // Critical slack path

Commands 1-11 are intended for Synthesis process while 12-17 for Generating reports and Outputs.

Note 1:-

1. The Cells given in the netlist can be checked in the .lib files for their properties.
2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

Synthesis RTL Schematic :

24

190
Some Common Constraints are given below for reference

Note 2:-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

191
 Lab 3 : UART
Aim: Write a verilog code for UART and carry out the following:
• To Verify the Functionality using test Bench
• Synthesize Design using constraints
• Tabulate Reports using various Constraints
• Identify Critical Path and calculate Max Operating Frequency

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

The UART is “Universal Asynchronous Receiver/Transmitter”, and it is an inbuilt IC within

a micro-controller but not like a communication protocol (I2C & SPI). The main function of UART
is to serial data communication. In UART, the communication between two devices can be done in
two ways namely serial data communication and parallel data communication.
The transmitter section includes three blocks namely transmit hold register, shift register and
also control logic. Likewise, the receiver section includes a receive hold register, shift register, and
control logic. These two sections are commonly provided by a baud-rate-generator. This generator
is used for generating the speed when the transmitter section & receiver section has to transmit or
receive the data.

Fig: UART

Creating a Workspace :
• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

192
a) Functional Verification using Test Bench

Source Code – Transmitter :

// This code contains the UART Transmitter. This transmitter is able

// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_TX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg o_TX_Serial,
output o_TX_Done
);

parameter IDLE = 3'b000;

parameter TX_START_BIT = 3'b001;
parameter TX_DATA_BITS = 3'b010;
parameter TX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 0;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data = 0;
reg r_TX_Done = 0;
reg r_TX_Active = 0;

always @(posedge i_Clock)

begin

case (r_SM_Main)
IDLE :
begin
o_TX_Serial <= 1'b1; // Drive Line High for Idle
r_TX_Done <= 1'b0;

193
 r_Clock_Count <= 0;
r_Bit_Index <= 0;

if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <= i_TX_Byte;
r_SM_Main <= TX_START_BIT;
end
else
r_SM_Main <= IDLE;
end // case: IDLE

// Send out Start Bit. Start bit = 0

TX_START_BIT :
begin
o_TX_Serial <= 1'b0;

// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish

TX_DATA_BITS :
begin
o_TX_Serial <= r_TX_Data[r_Bit_Index];

if (r_Clock_Count < CLKS_PER_BIT-1)

begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;

194
 // Check if we have sent out all bits

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= TX_STOP_BIT;
end
end
end // case: TX_DATA_BITS

// Send out Stop bit. Stop bit = 1

TX_STOP_BIT :
begin
o_TX_Serial <= 1'b1;

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT

// Stay here 1 clock

CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;

assign o_TX_Done = r_TX_Done;

endmodule

195
Source Code – Receiver :

// This file contains the UART Receiver. This receiver is able to

// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_RX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_RX_Serial,
output o_RX_DV,
output [7:0] o_RX_Byte
);

parameter IDLE = 3'b000;

parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;

reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;

// Purpose: Control RX state machine

always @(posedge i_Clock)
begin

case (r_SM_Main)
IDLE :

196
begin r_RX_DV<= 1'b0;

r_Clock_Count <= 0;
r_Bit_Index <= 0;

if (i_RX_Serial == 1'b0) // Start bit detected

r_SM_Main <= RX_START_BIT;
else
r_SM_Main <= IDLE;
end

// Check middle of start bit to make sure it's still low

RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (i_RX_Serial == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= RX_DATA_BITS;
end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles to sample serial data

RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= i_RX_Serial;

// Check if we have received all bits

if (r_Bit_Index < 7)

197
begin
r_SM_Main <= RX_DATA_BITS;
r_Bit_I
ndex
<=
r_Bit_I
ndex +
end

begin
else
r_Bit_Index <= 0;
r_SM_Main <= RX_STOP_BIT;
end
end
end // case: RX_DATA_BITS

// Receive Stop bit. Stop bit = 1

RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT

// Stay here 1 clock

CLEANUP :
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end

default :
r_SM_Main <= IDLE;

endcase
end

assign o_RX_DV = r_RX_DV;

assign o_RX_Byte = r_RX_Byte;

endmodule // UART_RX

198
Test bench :

// This testbench will exercise the UART RX.

// It sends out byte 0x37, and ensures the RX receives it correctly.
`timescale 1ns/10ps

`include "uart_tx.v"
`include "uart_rx.v"

module UART_TB ();

// Testbench uses a 25 MHz clock

// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.
parameter c_CLOCK_PERIOD_NS = 40;
parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;

reg r_Clock = 0;
reg r_TX_DV = 0;
wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;

UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst

(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)
);

UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst

(.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);

// Keeps the UART Receive input high (default) when

199
 // UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;

always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

34

// Main Testing:
initial
begin
// Tell UART to send a command (exercise TX)
@(posedge r_Clock);
@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F;
@(posedge r_Clock);
r_TX_DV <= 1'b0;
end
endmodule

Waveform :

Fig: Simulation Waveform for UART

200
b) Synthesize the Design
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib

2. read_hdl {uart_tx.v / uart_rx.v} //Choose any one

3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
35

8. syn_generic
9. syn_map
10. syn_opt //Performing Synthesis Mapping and Optimisation
11. report_timing > uart_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > uart_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. report_qor > uart_qor.rep
15. write_hdl > uart_netlist.v
//Creates readable Netlist File
16. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

Synthesis RTL Schematic :

201
c) Note :-
You can tabulate Area, Power and Timing Constraints using any of theSDC Constraints as
instructed.
1. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

202
 Lab 4 : 32-bit ALU
Aim: Write a verilog code for 32 bit ALU supporting four logical and four arithmetic operations,
use case statement and if statement for ALU behavioral modeling.
• To Verify the Functionality using Test Bench
• Synthesize and compare the results using if and case statements
• Identify Critical Path and constraints

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the
following task like addition subtraction, multi-fiction and logical operations. As the input is given in
32 bit we get 32 bit output. The arithmetic will show only one output at a time so a selector is
necessary to select one of the operator.

Creating a Work space :

• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

203
 a) To Verify the Functionality using Test Bench

Source Code – Using Case Statement :

module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; //Multiply
default:y=32'bx;
endcase
end
endmodule

Test Bench :

module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;

alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));

initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;

#10 f=3'b100;
end
initial
#50 $finish;endmodule

204
Source Code - Using If Statement :

module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation
else if (f==3'b001)
y=a|b; //OR Operation
else if (f==3'b010)
y=a+b; //Addition
else if (f==3'b011)
y=a-b; //Subtraction
else if (f==3'b100)
y=a*b; //Multiply
else
y=32'bx;
end
endmodule

Test bench :

module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end

205
 initial
#50 $finish;
endmodule

Wave Forms :

b) Synthesize Design
• Run the synthesis Process one time for each code and make sure the output File names are
changed accordingly.

Synthesis Process :
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {alu_32bit_if.v (OR) alu_32bit_case.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Optional-Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
//Performing Synthesis Mapping and Optimisation
11. report_timing > alu_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > alu_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > uart_netlist.v
//Creates readable Netlist File
15. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

206
Synthesis RTL Schematic :

Fig: Schematic Capture of 32 Bit ALU

Note :-

1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do
not overwrite the earlier ones.

207
 Lab 5 : Latches and Flip Flops

Aim : Write a verilog code for Latch and Flip-flops (D, SR, JK), Synthesize the design and
compare the synthesis report.

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus

Design Information and Bock Diagram:

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop
can store one bit of information. The main difference between latches and flip-flops is that for
latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted.
In other words, when they are enabled, their content changes immediately when their inputs
change. Flip-flops, on the other hand, have their content change only either at the rising or falling
edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising
or falling edge of the clock, the flip-flop content remains constant even if the input changes.
There are basically four main types of latches and flip-flops: SR, D, and JK. The major
differences in these flip-flop types are the number of inputs they have and how they change state.
For each type, there are also different variations that enhance their operations.

Example: D-Flip-flop

Fig: Block Diagram and truth table of D-Flip Flop

208
 Creating a Work space :
• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

a) Verilog Codes for D-Flip Flop, JK-Flip Flop and SR-Flip Flop.

Source code for D-Flip Flop :

module DFF( Q,Qbar,D,Clk,Reset);
output reg Q;
output Qbar;
input D,Clk,Reset;
always @(posedge Clk)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule

Source code for D-Latch :

module DFF( Q,Qbar,D,en,Reset);
output reg Q;
output Qbar;
input D,en,Reset;
assign Reset = ~D;
always @(en)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule

Source code for SR Flip Flop :

module Main(S,R,clk,Q,Qbar);
input S,R,clk;
output Q,Qbar;
reg M,N;
always @(posedge clk)
begin
M = !(S & clk);
N = !(R & clk);

209
 end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);
endmodule

Source Code for SR Latch :

module Main(S,R,en,Q,Qbar);
input S,R,en;
output Q,Qbar;
reg M,N;
always @(en)
begin
M <= !(S & clk);
N <= !(R & clk);
end
assign Q <= !(M & Qbar);
assign Qbar <= !(N & Q);
endmodule

Source Code for JK Flip Flop :

module jkff(J, K, clk, Q);
input J, K, clk;
output reg Q,Qm;
always @(posedge clk)
begin
if(J == 1 && K == 0)
Qm = 1;
else if(J == 0 && K == 1)
Qm = 0;
else if(J == 1 && K == 1)
Qm = ~Qm;
end
endmodule

Source of JK Latch :
module jkff(J, K, en, Q);
input J, K, en;
output reg Q,Qm;
always @(en)
begin
if(J == 1 && K == 0)
Qm <= 1;
else if(J == 0 && K == 1)
Qm <= 0;
else if(J == 1 && K == 1)
Qm <= ~Qm;
end

endmodule

210
Wave Forms for D-Flip Flop:

b) Synthesize the Design & Comparing Reports

Synthesis Commands :
1. read_libs /home/install_run/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl dff.v
3. elaborate
4. read_sdc constraints_top.sdc
5. set_db syn_generic_effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
11. report_timing > dff_timing.rep
12. report_area > dff_area.rep
13. report_power > dff_power.rep
14. write_hdl > dff_netlist.v
15. write_sdc > dff_sdc.sdc

211
Example for SDC:

The Above is the example SDC for a D Flip Flop

45

The above is an Example for SDC File for D Latch.

Synthesis RTL Schematic :

Fig: Schematic of D-Flip Flop

212
Note :-

1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed sothat the latest reports
do not overwrite the earlier ones.

213
 Lab 6 : Physical Design
Aim: For the synthesized netlist carry out the following any two above experiments:
• Floor planning, identify the placement of pads, placement and Routing

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus
• Physical Design: Innovus

Mandatory Inputs for PD:

1. Gate Level Netlist [Output of Synthesis]
2. Block Level SDC [Output of Synthesis]
3. Liberty Files (.lib)
4. LEF Files (Layer Exchange Format)

Expected Outputs from PD:

1. GDS II File (Graphical Data Stream for Information Interchange – Feed In for Fabrication
Unit).
2. SPEF, SDF

• Make sure the Synthesis for the target design is done and open a terminal from the
corresponding workspace.
• Initiate the Cadence tools and cmd :innovus (Press Enter)
• For Innovus tool, a GUI opens and also the terminal enters into innovus command prompt
where in the tool commands can be entered.

Physical Design involves 5 stages as following :

After Importing Design,
→ Floor Planning
→ Power Planning
→ Placement
→ CTS (Clock Tree Synthesis)

→ RoutingModule

Importing Design

To Import Design, all the Mandatory Inputs are to be loaded and this can be done either using script
files named with .globals and .view/.tcl or through GUI as shown below.

The target design considered here is counter design

The procedure shall remain the same for any other design from the above discussed experiments.

214
Note :

1. For Synthesis, slow.lib was read as input. Each liberty file contains a pre-defined Process,
Voltage and Temperature (PVT) values which impact the ease of charge movement.
2. Process, Voltage and Temperature individually affect the ease of currents as depicted below.

3. Hence, slow.lib contains PVT combination (corner) with slow charge movement =>
Maximum Delay => Worst Performance
4. Similarly, fast.lib contains PVT Combination applicable across its designs to give Fast
charge movement => Minimum Delay => Best Performance.
5. When these corners are collaborated with the sdc, they can be used to analyse timing for
setup in the worst case and hold in the best case.
6. All these analysis views are to be manually created either in the form of script or using the
GUI.

215
 Script under Default.globals file

Script under Default.view (or) Default.tcl file

Note : Check the paths to properly read in the input files.

• Else, if you would like to import your design using GUI, open the Innovus tool and from the
GUI, go to File → Import Design.
• A new pop-up window appears.
• First load the netlist. You can browse for the file and select “Top cell : Auto Assign”.

216
Similarly select your lef files from /home/install/FOUNDRY/digital/90nm/dig/lef/ as shown below.

Once both the Netlist and LEF Files are loaded, your import design window is as follows.

217
• In order to load the Liberty File and SDC, create delay corners and analysis view, select the
“Create Analysis Configuration” option at the bottom.

• An MMMC browser Pops Up.

218
The order of adding the MMMC Objects is as follows.
1. Library Sets
2. RC Corners
3. Delay Corners
4. Constraints (SDC)

Once all of them are added, Analysis Views are created and assigned to Setup and Hold.

In order to add any of the objects, make a right click on the corresponding label → Select New.

• Adding Liberty Files under “Library Sets”

219
• Similarly, add fast.lib with a label Fast or any identifier of your own.

• Adding RC Corners can also be done in a similar process. The temperature value can be
found under the corresponding liberty file. Also, cap table and RC Tech files can be added
from Foundry where available.

220
• Delay Corners are formed by combining Library Sets with RC Corners.
• An example is shown below.

221
• Similarly, SDC can be read in under the MMMC Object of “Constraints”.

222
• Analysis Views are formed from combinations of SDC and Delay Corner.

• Once “Best” and “Worst” Analysis views are created, assign them to Setup and Hold.

• Once all the process is done, Click on “Save&Close” and save the script generated with any
name of your choice.
• Make sure the file extension remains .view or .tcl
• After saving the script, go back to Import Design window and Click “OK” to load your
design.

223
• Add Power and Ground Net names (Identifiers) under Import design window.

224
• A rectangular or square box appears in your GUI if and only if all the inputs are read
properly.

• If the box does not appear, check for errors in your log (Either on terminal or log file from
pwd)

225
 • The internal area of the box is called “Core Area”.
• The horizontal lines running along the width of Core are “Standard Cell Rows”. Every
alternate of them are marked indicating alternate VDD and VSS rows.
• This setup is called “Flipped Standard Cell Rows”.

→ Floorplan

Steps under Floorplan :

1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]

2. Core Utilisation [The total Core Area % to be used for Floor Planning]
3. Channel Spacing between Core Boundary to IO Boundary

• Select Floorplan → Specify Floorplan to modify/add concerned values to the above Factors.
On adding/modifying the concerned values, the core area is also modified.

226
 • The Yellow patch on the Left Bottom are the group of “Unassigned pins” which are to be
placed along the IO Boundary along with the Standard Cells [Gates].

→ Power Planning

Steps under Power Planning :

1. Connect Global Net Connects
2. Adding Power Rings
3. Adding Power Strings
4. Special Route

Under Connect Global Net Connects, we create two pins, one for VDD and one for VSS connecting
them to corresponding Global Nets as mentioned in Globals file / Power and Ground Nets.

1. Select Power → Connect Global Nets.. to create “Pin” and “Connect to Global Net” as
shown and use “Add to list”.
2. Click on “Apply” to direct the tool in enforcing the Pins and Net connects to Design and
then Close the window.

227
• In order to Tap in Power from a distant Power supply, Wider Nets and Parallel connections
improve efficiency. Moreover, the cells that would be placed inside the core area are
expected to have shorter Nets for lower resistance.
• Hence Power Rings [Around Core Boundary] and Power Stripes [Across Core Boundary]
are added which satisfies the above conditions.
• Select Power → Power Planning → Add Rings to add Power rings ‘around Core Boundary’.

228
 • Select the Nets from Browse option OR Directly type in the Global Net Names separated by
a space being Case and Spelling Sensitive.
• Select the Highest Metals marked ‘H’ [Horizontal] for Top and Bottom and Metals marked
‘V’ [Vertical] for Right and Bottom. This is because Highest metals have Highest Widths
and thus Lowest Resistance.
• Click on Update after the selection and “Set Offset : Centre in Channel” in order to get the
Minimum Width and Minimum Spacing of the corresponding Metals and then Click “OK”.
• Similarly, Power Stripes are added using similar content to that of Power Rings.

Factors to be considered under Power Stripes :

→ Nets
→ Metal and It’s Direction
→ Width and Spacing [Updated]
→ Set to Set Distance = ( Minimum Width of Metal + Min. Spacing ) x 2

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 • On adding Power Stripes, The Power mesh setup is complete as shown. However, There are
no Vias that could connect Metal 9 or Metal 8 directly with Metal 1 [VDD or VSS of
Standard Cells are generally made up of Metal 1].
• The connection between the Highest and Lowest Metals is done through Stacking of Vias
done using “Special Route”.
• To perform Special Route, Select Route → Special Route → Add Nets → OK.
• After the Special Route is complete, all the Standard Cell Rows turn to the Color coded for
Metal 1 as shown below.

The complete Power Planning process makes sure Every Standard Cell receives enough power to
operate smoothly.

→ Pre – Placement :

• After Power Planning, a few Physical Cells are added namely, End Caps and Well Taps.
• End Caps : They are Physical Cells which are added to the Left and Right Core Boundaries
acting as blockages to avoid Standard Cells from moving out of boundary.
• Well Taps : They act like Shunt Resistance to avoid Latch Up effects.

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To add End Caps, Select Place → Physical Cell → Add End Caps and “Select” the FILL’s from the
available list.

• Higher Fills have Higher Widths. As shown Below, The End Caps are added below your
Power Mesh.

• To add Well Taps, Select Place → Physical Cell → Add Well Tap → Select →FillX [X →
Strength of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of 30-45u] → OK

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→ Placement
1. The Placement stage deals with Placing of Standard Cells as well as Pins
2. Select Place → Place Standard Cell → Run Full Placement → Mode
→ Enable ‘Place I/O Pins’ → OK → OK .
1.

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• All the Standard Cells and Pins are placed as per the communication between them, i.e.,
Two communicating Cells are placed as close as possible so that shorter Net lengths can be
used for connections as Shorter Net Lengths enable Better Timing Results.

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 • You can toggle the Layer Visibility from the list on the Right. The List of Layers available
are shown on the right under “Layer” tab with colour coding.

→ Report Generation and Optimization :

1. Timing Report :
1. To generate Timing Report, Timing → Report Timing → Design Stage – PreCTS
2. Analysis Type – Setup → OK
3. The Timing report Summary can be seen on the Terminal.
2. Area Report :
1. cmd : report_area
3. Power Report :
1. cmd : report_power

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• In case of any Violating paths, the design could be optimized in the following way.
• To optimize the Design, Select ECO → Optimize Design → Design Stage [PreCTS] →
Optimization Type – Setup → OK

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 After you run the optimization, the terminal displays the latest Timingreport and updated area
and power reports can be checked.

• This step Optimizes your design in terms of Timing, Area and Power. You can Generate
Timing, Area, Power in similar way as above report Post – Optimization to compare the
Reports.

Clock Tree Synthesis

• The CTS Stage is meant to build a Clock Distribution Network such that every Register
(Flip Flop) acquires Clock at the same time (Atleast Approximately) to keep them in proper
communication.
• A Script can be used to Build the Clock Tree as follows :

• Source the Script as shown in the above snapshot through the Terminal and then Select
Clock → CCOpt Clock Tree Debugger → OK to build and view clock tree.

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 • The Red Boxes are the Clock Pins of various Flip Flops in the Design while Yellow
Pentagon on the top represents Clock Source.
• The Clock Tree is built with Clock Buffers and Clock Inverters added to boost up the Clock
Signal.

Report Generation and Design Optimization :

• CTS Stage adds real clock into the Design and hence “Hold” Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports are to
be Generated for Setup and Hold Individually.

Setup Timing Analysis :

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Hold Timing Analysis :

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Routing :
All the net connections shown in the GUI till CTS are only based onthe Logical connectivity.
1. These connections are to be replaced with real Metals avoiding Opens, Shorts, Signal
Integrity [Cross Talks], Antenna Violations etc.
2. To run Routing, Select Route → Nano Route → Route and enable Timing Driven and SI
Driven for Design Physical Efficiency and Reliability.

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Area and Power Reports :
Use the commands report_area and report_power for Area and Power
Reports respectively.

• As an alternate to the setAnalysisMode command, you can use the GUI at Tools → Set
Mode → Set Analysis Mode → Select On-Chip-Variation and CPPR.

• The Report generation is same as shown prior to Design Optimization.

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It is recommended to save Netlist and Design at every stage.

To restore a Design Data Base, type source <DesignName>.enc in the terminal.

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 Physical Verification – Capturing DRC and LVS :

• After saving the routed Database, you can proceed for Physical Verification and capture the
DRC and LVS reports.
• Inputs Required – DRC :
◦ Technology Library and Rule Set
◦ GDS format giles of all Standard Cells (Given by Cadence at
/home/install/FOUNDRY/90nm/dig/gds for 90nm Tech node)

Outputs – DRC :
◦ DRC Violation Report
◦ Physical Netlist (Optional)

From the Innovus GUI, select PVS → Run DRC to open the “DRC Submission Form

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The DRC Run Submission Form begins with mentioning the Run Directory. The Run Directory is
the location where all the logs, reports and other files concerned with PVS are saved.

The technology Library is to be loaded under “Rules tab”.

• The Technology Library is specific for PVS Tool and technology node on which the design
is created.
• On reading the tech lib, the rule set is loaded and the corresponding fabrication rules are
read in to be checked against the design.

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• The GDS format files of all standard cells available with the corresponding technology node
are also provided by the vendor. Select all of them to add.

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• The output report can be named and saved as shown.

• Hit “Submit” to run the DRC and the following windows appear.

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• All the list of DRC Errors can be seen in the above window of which the location of the
DRC Violation occuring can be highlighted dealing one to one.

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• For example, in the above shown snapshot, the errors associated with N-Implant can be
seen. (Select a error occurrence and click on the right arrow below to highlight/zoom in the
location.)
• You can save the DRC Run as a “Preset” file to rerun the DRC if required at a later point of
time.
• Saving/loading the Preset File is shown below.

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 • Loading a Preset file is shown below.

Note : A Physical Netlist can be saved after the DRC Run as shown below.

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• Inputs Required – LVS :
◦ Technology Library
◦ Standard Cell GDS Files
◦ Spice Netlist of all Standard Cells (Provided by Library Vendor)
• Outputs – LVS :
◦ LVS Match/Mismatch Report

• From the Innovus GUI, Select PVS → Run LVS to open the LVS run submission form.

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• Provide the Run directory and log file name (Along with path – Optional)
• Load the Tech Lib, GDS Files and Spice Netlist of all Standard Cells under the
corresponding technology node.

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• On successful completion of LVS Run, the following windows appear.

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• You can create a GDS file along with Stream out file either using the GUI as File → Save →
GDS/Oasis or use the following command.
• Cmd : streamOut <GDSFileName>.gds -streamOut <streamOut>.map

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