HARDWARE ARCHITECTURE

OF EMBEDDED SYSTEMS
Dr. Kavitha A K
AP(Sr. Gr.)
Department of Electronics and Communication Engineering
Sri Ramakrishna Institute of Technology, Coimbatore
2 Detailed Hardware Design
The components of embedded systems consist of
hardware and software elements that work together to
enable the desired functionality of the system.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
3
Embedded Systems
The components of embedded systems consist of hardware and software
elements that work together to enable the desired functionality of the system.

Image Source – Google.com

Image Source – Google.com
Hardware Architecture of Embedded System
 EMBEDDED SYSTEM DESIGN PROCESS
4

 Design process:
 Design Process is a way of figuring out what is needed to be
done in developing an embedded product.
 It describes design procedures, techniques, tools and design flow
steps at various levels of abstraction.
 Abstraction:
 Abstraction is the main concept in design process.
 Abstraction of design means presenting essential features of
implementation and hiding the minor or background details

Hardware Architecture of Embedded System

 Architecture design
5

 What major components go satisfying the specification?

 Hardware components:
 CPUs, peripherals, etc.
 Software components:
 major programs and their operations.
 Must take into account functional and non-functional
specifications.
Hardware Architecture of Embedded System
 Functional vs. non-functional requirements
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 Functional requirements:
 output as a function of input - (basic functions of the embedded
system)
 Non-functional requirements:
 Performance (speed, time)
 Cost(manufacturing cost, NRE- Non-Recurring Engineering cost)
 Physical size, weight, etc.
 power consumption
 reliability

Hardware Architecture of Embedded System

 Central Processing Unit
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 The Central Processing Unit (CPU) used in an embedded system can

be one of the following two categories:
 General Purpose Processor (GPP)
 Digital Signal Processor (DSP).
 The GPPs are further classified as micro-controllers and
microprocessors.
 A micro-controller has memory and other peripherals on the chip
itself; hence, it is the best choice for small embedded systems.
 On the other hand, a microprocessor is more powerful but requires
a large number of external components.

Hardware Architecture of Embedded System

 Embedded System Hardware Architecture
8

General Purpose
ALU
Register

Memory Address
Stack Pointer Address Bus
Register

Memory Data
Instruction Pointer Data Bus
Register

Control and
Instruction Decoder Status Bus

Building Blocks of the Hardware in an Embedded Systems

Internal Architecture of a Process
Hardware Architecture of Embedded System
 Central Processing Unit (contd.,)
9

The CPU consists of

 Arithmetic Logic Unit (ALU) which performs arithmetic and logic
operations (such as add, multiply, subtract, etc.)
 General purpose registers:
 These registers constitute the processor's internal memory. The number of
registers varies from processor to processor.
 Registers contain the current data and operands that are being
manipulated by the processor.
 When a processor is referred to as of 8-bits, 16-bits etc., it refers to the
width of the registers.

Hardware Architecture of Embedded System

 Central Processing Unit (contd.,)
10

 Control unit - fetches the instructions from memory, decodes them

and executes them.
 A control unit consists of:
 Instruction Pointer that points to the next instruction to be executed.
Instruction Pointer is also called Program Counter.
 Stack Pointer - points to the stack in the memory. In the external
memory, the processor implements a stack. When required, the contents
of registers are transferred to this stack. The processor keeps track of
the next free location in the stack through stack pointer.
 Instruction Decoder that decodes the instructions.
 Memory Address Register and Memory Data Register

Hardware Architecture of Embedded System

 Von Neumann architecture
11

 Memory holds data, instructions.

 Central processing unit (CPU) fetches instructions from
memory.
 Separate CPU and memory distinguishes programmable
computer.
 CPU registers help out: program counter (PC), instruction
register (IR), general-purpose registers, etc.,.
Hardware Architecture of Embedded System
 Computer Architecture in terms of Instruction Set
12

 Complex instruction set computer (CISC):

 many addressing modes;

 many operations

 Different instruction formats of varying lengths.

 Reduced instruction set computer (RISC):

 load/store; (data operands must first be loaded into the CPU and then stored back to main
memory to save the results.)
 Fewer and simpler instructions
 pipelinable instructions.

Hardware Architecture of Embedded System

 Processor Architectures
13

 In addition to manipulating data, a processor's job is to read data and

instructions from memory, read and write data to memory, write data to
output devices, and read data from input devices.
 To do these functions, the processor communicates with other devices
using three buses, a bus being a group of signals. These buses are:
 Data bus which carries the data between the processor and other devices.
This bus is bi-directional.
 Address bus which carries the address information from the processor to
memory, and hence this bus is unidirectional.
 Control and Status bus which carries control/status information such as
whether the operation is read or write, indication of address error, as well as
processor reset signal, clock input and Interrupt signals. This bus is bi-
directional. Generally, this bus is not explicitly shown in figures.
Hardware Architecture of Embedded System, Dr. Kavitha A K
 Processor Architectures
14

Fig. shows the interaction between the CPU and memory using these three buses.

Hardware Architecture of Embedded System

 Processor Architecture Types
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 Based on the number of memory and data buses used,

there are three types of architectures for the processors.
 These are:
 Von Neumann Architecture
 Harvard Architecture

 Super Harvard Architecture

Hardware Architecture of Embedded System

 CPU + memory - Von Neumann
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• The von Neumann architecture

is the most widely used
architecture.
• This architecture, has one
memory chip which stores both
instructions and data.
• The processor interacts with
the memory through address
and data buses to fetch
instructions and data.

Hardware Architecture of Embedded System

 Instruction sets preliminaries
17

 Instruction sets- “The programmer’s interface to the hardware”

 The instruction set is the key to analyze the performance of programs.
 By understanding the types of instructions that the CPU provides, insight
into alternative ways to implement a particular function can be gained

A von Neumann architecture computer A Harvard architecture

Hardware Architecture of Embedded System
 Harvard architecture
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 There are two separate memory blocks one is program

memory and the other is data memory.
 Program memory stores only instructions and data memory
stores only data.
 Two pairs of data buses are used between the CPU and
the memory blocks.
 Program memory address bus and program memory data
bus are used to access the program memory.
 Data memory address bus and data memory data bus
are used to access the data memory.
 This architecture is much more efficient because accessing
the instructions and data will be very fast.
Advantages of Harvard : Separation of data and program memory provides high performance
for DSP
Hardware processors
Architecture of Embedded System
 Which Architecture is Best Suited for µp and DSP?
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Von Neumann Architecture Harvard Architecture

Stored program concept
(stores program code along with
data)
A Harvard Architecture,
Von Neumann Memory common to many DSP
Architecture, common among Processors.
micro controllers. The processor can
Since there is only one data simultaneously access the
bus, operands cannot be two memory banks using
loaded while instructions are independent sets of
fetched, creating a bottle buses, allowing operands
neck that slows the execution to be loaded while
of DSP Algorithms. fetching instructions.
Hardware Architecture of Embedded System
 Super Harvard Architecture
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 The Super Hardvard Architecture

(SHARC) a slight but significant
modification of the Harvard architecture.
 In Harvard architecture, the data
memory is accessed more frequently than
the program memory.
 Therefore, in SHARC, provision has been
made to store some secondary data in
the program memory to balance the load
on both memory blocks.
 This architecture, proposed by Analog
Devices, is used extensively in Digital
Signal Processors.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
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Embedded Systems

Interrupts

Hardware Architecture of Embedded System

 Interrupts
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 It is a signal to the processor that some important event has occurred.

 For example, the processor does not keep on checking whether you are pressing a key on the keyboard.
 Whenever a key is pressed, an interrupt goes to the processor and then the processor reads the key
pressed.
 Corresponding to each interrupt, there will be an Interrupt Service Routine (ISR) that will be executed.
 But, before executing the ISR, the processor has to temporarily halt the work it is doing. So, it saves the
contents of the registers by pushing the register values and stack pointer onto the stack.
 Then the processor loads the interrupt vector, i.e. the address at which the ISR is lying, into the Program
Counter. (a register that stores the address of the next instruction to be executed)
 After execution of the ISR, the processor reloads the registers and the stack pointer, and resumes the
previous execution.
 There may be more than one interrupt to the processor. Hence, priorities are assigned to the interrupts so
that the processor executes the highest priority interrupt.
Hardware Architecture of Embedded System
 Interrupts Contd.,
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 A Programmable Interrupt Controller (PIC) interfaces with the CPU to handle

external devices and decide which interrupt has to be processed.
 An interrupt table contains the details of various interrupts such as interrupt
number (IRQ), the memory location where the ISR is stored (interrupt vector),
priority of the interrupt and the frequency with which the interrupt is likely to
occur.
 Interrupt that has to be processed immediately is called Non-Maskable
Interrupt (NMI).
 Many processors have NMI request lines.
 For example, if a reset button is pressed then its corresponding interrupt is
processed immediately.
 The processor does not wait for some other work to be completed before
resetting the system.
Hardware Architecture of Embedded System
 Interrupts Contd.,
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CISC and RISC

 Processors are divided into the following categories:

 Complex Instruction Set Computer (CISC)

 Reduced Instruction Set Computer (RISC)

Hardware Architecture of Embedded System

 Interrupts Contd.,
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 CISC (Complex Instruction Set Computer) is characterized by its large instruction set.
 A large number of instructions are available to program the processor.
 So, the number of instructions required to do a job is very less and hence less memory is
required.
 The number of registers in CISC processors is very small.
 The aim of designing CISC processors is to reduce the software complexity by increasing
the complexity of the processor architecture.

Examples are: Intel x86 family and Motorola 68000 series processors.

Hardware Architecture of Embedded System

 Interrupts Contd.,
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 RISC (Reduced Instruction Set Computer) is characterized by its limited number of

instructions.
 A complex instruction is obtained as a sequence of simple instructions.
 So, in RISC processors, the software is complex but the processor architecture is simple.
 However, large number of registers are required in RISC processors, which are of small
size and consume less power.
 Another feature of RISC processors is the pipelined instruction execution.
 While one instruction is being executed, second instruction is decoded and the third
instruction is fetched leading to faster execution of the program.
 Embedded systems generally use RISC processors.
Examples are ARM. ATMEL AVR, MIPS, Microchip PIC, Power PC and Sun SPARC.
Hardware Architecture of Embedded System
 Interrupts Contd.,
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 There are nearly 150 processors manufactured by about 50 semiconductor

manufacturers.
 The specifications of these processors differ significantly.
 While evaluating the processor, the following specifications are to be considered:
1. Clock Speed
2. Length of Registers
3. Width of Database and Address Bus
4. Number of Registers, Internal RAM
5. Internal ROM
6. On-Chip Peripherals such as Timer, UART, ADC, DAC
7. Interrupt Lines,
8. Number of Programmable I/O Lines.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
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Embedded Systems

Memory

Hardware Architecture of Embedded System

 Memory
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The memory is divided into two categories:

 Program Memory and Data Memory.
 The program memory stores the firmware permanently whereas data memory contents
are erased when power is switched off.
 Both program memory and data memory can be internal to the processor (as in the case
of a micro-controller) or it can be external memory.
 In a micro-controller, both program memory and data memory are on chip.
 If the capacity of the internal memory is not sufficient, you can use external memory chips to
increase the memory capacity.
 Memory chips are classified as:
Random Access Memory (RAM), Read-Only Memory (ROM), & Hybrid Memory
Hardware Architecture of Embedded System
 Memory
30
Random Access Memory (RAM)
 In RAM, the memory locations can be accessed randomly and it is a read-write chip
 RAM is of two types:
 Static RAM (SRAM)
 SRAM loses its contents the moment power is switched off to the chip.
 SRAM is faster and consumes less power.

 Dynamic RAM (DRAM)

 DRAM retains its contents for a fraction of a second even if power is supplied continuously to
the chip. To keep its contents intact, DRAM has to be refreshed periodically.
 A DRAM controller is used to carry out this operation.
 The main attraction of DRAM is that it is very cheap and hence it is used when a high-capacity
RAM is required but the chip has to be of low cost.
 DRAM is used in handheld computers. Hundai HM 62256 BLP-7 is an SRAM chip with 32 KB
capacity and an access time of 70 nanosec.
Hardware Architecture of Embedded System
 Memory
31
Read Only Memory (ROM)
 ROM is used to store the firmware in embedded systems because it retains
its contents even if power is switched off.
 How do you write data into the ROM chip first time?
 Some ROMs are fused in the factory, i.e. data is written in the factory
and then shipped.
 A variety of ROMs are available with different capabilities.

 These are:
 Programmable ROM
 Erasable Programmable ROM.

Hardware Architecture of Embedded System

 Memory
32
Read Only Memory (ROM)
 Programmable ROM (PROM):
 PROM devices can be programmed only once. When your firmware is
ready, put it on the PROM and then mount the device on your embedded
system. Well, if your firmware has a bug, you need to throw that PROM.
 Erasable Programmable ROM (EPROM):
 EPROM can be programmed many times. To write data into, EPROM, you
need an EPROM Programmer. Also, you need a tool called EPROM Eraser
to erase the contents.
 An EPROM Eraser applies Ultra Violet (UV) radiation to the device to
erase the contents. As compared to RAM, ROMs are slower.
Hardware Architecture of Embedded System
 Memory
33
Hybrid memory devices
 Electrically Erasable PROM (EEPROM):
 EEPROM is similar to EPROM but its contents can be erased by applying electrical
signal to one of the pins of the device.
 Non-Volatile RAM:
 Non-Volatile RAM is SRAM with a battery backup.

 So, even if power is switched off, the battery will ensure that the contents are not
erased.
 Flash memory:
 Flash memory is type of EEPROM.

 These low-cost chips are characterized by their fast read quality (but not fast write).

 The memory is divided into sectors or blocks. Typical sector size is 256 bytes to 16 KB.
Hardware Architecture of Embedded System
 Memory
34
Hybrid memory devices
 Flash memory: Contd.,
 Each sector is an erasable unit. When erased, the bits in that sector are set to 1.

 As it is electrically erasable, contents of the Flash memory can be updated in the

embedded system.
 Flash memory is nowadays extensively used in embedded systems for scoring the
firmware.
 Attractive feature of Flash - it can be used as a 'disk' by developing a Flash file system, so
that data can be accessed through file names rather than through memory addresses.
 A sector in a Flash memory chip can last about one million erase cycles
 ATMEL'S AT25080 (1 KB), AT25160 (2KB), AT25320 (4 KB), AT25640 (8KB) are the
EEPROMS. AMD's AM29F010 is a Flash device of 128 KB capacity

Hardware Architecture of Embedded System

 Memory in Embedded Systems
35

EEPROM and Flash are the most widely use memory

chips because they are in-circuit programmable.

PROCESSOR

Address Bus

Data Bus

FLASH
EEPROM MEMORY
RAM

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
36
Embedded Systems
Clock Circuitry

Hardware Architecture of Embedded System

 Real Time clock will be used in the
Clock Circuitry embedded systems to provide “real”
time including the data
37

 The processor has to be given the clock input to one of the pins.
 To generate the clock signal, a crystal and oscillator are required.
 For some processors, the oscillator circuitry is in-built, only external crystal has to be
added to generate the clock signal.
 Real Time Clock (RTC) keeps track of the date and time.
 All processor events are related to the clock.
 The higher the clock frequency, the higher the speed of the processor.
 However, different processors cannot be compared based on clock speed alone.
 One processor may take one clock cycle for executing an instruction, whereas another
processor may take 16 clock cycles to execute the same instruction.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
38
Embedded Systems
Watchdog Timer / Reset Circuitry
Watchdog timer is used to reset the processor automatically if it does not
receive a signal periodically from the processor indicating its healthy status.
This mechanism obviates the need for a reset button on the embedded system.

Hardware Architecture of Embedded System

 Watchdog Timer / Reset Circuitry
39

 Most embedded systems do not have a reset button.

 Due to some software or hardware error, a need may arise to reset the processor.
 The watchdog timer does the resetting.
 A timer is set to a large value and it is decremented slowly.

 If the timer value reaches zero, the processor is reset through a reset-signal.

 If everything is going on fine, intermittently, the timer value is again set to the large value.

 If a reset button is provided in an embedded system, on pressing the button, a reset signal is
sent to the processor.
 Alternatively, the processor sends a periodic signal to the reset circuit indicating that does not
receive this signal, then the processor is reset. it is healthy.
 If the reset circuitry does not receive the signal then the processor is reset.
Hardware Architecture of Embedded System
 Detailed Hardware and Software Design of
40
Embedded Systems
Chip Select
As many peripherals (different memory chips and input/output devices) share a
common bus, the processor must be able to uniquely identify a peripheral to
communicate with it.
The processor performs this identification using a signal called Chip Select (CS).
The Chip Select signal is available to all the peripherals connected to the bus.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
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Embedded Systems
Input / Output Devices

Hardware Architecture of Embedded System

 Input/Output (I/O) Devices
42

 I/O devices can be categorized as

 Programmed I/O
 Interrupt-driven I/O.
 In programmed I/O the processor sends the data to the
device on its own.
 In interrupt driven I/O, the processor is interrupted by an
interrupt signal and the ISR is executed.
 ISR transfers the data from the input device to the memory or
memory to output device.

Hardware Architecture of Embedded System

 Input/Output (I/O) Devices
43

 Generally, data transfer between the I/O device

and the memory is coordinated by the CPU. CPU
DMA
Controller
 In cases where handling of the I/O device by the
processor is not efficient, data transfer between the
I/O device and the memory can take place
directly, which is known as DMA.
 A special device called DMA controller does the
Memory I/O Device
job.
 DMA controller takes the control of the buses and
transfers data between the I/O device and the Fig. Dynamic Memory Access
memory.
Dynamic Memory Access facilitates transfer of data between the input/output device and the
memory directly without the intervention of the processor.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
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Embedded Systems
Sensors and Transducers

Embedded systems need to convert real-life information into

equivalent electrical signals. This is achieved through sensors and
transducers.

Hardware Architecture of Embedded System

 Sensors and Transducers
45

Some important sensors and transducers are listed below:

• Temperature sensors : -
• Converts temperature into an equivalent electrical voltage.
• The output of the sensor is a signal whose voltage level is proportional to the temperature.
• Measurement of temperatures in air-conditioners, boilers, coffins etc. is done through this
sensor.
• Analog Devices AD22100, AD22103 and Dallas Semiconductors' DS 18B20 are examples of
temperature sensors.
• Light sensors : -
• Converts light intensity into an equivalent electrical voltage.
• The output of the sensor, the voltage level, is proportional to the light incident on the sensor.
• The light is sensed through a photodiode, and an in-built amplifier amplifies the voltage level.
An example is Texas Advanced Optical Solutions' TAOS TSL250R.

Hardware Architecture of Embedded System

 Sensors and Transducers
Some important sensors and transducers Contd.,:
46

• Accelerometer
• Converts the acceleration into voltage.
• The voltage is proportional to the acceleration of a vehicle.
• ADXL 150/250 does this job.
• Pressure sensors:
• Convert the pressure level to voltage level.
• Pressure sensors are used in blood pressure equipment, and to measure altitude of
aircraft, ocean depth etc.
• MPXA 6115A is an example.
• Microphone and speakers:
• Microphone converts the acoustic energy into a voltage signal.
• When you speak into a microphone, the output of the microphone is an electrical signal
with continuously varying amplitude.
• The speakers convert the electrical signal back into acoustic waves.
Hardware Architecture of Embedded System
 Sensors and Transducers
Some important sensors and transducers Contd.,:
47

• Video camera and monitor:

• The real-life image or scenery is converted into electrical signal image or scenery is
converted into electrical signal using a video camera.
• The video camera output is a continuously varying electrical signal.
• The electrical signal is converted back to the image on a monitor.
• Sensors and transducers convert the real life information into equivalent electrical signals these
analogue signals are converted into digital format to be processed by the processor.
• The electrical signals produced by these sensors and transducers are analog signals.
• Their amplitude varies continuously with time. However, the computing devices are digital.
• They can process only digital data.
• Hence, we need to convert the analog signals into digital signals.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
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Embedded Systems
ADC and DAC

Hardware Architecture of Embedded System

 ADC and DAC
49

 The analog signals produced by sensors and transducers

have one important characteristic: bandwidth.
 The bandwidth of a signal is the highest significant frequency
component present in the signal.
 For instance, voice signals have a bandwidth of 4 KHz, ie, the
frequency components above 4 KHz are insignificant.
 The analog signal can be converted into digital format in two
stages:
 Sampling and
 Quantization.
 In sampling, the amplitude levels of the signal are measured The sample value shown in Fig. lies between 250 and
at regular intervals 251. So, the sample value is approximated to 250.
 In quantization, the sampled value is converted into a
number. Hardware Architecture of Embedded System
How many samples are required to correctly
represent an analog signal?
50

 Nyquist theorem provides the answer.

 If the bandwidth of a signal is B Hz, the number of samples required per second (called the
sampling rate) should be at least 2B.
 So, for voice signals with a bandwidth of 4 KHz, the minimum sampling rate is 8000
samples per second.
 These samples are quantized by dividing the complete range of amplitudes into say 256
levels. These levels are called quantization levels.
 To represent the 256 levels, 8 bits are required.
 Hence, to represent each sample value, 8 bits are required.
 To represent 4096 levels, 12 bits are required.

Hardware Architecture of Embedded System

 ADC and DAC
51

 This process of sampling and quantization is done ADC chips.

 The reverse process of converting the digital signal to analog signal is done through DAC.
 Analog-to-digital conversion introduces error because each sample value is rounded off to its
nearest quantization level. This error is known as quantization error.
 By increasing the number of quantization levels, the quantization error can be reduced.
 Another important aspect in analog-to-digital conversion is the sampling rate.
 If the sampling is done at a rate lower than the Nyquist sampling rate, then the analog signal is
not represented correctly and the effect is known as aliasing.
 While choosing the ADC and DAC chips, the two important characteristics are to be considered:
1. Sampling rate

2. Resolution
Hardware Architecture of Embedded System
 ADC and DAC
52

 Consider the voice signals

 In telephone networks, the voice signals are considered to have a bandwidth of 4 KHz and
the resolution is 8 bits.
 In CD audio, the bandwidth is considered to be 44.1 KHz and 16-bit resolution is used and
hence the quality of CD audio is very high.
 In DVD audio, the bandwidth is considered as 48 KHz, and the resolution is 24 bits.
 Consider a temperature sensor
 It produces an electrical signal whose amplitude is proportional to temperature.

 To measure the temperature with an accuracy of 0.5 degrees between 0 and 50 degrees,
we need 100 levels.
 So, an ADC of 7 bits is enough.
 As 7-bit ADC's are not available, we choose an 8-bit ADC.
Hardware Architecture of Embedded System
 ADC and DAC
53

Key points to remember

(a) Analog-to-Digital Conversion (ADC) involves two steps: sampling; and
quantization.
(b) The analog signal is sampled at regular intervals and the sampled
values are rounded off to fixed number of levels called quantization
levels.
(c) These quantized values are converted into bit stream.

According to Nyquist theorem, a signal of bandwidth B has to be

sampled with a minimum sampling rate of 2B so that the signal can
be reconstructed without any distortion.
Hardware Architecture of Embedded System
 Function Keypad for Tape Recorder Functionality
54

Based on the application, an embedded system has

to be provided with a function keypad to input data
and or commands.
A representative function keypad shown in figure.
This Keypad has been designed to do the functions
of controlling a tape recorder.
It has various buttons for Play, record, pass, forward,
go to first file, go to Last file, etc.,
Based on the application needs you need to design
your keypad and interface it to the processor circuitry.

Hardware Architecture of Embedded System

 Light Emitting Diodes (LEDs)
55

 LED's are the most widely used output devices

in embedded systems.
 Red, green, and yellow LED are used for
status display as well as for indication of
visible alarm for such events, like power
supply failure.
 Blue and white lEDs are also available but
they are very expensive.

Hardware Architecture of Embedded System

 Liquid Crystal Display (LCD)
56

 In LCD, liquid-crystal solution is sandwiched by two sheets for polarizing material.

 LCD is used to display the status information or to display prompts to the user.
 The display can be as small as 1 Line with 8 characters.
 Other displays used in embedded systems can be of 6.4 inch or 8.4 inch etc.
 The diagonal distance is indicated as display size.
 Resolution can be 640*480 or 1024 * 768 etc.
 The display driver circuitry is connected to the processor
 Display technology is changing very fast.
 Thin Film Transistor (TFT) displays provide very high-resolution display.
 TFT displays are used in mobile phones.
Hardware Architecture of Embedded System
 Liquid Crystal Display (LCD)
57

 Another innovation is 3-dimensional displays in which two LCDs are used to give the 3-
dimensional effect.
 Another type of display that is now making inroads is Organic Light Emitting Diode
(OLED) display in which any organic light-emitting polymer is placed between anode
and cathode.
 When a voltage is applied between anode and cathode, the organic material glows
OLED gives a much brighter display as compared to LCD and is now being used on
mobile phones and PDAs.

LCD, TFT and OLED displays of different sizes and resolutions

are used to display status information and prompts.

Hardware Architecture of Embedded System

 Detailed Hardware and Software Design of
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Embedded Systems
Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI) uses a set of 4 signals for interfacing

peripherals to the processor.
RTC, EEPROMS, Flash memory etc. can be interlaced using SPI.

Hardware Architecture of Embedded System

 Serial Peripheral Interface (SPI)
59

 SPI was developed by Motorola.

 Peripheral devices such as memory chips, potentiometers, ADCs and DACS, Real-Time Clock
etc. are provided with SPI interface so that they can be interfaced to the processor.
 The processor generates the clock and the peripheral uses the clock to synchronize to
acquisition of the data.
 SPI users four type of signals for interfacing peripherals to the processor
 Master Out Slave In (MOSI)

 Master In Slave Out (MISO)

 Serial Clock (SLCK)
 Chip Select (CS) for the peripheral

Hardware Architecture of Embedded System

 Serial Peripheral Interface (SPI)
60

 SPI is based on the master-slave protocol.

 The processor acts as the master and the peripheral acts as the slave.
 The processor and the peripheral are connected using these 4 signals.
 Both the master and the slave contain shift registers.
 The master sends a byte to the slave on MOSI line, and the slave sends its register contents
on MISO line.
 Both write and read can be done simultaneously.
 If the master has to read a byte from the slave, it had to write a dummy byte to initialize
the slave for transmission.
 This is a synchronous protocol for communication between the processor and the peripheral.
 DS 1305 Real Time Clock (RTC), AD 5203 digital potentiometer, ATMEL AT45DB161 2MB
serial data flash, AT25640 EEPROM SKB, AT25080 1KB, AT25160 2KB, AT25320 4 KB
EEPROMs can also be interfaced using SPI pins.

Hardware Architecture of Embedded System

 Serial Peripheral Interface (SPI)
61

 The bus consists of two lines serial clock (SCL) and serial data
(SDA).
 Both lines remain high, when Not in use.
 A device using the bus drives the line low.
 Each device has a unique address of 7bits or 10 bits.
 If 7 bits are used 128 devices can be connected to the bus.
 A device can act as a master or slave.
 Transmitting device is the master and the receiving device is Figure : I 2C bus uses to connecting devices as
slave. shown in figure. the buses are bidirectional and
 The same line is used for master transmission and slave synchronous to a common clock microcontroller
with built in PC and available data rates of 100
response. KBPS (standard mode)and 100 MBPS (fast
 I2C bus is a multi-master bus. mode) are supported.

 More than one device can act as master.Hardware Architecture of Embedded System
 Debug Port
62

 Debugging a processor-based board is very difficult.

 Earlier, many processor manufacturers used to provide proprietary interfaces to do the
debugging. J
 Joint Test Access Group (TAG) standardized a mechanism for providing the debugging through
a pore called JTAG port.
 JTAG port provides access to the internals of the processor.
 The standard IEEE 1149.1a-1993 (Standard Test Access Port and Boundary Scan Architecture)
gives the details of the protocols used in JTAG port.
 Using technique known as Boundary Scan, the connections between the processor and the
memory/peripherals can be probed by given appropriate signals at the output pins and
reading the response from input pins.

Hardware Architecture of Embedded System

 Debug Port
63

 JTAG port consists of 4 signals:

 Test Data Input (TDI)
 Test Data Output (TDO)
 Test Mode Select (TMS)
 Test Clock (TCK)
 JTAG port is like a synchronous serial interface.
 JTAG port can also be used to download the software onto the embedded system.

Joint Test Access Group (JTAG) port is a standardized port to access the
internal circuitry of the processor. JTAG port is used for debugging as well as
to download the software, on to the embedded system.

Hardware Architecture of Embedded System

 Communication Interfaces
64

 For embedded systems to interact with the external world, a

number of communication interfaces are provided.
 These are:
 Serial interface using RS232
 Serial interface using RS422/RS485
 Universal Serial Bus (USB)
 Infrared/
 Ethernet
 Wireless interface based on IEEE 802.11 Wireless LAN standard
 Bluetooth radio interface

Hardware Architecture of Embedded System

 Power Supply Unit
65

 An embedded system operates either through a 230 V mains supply or through a battery.
 Since the components in the embedded system require different DC voltages such as +12
volts, -12 volts, +5 volts, +3.3 volts etc., a Power Supply Unit (PSU) is required which
provides stable DC voltages from the mains or battery.
 An AC adapter converts the mains supply to +5 volts to +12 volts DC supply giving a
current up to 500 mA.
 The batteries give different voltages, but the output is not stable and the power supply unit
has to derive the necessary voltages from this DC voltage.
 Voltage regulators are used for this purpose.
 The input to a voltage regulator is a range of DC voltages and the output is a stable fixed
voltage.

Hardware Architecture of Embedded System

 Power Supply Unit
66

 DC-DC converters convert an unregulated voltage to a constant DC voltage.

 There are two types of DC-DC converters used in embedded systems.
 Linear regulators
 Switching regulators
 In linear regulators, the output voltage is less than the input voltage. They need less number of
components, hence these regulators cost less and give low noise. But they are less efficient and
waste more power. The IC LM78xx series are examples of linear regulators.
 Switching regulators step-up or step-down the input voltage level, or invert the voltage level.
For instance, switching regulator can produce 5 volt DC by taking 3.6volt input from a battery.
They are more efficient as they waste less power during conversion, but more components are
required and hence these regulators are more noisy, occupy more space, and costly. LM78xx
series, Maxim's MAX 603, 604, 1615, 724 are examples.

Hardware Architecture of Embedded System

 Power Supply Unit
67

 For designing the PSU of an embedded system, the power supply requirement for different
components has to be identified and the total current rating has to be estimated.
 Note that some devices, particularly the processors, take more power during startup.
 Flash devices draw high current during write operations.
 These considerations need to be kept in mind while working out the power supply requirements.
Some important steps in this direction are:
 use low power devices
 Processors and peripherals such as UART, memory devices to be out into low power mode
when they are not in use.
 3. If the hardware contains lot of ICs such as gates, flip flops etc , the component count can
be reduced using the PLDs or FPGA.

Hardware Architecture of Embedded System

 References
1. Marilyn Wolf, “Computers as Components - Principles of Embedded Computing System Design”, 3rd Edition, Morgan
Kaufmann Publisher (An imprint from Elsevier), 2012.
2. K.V.K.K.Prasad “Embedded /Real-Time Systems: Concepts, Design and Programming”, Dream tech, Wiley 2012.
3. Introduction To Embedded System Design, NPTEL, IIT Delhi.
4. https://embeddedhash.in/