1. Write down importance’s of IC technology?

ICs are used in computers for microprocessor, memory, and interface chips.
ICs are also used in computer networking, switching systems, communication
systems, cars, airplanes, even microwave ovens.
ICs are now even used in toys, hearing aids and implants for human body

2. List down all the VLSI design cycle and briefly explain each of them?
VLSI Design Cycle
1.System Specification: a high level representation of the system.
The factors to be considered in this process include:
 •performance,
 •functionality,
 •physical dimensions (size of the die (chip))
 •the fabrication technology
 •design techniques
 •market requirements

2.Architectural Design: includes, such decisions as

 •RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction
Set Computer),
 •number of ALUs,
 •Floating Point units
 •number and structure of pipelines,
 •size of caches among others.
3.Behavioral or Functional Design: identifies
 •the main function of the system
 •the interconnect requirements between the units
 •area, power, and other parameters each unit are estimated.
4.Logic Design:
 •the control flow,
 •word widths,
 •register allocation,
 •arithmetic operations,
 •logic operations of the design that represent the functional design are
derived and tested.
5.Circuit Design:
The purpose of circuit design is to develop a circuit representation based on the
logic design. The Boolean expressions are converted into a circuit representation
by taking into consideration the speed and power requirements of the original
design.
6.Physical Design:
this step the circuit representation (or netlist) is converted into a geometric
representation. this geometric representation of a circuit is called a layout. Layout
is created by converting each logic component (cells, macros, gates, transistors)
into a geometric representation (specific shapes in multiple layers), which
perform the intended logic function of the corresponding component.
7.Fabrication:
Layout data is converted (or fractured) into photo-lithographic masks, one for
each layer. Masks identify spaces on the wafer, where certain materials need to
be deposited, diffused or even removed. Silicon crystals are grown and sliced to
produce wafers.
8.Packaging, Testing and Debugging:
Finally, the wafer is fabricated and diced into individual chips in a fabrication
facility. Each chip is then packaged and tested to ensure that it meets all the
design specifications and that it functions properly.
3. List down all the physical design cycle and explain each of them?
Physical Design Cycle
1.Partitioning:
A chip may contain several million transistors. Due to the limitations of memory
space and computation power available it may not be possible to layout the
entire chip (or generically speaking any large circuit) in the same step. Therefore,
the chip (circuit) is normally partitioned into sub-chips (sub-circuits). These sub-
partitions are called blocks.

2.Floor planning and Placement:

This step is concerned with selecting good layout alternatives for each block, as
well as the entire chip. The area of each block can be estimated after partitioning
and is based approximately on the number and the type of components in that
block.

3.Routing:
The goal of a router is to complete all circuit connections using the shortest
possible wire length and using only the channel and switch boxes.

4.Compaction:
Compaction is simply the task of compressing the layout in all directions such that
the total area is reduced. By making the chip smaller, wire lengths are reduced,
which in turn reduces the signal delay between components of the circuit. At the
same time, a smaller area may imply more chips can be produced on a wafer,
which in turn reduces the cost of manufacturing.

5.Extraction and Verification:

Design Rule Checking (DRC) is a process which verifies that all geometric patterns
meet the design rules imposed by the fabrication process. After checking the
layout for design rule violations and removing the design rule violations, the
functionality of the layout is verified by Circuit Extraction.
4. Briefly explain the two techniques of doping?
This process of substituting other atoms for some of the semiconductor
atoms is called doping.
Diffusion
Dopant atoms are introduced from the gas phase of using doped oxide sources.
Doping concentration decreases monotonically from the surface. Indepth
distribution of the dopant is determined mainly by the temperature and diffusion
time. Used to form a deep junction.

Ion implantation
A low temperature process. Ions of one elements are accelerated into a solid
target, thereby changing the physical, chemical or electrical properties of the
target.

5. List down all the three FPGA programming techniques? Write

down their advantages and disadvantages?
FPGA Programming Technologies
 Static RAM cells-Flip flops of static RAM
 Anti-fuse –Burnable Joints
 EPROM (Erasable Programmable Read Only Memory),EEPROM(Electrically
Erasable Programmable Read Only Memory) and Flash ROM elements
commanded by floating gate
6. Give concrete examples of full custom, semi-custom and
programmable ASIC?

Full custom ASIC

A Full custom ASIC is one which includes some (possibly all) logic cells that are
customized and all mask layers that are customized.
A microprocessor is an example of a full-custom IC. Designers spend many hours
squeezing the most out of every last square micron of microprocessor chip space
by hand.
The manufacturing lead time (the time required just to make an IC not including
design time) is typically eight weeks for a full-custom IC.
These specialized full-custom ICs are often intended for a specific application so;
we might call some of them as full custom ASICs.
In a full-custom ASIC an engineer designs some or all of the logic cells, circuits, or
layout specifically for one ASIC. This means the designer avoids using pretested
and pre characterized cells for all or part of that design.

Semi-custom ASICs
ASICs, for which all of the logic cells are predesigned and some (possibly all) of the
mask layers are customized are called semi-custom ASICs.
Using the predesigned cells from a cell library makes the design, much easier.
There are two types of semicustom ASICs
(i)Standard-cell–based ASICs (ii)Gate-array–based ASICs.
Standard-Cell Based ASICs
A cell-based ASIC (cell-based IC, or CBIC pronounced sea-bick) uses predesigned
logic cells (AND gates, OR gates, multiplexers, and flip-flops, for example) known
as standard cells.
Gate-Array Based ASICs
In a gate array (sometimes abbreviated GA) or gate-array based ASIC the
transistors are predefined on the silicon wafer.
The predefined pattern of transistors on a gate array is the base array , and the
smallest element that is replicated to make the base array is the base cell
(sometimes called a primitive cell )

7. . Briefly explain the six masking process in CMOS fabrication? With

figures? (3 marks )
8. Briefly explain the three steps in logic synthesis? With concrete
examples?
Main steps: RT level synthesis, Logic synthesis , Technology mapping
RT level synthesis : In RTL design, a circuit is described as a set of registers and a
set of transfer functions describing the flow of data between the registers. The
registers are implemented directly as flip-flops, whilst the transfer functions are
implemented as blocks of combinational logic.
 Realize VHDL code using RT-level components
 Somewhat like the derivation of the conceptual diagram
 Limited optimization
 Generated netlist includes :
 “regular” logic: e.g., adder, comparator
 “random” logic: e.g., truth table description
Module generator

 “regular” logic can be replaced by predesigned module

 Pre-designed module is more efficient
 Module can be generated in different levels of detail
 Reduce the processing time
Logic Synthesis
 Realize the circuit with the optimal number of “generic” gate level
components
 Process the “random” logic
 Two categories:
 Two-level synthesis: sum-of-product format
 Multi-level synthesis
Technology mapping
 Map “generic” gates to “device-dependent” logic cells
 The technology library is provided by the vendors who manufactured
(in FPGA) or will manufacture (in ASIC) the

device

9. Compare full custom, standard cell, gate array, FPGA based on

a. Cell type
b. cell size
c. Cell placement. Interconnection
d. Design cost
e. Area
f. Performance
10. Compare different IC technologies such as BJT, MOS and CMOS in
terms of?
a. Power consumption
b. Speed
c. Size
d. Cost
11. Briefly explain the following? Give concrete examples?(8 marks)
A. PLD
B. FPGA

Programmable Logic Devices

Programmable logic devices ( PLDs ) are standard ICs that are available in
standard configurations.
Features of PLDs
 No customized mask layers or logic cells
 Fast design turnaround
 A single large block of programmable interconnect
 A matrix of logic macro cells that usually consist of programmable array
logic followed by a flip-flop or latch
The simplest type of programmable IC is a read-only memory( ROM ). The most
common types of ROM use a metal fuse that can be blown permanently (a
programmable ROM or PROM ).

Field-Programmable Gate Arrays(FPGAs

An FPGA is usually just larger and more complex than a PLD. In fact, some vendors
that manufacture programmable ASICs call their products as FPGAs and some call
them as complex PLDs .
Characteristics of an FPGA
 None of the mask layers are customized.
 There is a method for programming the basic logic cells and the
interconnect.
  The core is a regular array of programmable basic logic cells that can
implement combinational as well as sequential logic (flip-flops).
 A matrix of programmable interconnect surrounds the basic logic cells.
 Programmable I/O cells surround the core.
 Design turnaround is a few hours.

12. Compare CPLD and FPGA based on:

A. Architecture
B. Speed
C. Density
D. Interconnection
13. Briefly explain the following terms
A. Photolithography
B. Etching
C. Epitaxy
D. Lithography
Lithography: lithography is the process delineating the patterns on the wafers to
fabricate the circuit elements and provide for component interconnections.
Because the polymeric materials resist the etching process they are called resists
and, since light is used to expose the IC pattern, they are called photoresists. The
wafer is first spin-coated with a photoresist.
Etching: Etching is the process of transferring patterns by selectively removing
unmasked portions of a layer. Dry etching techniques have become the method of
choice because of their superior ability to control critical dimensions reproducibly.
Wet etching techniques are generally not suitable since the etching is isotropic

Epitaxy: This is the process of depositing a thin single-crystal layer on the surface
of a single-crystal substrate. The word epitaxy is derived from two Greek words:
epi, meaning ‘upon’, and taxis, meaning ‘ordered’. Epitaxy is a Chemical Vapor
Deposition (CVD) process in which a batch of wafers is placed in a heated
chamber. At high temperatures (900°to 1250°C), deposition takes place when
process gases react at the wafer surface.
Photolithography since exposure of the photoresist occurred while using the
mask, the pattern of exposed parts on the wafer is exactly the same as in the
mask. This process of transferring a pattern from a mask onto a wafer is called
photolithography
14. F = ((AB +BA)C + AC)D +CD draw F in CMOS technology?
15.
16.