EEE 335 Laboratory 2

Assignment Description
Spring 2021

General Rules
§ All reports need to be saved as PDF format.
§ Use Report Submission Template to write out your lab report.
§ In order to get full credit, you must add material indicated after the INCLUCE
prompt under the tasks below.
§ If you directly import cadence plots into your presentation, they must have
clearly visible axes, white background or CLEARLY labeled on black
background, and solid easily viewable traces.
§ All schematics must be clearly annotated!
§ All hand analysis may be scanned and pasted into the corresponding space(s).
§ Please ensure that your hand analysis follows the same naming scheme as your
circuits/simulations.
§ Please clearly mark all simulation axes (or title the simulation plots) (I do not
know what V/net5 is!).

Lab Documents
This is the ‘Assignment Description’, it includes a brief overview of the lab as
well as descriptions of all task’s students will have to take in order to complete this
lab. For further information on how to complete these tasks reference the ‘Lab
Walkthrough’ PowerPoint.

As the tasks are completed fill out the ‘Report Submission Template’ document.
All graph titles that are required will already be populated; you need only add your
results above them and your name to the upper right-hand corner. Once all blanks are
filled, save the document as a pdf with the title being in the format
“LastName_FirstName_Lab2.pdf”.

Description
In this lab students will be creating and testing a CMOS inverter in Cadence.
Students will be running DC and Transient analyses on the circuit and compare the
results to their own hand calculations. During these steps’ students will look at gate to
source voltages, drain to source voltages, drain currents, propagation delays and noise
margins. Students will then create a plot of the voltage transfer characteristic. Lastly
students will run a Parametric analysis of length and width of the NMOS and PMOS
and look at the changes to the Vin, Vout and VTC.

This lab consists of the following ten tasks:

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Task 1. Inverter DC Hand Analysis (1)
§ Hand-calculate the values of Vgs (Vsg), Vds (Vsd), & id for both NMOS and
PMOS of your inverter when the input voltage is VIN = 0V, 2.5V and 0.75V
§ The following values may be used in your hand analysis:

§ INCLUDE: Scan 1. DC Hand Calculations of Vgs (Vsg), Vds (Vsd), & id for NMOS
and PMOS.

Task 2. Inverter DC simulation (2)

§ Follow slide 7 of the Lab Walkthrough and make a DC simulation on the CMOS
inverter you have built.
§ INCLUDE: Fig. 1. DC annotated schematic (result screen-shot) as shown on slide
8 in EEE 335 Laboratory 2 Walkthrough.

Task 3. DC Conclusion and Comparison (2)

§ On the Report Submission Template compare your results from the hand
calculations and simulations.
§ INCLUDE: Table I. Compare Hand Calcs & Simulation: Vgs, Vds, & id.
§ INCLUDE: A brief conclusion about your DC simulation.

Task 4. Inverter Transient Hand Analysis (4)

§ Complete hand analysis and determine the rise time (tr) & fall time (tf),
propagation delay Low->High (tPLH), High->Low (tPHL), average propagation
delay (tP), VOL, VIL, VIH, VOH, and noise margins NML, NMH of the inverter.
§ Both equations and results must be included. SHOW YOUR WORK.
§ These are some parameters you can use in the calculation:

§ INCLUDE: Scan 2. Transient Hand Calculations of tr, tf, tPLH, tPHL, tP, VOL, VIL,
VIH, VOH, NML, and NMH.

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Task 5. Inverter Transient Simulation tPLH, tPHL, rise and fall time (4)
§ Follow slide 9 of the Lab Walkthrough and make a transient simulation on the
CMOS inverter you have built.
§ INCLUDE: Screenshot with the transient analysis plot, with rise/fall time, and
propagation delays (tPLH, tPHL) clearly marked as shown on slides 16 & 17.
• Two plots:
- Fig. 2. Rise Time and Fall Time
- Fig 3. Propagation Delay Low to High and High to Low

Task 6. Inverter Transient Simulation Parametric Analysis (2)

§ Follow slides 18, 19 & 20 of the Lab Walkthrough and make a parametric
analysis simulation on the CMOS inverter you have built.
§ INCLUDE: Fig. 4. Timing for a Sweep of Capacitance from 500fF to 1500fF
§ INCLUDE: Answer to the following question.
• What value of capacitance has better rise and fall times and better
propagation delay? Why is this true?

Task 7. Inverter DC Transfer Characteristics (2)

§ Follow slides 23, 24 & 25 of the Lab Walkthrough and make a DC transfer
characteristics analysis simulation on the CMOS inverter you have built.
§ INCLUDE: Fig. 5. Voltage Transfer Characteristic and mark the NML and NMH.

Task 8. Transient Conclusion and Comparison (2)

§ INCLUDE: Table II. Compare Hand Calcs & Simulation: tPHL, tPLH, trise, tfall, NML, &
NMH
§ INCLUDE: A brief conclusion about your Transient simulation.

Task 9. Inverter Transient Simulation Parametric Analysis-Length (2)

§ Do the transient simulation and sweep the length of NMOS from 300nm to
700nm with 5 steps and keep L_pmos=300nm.
§ Do the transient simulation and sweep the length of PMOS from 300nm to
700nm with 5 steps and keep L_nmos=300nm.
§ INCLUDE: Screenshots for the parametric analysis on length of PMOS and
NMOS.
• Two plots
- Fig. 6. Vin & Vout for a Sweep of NMOS Length from 300nm to 700nm
- Fig. 7. Vin & Vout for a Sweep of PMOS Length from 300nm to 700nm

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Task 10. Inverter DC Transfer Characteristics Parametric Analysis-Length (4)
§ Do the DC Transfer Characteristics simulation and sweep the length of NMOS
from 300nm to 600nm with 2 steps and keep L_pmos=300nm,
W_pmos=1.35um, W_nmos=450nm.
§ Do the DC Transfer Characteristics simulation and sweep the length of PMOS
from 300nm to 600nm with 2 steps and keep L_nmos=300nm,
W_pmos=1.35um, W_nmos=450nm.
§ Do the DC Transfer Characteristics simulation and sweep the width of PMOS
from 1.35um to 2.7um with 2 steps and keep L_nmos=300nm, L_pmos=300nm,
W_nmos=450nm.
§ Do the DC Transfer Characteristics simulation and sweep the width of NMOS
from 450nm to 900nm with 2 steps and keep L_nmos=300nm, L_pmos=300nm,
W_pmos=1.35um.
§ INCLUDE: Screenshots for DC Transfer Characteristics Parametric Analysis,
• Four plots.
- Fig. 8. VTC for a Sweep of NMOS Length from 300nm to 600nm
- Fig. 9. VTC for a Sweep of PMOS Length from 300nm to 600nm
- Fig. 10. VTC for a Sweep of PMOS Width from 1.35um to 2.7um
- Fig. 11. VTC for a Sweep of NMOS Width from 450nm to 900nm

§ INCLUDE: Table III. Compare Varying Lengths and Widths: VIL, VIH, NML, & NMH
§ INCLUDE: A brief conclusion about your Parametric sweep.