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CCEE221L Lab Report Template 5

The lab report focuses on FPGA VHDL programming, specifically implementing a Full Adder circuit using Verilog HDL in Quartus Prime software. The experiment aims to understand the functionality of Full Adders and how to program them on an FPGA, detailing the necessary steps and code required for implementation. The report includes sections on the introduction, lab equipment, experiment theory, and concludes with an overview of the experiment's objectives and outcomes.

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2 views

CCEE221L Lab Report Template 5

The lab report focuses on FPGA VHDL programming, specifically implementing a Full Adder circuit using Verilog HDL in Quartus Prime software. The experiment aims to understand the functionality of Full Adders and how to program them on an FPGA, detailing the necessary steps and code required for implementation. The report includes sections on the introduction, lab equipment, experiment theory, and concludes with an overview of the experiment's objectives and outcomes.

Uploaded by

zakazikoziko35
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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College of Engineering

Electrical and Computer Engineering Department


CCEE 221L – Logic Lab Design
Spring 2024

Experiment [1]:
[FPGA VHDL Programming]

Lab Report Submitted by:


[Khaled Qasem] – [20230489] – [Introduction, lab equipment, experiment theory]
[Student 2 NAME] – [Student 2 ID] – [Distribution Load]

Lab Report Submitted to:


[Milana Kassab]

[Monday, 3 March 2025]


CCEE 221 – Logic Design Lab

[Adder and Subtractor]

Section 1: Introduction
The goal of this experiment is to understand FPGA (Field Programmable Gate Array) and learn
how to write code in Verilog HDL using Quartus Prime software. Verilog is a programming
language used to design digital circuits, and it is built into the Quartus II system. You can create
Verilog Design Files (.v) using the Quartus II Text Editor or any other text editor. In this
experiment, the circuit consists of two Full Adders.
A Full Adder is an important part of digital circuits used for addition and subtraction. It takes
three inputs—A, B, and a carry-in (C-IN)—and gives two outputs: the sum (S) and the carry-out
(C-OUT). Full Adders can be connected together to add multiple bits, allowing for larger
calculations like adding a full byte.

Figure 2: Full Adder Table 1: Full Adder Truth Table

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CCEE 221 – Logic Design Lab

Section 2: Lab Equipment


In this experiment we will use the Field Programmable Gate Array (FPGA) (fig1) . Below is a
general description about it and its uses .
A Field Programmable Gate Array (FPGA) is a special type of computer chip that can be
programmed to perform different tasks. It consists of small building blocks called logic blocks,
which can be connected in various ways to create custom circuits. Unlike regular chips that have
a fixed design, an FPGA can be reprogrammed as needed.
FPGAs are often used to test and develop new processors or special-purpose chips before they
are made permanent. They can handle simple tasks, like basic logic operations (AND, OR), or
complex tasks, like running a multi-core processor. FPGAs are used in many industries,
including computers, cameras, cars, airplanes, and military systems. Their power and voltage
levels depend on how they are used, usually ranging from 1.2V to 3.3V.

Figure 2: FPGA

Section 3: Experiment Theory

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CCEE 221 – Logic Design Lab

To implement a Full Adder in Quartus Prime using Verilog, a new project and a Verilog HDL
file need to be created. The Verilog file should contain the necessary code to define the Full
Adder circuit.
In the Full Adder, a module is created with three inputs (A, B, C) and two outputs (Cout, S). The
inputs represent binary values (0 or 1) that are manually entered using a switch on the FPGA.
The output s gives the sum of the inputs, while the carry output Cout is passed as the carry-in for
the next adder in a multi-bit addition setup.
We write the following code on verilog :
module addsub (input A, B, input C, output S, Cout);
assign S=A^B^C;
assign Cout=A*C|A*B|B*C;
end module
When done for the module, the symbol should be created by the following steps :
file>create update>create symbol file for current file
named as the name of the module
Note: The symbol name must be exactly the same as the module name and should be different
from the block and project names.
Now that the blocks are ready, they can be added to the block diagram by going to "Inputs" →
"Project" → selecting the created blocks.
 The first input a0 is connected to a.
 Inputs b0 and s pass through an XOR gate before connecting to b.
 The output s is also connected to another XOR gate along with input b1, which then
connects to b in the second Full Adder.
 The output s is linked to an output called sum0.
 The carry output co from the first Full Adder is connected to the carry-in (cin) of the
second Full Adder.
 In the second Full Adder, input a1 connects to a, while the outputs s and co represent the
sum and final carry output.
This setup allows numbers to be added using switches on the FPGA, as shown in Figure 3.

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CCEE 221 – Logic Design Lab

Figure 3: Fullstep
The next AdderisCircuit
to assign
each pin to its pin name by clicking on “pin planner” and getting each
pin location from the DE10 data sheet as shown in figure 4 .

Figure 4: Pin Planner Panel

The program is then compiled and the remaining steps in appendix A are completed. After
completing all steps, the circuit will be uploaded on the FBGA board and ready to compile.

Section 5: Experiment Implementation

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CCEE 221 – Logic Design Lab

[IF IT WAS DONE INSIDE THE LAB Show the implemented circuit on the breadboard and
specify the input/output values, with a detailed experimental discussion based on your outputs.]
All figures/tables/diagrams if present must be very clear labeled and captioned

Section 6: Conclusion
[A brief conclusion of 4 to 5 lines.]

Section 7: References
[No references]

Page 6 of 6

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