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Parallel Processing Challenges

The document discusses the challenges of parallel processing, emphasizing the difficulty in writing efficient software for multiple processors. It outlines Flynn's classification of processor organization, including SISD, SIMD, MISD, and MIMD, detailing their characteristics and examples. Additionally, it highlights the advantages of SIMD, particularly in handling data-level parallelism and the use of vector architecture for improved performance.

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Rene Dev
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8 views4 pages

Parallel Processing Challenges

The document discusses the challenges of parallel processing, emphasizing the difficulty in writing efficient software for multiple processors. It outlines Flynn's classification of processor organization, including SISD, SIMD, MISD, and MIMD, detailing their characteristics and examples. Additionally, it highlights the advantages of SIMD, particularly in handling data-level parallelism and the use of vector architecture for improved performance.

Uploaded by

Rene Dev
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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PARALLEL PROCESSING CHALLENGES:

 It is difficult to write software that uses multiple processors to complete one task
is faster.
 Parallel processing will increase the performance of processor and it will reduce
the utilization time to execute a task.
 By obtaining the parallel processing is not an easy task.
 The difficulty is not in hardware side it is in software side.
We can understand that it is difficult to write parallel processing programs that are
fast, especially as the number of processor increases.

PROCESSOR ORGANAIZATION [FLYNN’S CLASSIFICATION]


SISD
 Single Instruction stream, Single Data stream.
 Example of SISD is uniprocessor.
 It has a single control unit and producing a single stream of instruction.
 It has one processing unit and the processing has more than one functional unit
these are under the supervision of one control unit.
 It has one memory unit

SIMD
 It has one instruction and multiple data stream.
 It has a single control unit and producing a single stream of instruction and multi
stream of data.
 It has more than one processing unit and each processing unit has its own
associative data memory unit.
 In this organization, multiple processing elements work under the control of a
single control unit.
 A single machine instruction controls the simultaneous execution of a number of
processing element.
 Each instruction to be executed on different sets of data by different processor.
 The same instruction is applied to many data streams, as in a vector processor.
 All the processing elements of this organization receive the same instruction
broadcast from the CU.
 Main memory can also be divided into modules for generating multiple data
streams acting as a distributed memory as shown in figure.
 Therefore, all the processing elements simultaneously execute the same
instruction and are said to be 'lock-stepped' together.
 Each processor takes the data from its own memory and hence it has on distinct
data streams.
 Every processor must be allowed to complete its instruction before the next
instruction is taken for execution. Thus, the execution of instructions is
synchronous.
 Example of SIMD is Vector Processor and Array Processor.

Advantage of SIMD:
 The original motivation behind SIMD was to amortize the cost of the control unit
over dozens of execution units.
 Another advantage is the reduced instruction bandwidth and space.
 SIMD needs only one copy of the code that is being simultaneously executed
while message-passing MIMDs may need a copy in every processor, and shared
memory MIMD will need multiple instruction caches.
 SIMD works best when dealing with arrays in for loops because parallelism
achieved by performing the same operation on independent data.
 SIMD is at its weakest in case or switch statements, where each execution unit
must perform a different operation on its data, depending on what data it has.
Execution units with the wrong data must be disabled so that units with proper
data may continue.

MISD
 Multiple Instruction and Single Data stream (MISD)
 In this organization, multiple processing elements are organized under the
control of multiple control units.
 Each control unit is handling one instruction stream and processed through its
corresponding processing element.
 But each processing element is processing only a single data stream at a time.
 Therefore, for handling multiple instruction streams and single data stream,
multiple control units and multiple processing elements are organized in this
classification.
 All processing elements are interacting with the common shared memory for the
organization of single data stream as shown in figure.  The only known example
of a computer capable of MISD operation is the C.mmp built by Carnegie-Mellon
University.
MIMD
 Multiple Instruction streams and Multiple Data streams (MIMD). In this
organization, multiple processing elements and multiple control units are
organized.
 Compared to MISD the difference is that now in this organization multiple
instruction streams operate on multiple data streams.
 Therefore, for handling multiple instruction streams, multiple control units and
multiple processing elements are organized such that multiple processing
elements are handling multiple data streams from the main memory as shown in
figure.
 The processors work on their own data with their own instructions. Tasks
executed by different processors can start or finish at different times.
 They are not lock-stepped, as in SIMD computers, but run asynchronously.
 This classification actually recognizes the parallel computer. That means in the
real sense MIMD organization is said to be a Parallel computer.

SIMD-VECTOR ARCHITECTURE [SPMD] (Single Program Multiple data)


 SIMD is called vector architecture.
 It is also a great match to problems with lots of data-level parallelism.i.e.
Parallelism achieved by performing the same operation on independent data.
 Rather than having 64 ALUs perform 64 additions simultaneously, like the old
array processors.
 The vector architectures pipelined the ALU to get good performance at lower
cost.
 The basic idea of vector architecture is to collect data elements from memory,
put them in order into a large set of registers, operate on them sequentially in
registers using pipelined execution units, and then write the results back to
memory.
 A key feature of vector architectures is then a set of vector registers. Thus,
vector architecture might have 32 vector registers, each with 64-bit elements.

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