International Conference on Emerging Research in Electronics, Computer Science and Technology – 2015

Design and Analysis of Dual Input SEPIC

Converter for Renewable Energy Sources

Danamma M Sangalad Hemalatha J N Dr. Hariprasad. S.A Dr.Anitha. G.S

M.Tech Dept. of EE Asst. Prof Dept. of EEE Prof. Dept. of EEE Asso. Prof Dept. of EEE
R.V.C.E R.V.C.E D. S. I.T R.V.C.E
Bengaluru, India Bengaluru, India Bengaluru, India Bengaluru, India
[email protected]

I. INTRODUCTION each switch is derived from common switching

frequency [10].
In a power electronic interface there will be
mismatch between input power and output demand at
any instant of time. Therefore there is need to II. PROPOSED SYSTEM
effectively interconnect them by matching their
characteristics. Multiple-input system employing The dual input SEPIC converter circuit is as shown in
such an interface will further increase its complexity. Fig. 1. Let us assume that circuit operates in
The traditional way of connecting multiple energy continuous conduction mode (CCM), Vin1>Vin2 and
sources was done in series or through parallel switching period of switch S1 is smaller than switch
connection. All the sources need to conduct same S2. Switching signals for S1 and S2 are as shown in
current when they are connected in series which is Fig. 3 where Gi(t) is one when Si is ON ,Gi (t) is zero
not always met. Furthermore, if they have different when Si is OFF for i=1,2 and G2eff (t) or D2eff is one
voltage levels, they cannot be connected in parallel only when G2 (t) is one and G1 (t) is zero. There are
[1]. A solution to harvest power from multiple three operational states in circuit during continuous
sources of different characteristics is a multiple input conduction mode. The equivalent diagram
power electronic converter integrated into a single representing the operation of circuit under these 3
system [2]. states is shown in Fig. 2(a), 2(b), 2(c).

Recently many multiple input converter (MIC)

topologies that act as an interface between renewable
energy module and load have been proposed in
literature [3-5]. Every type has its own advantages
and disadvantages. The MI DC-DC converters such
as Buck and Boost converters provide a limited range
of output voltages as they only step-down and step-
up voltages respectively. The Buck-Boost and Cuk
converter topologies provide a wider range of output
voltages but with an inverted polarity [6-7]. The
MISEPIC has the advantage of increasing life time of Fig. 1 Dual input SEPIC Converter
sources because of its current-source interface [8].
This topology is capable of generating high voltage
level to feed the 240V H-bridge inverter from a low A. State 1 (0 < t < D1T)
voltage input. In this paper, a 2ISEPIC with time Equivalent circuit of converter in this state is as
sharing switching strategy is implemented. The idea shown in Fig. 2 (a). In this state both the switches S1
behind this scheme is that the effective duty ratio of and S2 are ON. Though both the switches are ON,

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International Conference on Emerging Research in Electronics, Computer Science and Technology – 2015

switch S2 does not conduct because it is reverse

biased as shown in Fig.2. The switch S2 is reverse
biased because Vc1 is higher compared to Vc2 where
Vc1 and Vc2 are voltage on blocking capacitors C1 and
C2 respectively. Inductors L1 and L2 are energized
from input sources Vin1 and Vin2 respectively. Free-
wheeling diode D is reverse biased thus it does not
conduct any current through it.

Fig. 2(c) Equivalent converter circuit in state 3

Fig. 2(a) Equivalent converter circuit in state 1

B. State 2 (D1T< t < D2T)

Equivalent circuit of converter in this state is as
shown in Fig. 2 (b). During this interval switch S1 is
turned OFF while S2 remains ON. Current through L1
and L2 are increasing and free-wheeling diode D is
still reverse biased thereby not conducting any
current through it.

Fig. 3 Current and voltage waveforms for each state of operation of

converter

Inductor current in L1 in different time interval

is expressed as
݅௅ଵ ሺ‫ݐ‬ሻ ൌ
V1
Fig. 2(b) Equivalent converter circuit in state 2 ‫ۓ‬ iL1min + t 0<t<D1 T
L1
ۖ
V1 D1 T ሺV1 -VC1 +VC2 ሻሺt-D1 Tሻ
C. State 3 (D2T< t < T) iL1min + +  D1 T<t<D2 T(1)
Equivalent circuit of converter in this state is as ‫۔‬ L1 L1
shown in Fig. 2 (c). During this interval switch S2 is ۖ V1 -VC1 -V0
൰ ሺt-Tሻ
iL1min + ൬ D2 T<t<T
turned OFF. Thus gate pulse for both Switches are ‫ە‬ L1
absent in this interval. Free-wheeling diode D is 
forward biased. The energized inductors L1 and L2 By taking integral form of the switching dynamic
drive the load. These energized inductors L1 and L2 equations with variable functions, we can derive the
are discharged through the free-wheeling diode D. equations for equilibruim point. Change in the state
variables over a switching period is zero in steady
state operation.
The average value various variables in the SEPIC
converter are expressed as in equations:


International Conference on Emerging Research in Electronics, Computer Science and Technology – 2015

(D1 V0 ) D1 Deff V2 T(L1 L2 +L2 L0 +L0 L1 ) The input inductance is given by

iL1 = -  (2)
(1-D2 )R 2L1 L2 L0
ͳ ͳ
(Deff V0 ) D1 Deff V1 T(L1 L2 +L2 L0 +L0 L1 ) ͳ ൌ ሺͺሻ
iL2 = +  (3) ο ͳ ˆ
(1-D2 )R 2L1 L2 L0

୚బ Substituting respective values in above

a equation,
‹଴ ൌ (4)
ୖ
L1=19.24 mH
H
େଵ ൌ ଵ  (5) Similarly,

େଶ ൌ ଶ ሺ͸ሻ L2 = 6 mH

V1 D1 +V2 Deff The input capacitance is given by

y
V0 =  (7)
(1-D2 )
‘ ͳ
ͳ ൌ ሺͻሻ
Where, οͲ ˆ
Deff = D2-D1
Substituting respective values in above
a equation,

III. DESIGN OF THE CONVE

ERTER C1 = 361.32 µF
Similarly,
The design of various components ppresent in the C2 = 434 µF
proposed converter topology is discuussed here. A
dual input SEPIC converter is a DC--DC converter
that generates output voltage either lesser or greater IV. D RESULTS
SIMULATION AND
than the input voltages. For the simulation of
converter circuit, various components tto be designed
are duty cycle of the switches, input inductors and A. Open Loop Simulation and ressults
capacitors and output LC filter. The paarameters used The open-loop circuit as shown in n Fig. 1 is simulated
for the simulation of open-loop duall input SEPIC for different duty cycles of the gating
g signals for the
converter are presented in Table I. MOSFETs and different com mbination of input
voltages. The behaviour of SEPIC S converter is
analyzed. Time sharing switcching technique is
employed to generate the gatin ng pulses for power
electronic switches used in thiss converter. In this
scheme the input-leg switches haveh duty ratios that
are integer multiples of the commmon duty ratio.
Table I Design specifications of SEPIC converter At 66.7% duty cycle with respeect to gate signal of
Sl. No. Parameters Value switch S1 in the circuit and at 78%
7 duty cycle with
1 Input voltage 1 24V respect to gate signal of switch S22 as shown in Fig. 4,
2 Input voltage 2 12V the desired output voltage of 48 8 V is attained. The
3 Duty cycle 1 66.7%
simulation result of converter chharacteristics at these
4 Duty cycle 2 78%
5 Switching frequency 4 k Hz duty cycles is shown in the Fig. 5. Output voltage and
6 Output voltage 48 V current are as shown Fig. 6 and Fig. 7.
7 Load 100 watts
8 Efficiency •85

D1 and D2 are calculated from Output voltage given

by equation (7).
D1 is calculated by keeping V2=0 V iin equation (7)
and similarly D2 is calculated by keepinng V1=0 V

D1 = 66.7%

D2 = 78%


International Conference on Emerging Research in Electronics, Computer Science and Technology – 2015

Fig.4 Duty Cycle of Switching signals for swiitches S1 and S2

respectively

Fig. 7 Output current io at V1=24 V, V2=12 V, D1= 66.7% and

D2=78%

Fig. 5 Converter Characteristics at V1= 24 V, V2= 12 V, D1=66.7%

and D2=78%.

In the Dual input SEPIC converter ooutput voltage

ripple is found to be 1V (2% of outpput voltage) as
shown in Fig. 6

Fig.8 Converter Characteristics at V1= 24

4 V, V2= 8 V, D1=66.5%
and D2=82.7%.

The ripple in the inductor curren

nt is found to be 0.3
A. Dual input SEPIC Converteer characteristics for
various combinations of input vooltages are tabulated
in table II.
Fig. 6 Output Voltage Vo at V1=24 V, V2=12 V
V, D1= 66.7% and Table II Converter characteristics for vaarious input combinations
D2=78%

Sl. Input Input D1 D2 iL1 iL2 Vo

No V1(V) V2(V) (%) (%) (A) (A) (V)

1 24 12 66.7 78 2.074 4.09 48

2 24 8 66.5 82.5 2.74 5.4 48
3 24 16 66.7 73.6 1.39 2.68 48
4 24 24 66.9 66.9 2.1 2.11 47.8
5 12 12 81 80.2 4.5 4.4 48.4

B. Closed loop Simulation and reesults

The closed loop converter circuitt is as shown in Fig.
11. The closed-loop dual input SEPIC converter is


International Conference on Emerging Research in Electronics, Computer Science and Technology – 2015

simulated using the PI controller results in achieving

regulated output voltage of 48 V. The PI controller
parameters are obtained by manual tuning using the
Ziegler – Nichols tuning method. The resultant PI
controller parameters are presented in Table III.

Table III Parameters of PI controller

Sl. No. Parameter Value
1 Proportional gain, Kp 2.025
2 Integrator gain, Ki 0.000025

Fig. 12 PI controller output waveform at V1= 24 V and

V2= 12 V

Fig. 9. Closed loop circuit of dual input SEPIC

Fig. 10 Sub system block for PI Controller.

Fig.13 Closed loop converter characteristics at V1= 30 V and
V2= 8 V

Fig. 11 Closed loop converter characteristics at V1= 24 V and Fig. 14 PI controller output waveform at V1= 30 V and
V2= 12 V V2= 8 V

The closed loop output voltage of dual input

converter is regulated in the range 47.5- 48.5 V due


International Conference on Emerging Research in Electronics, Computer Science and Technology – 2015

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