Computer Org anisation and

Architecture
C ours e C ode: C O206
Module-2: Control Unit

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Contents of Module 2
❑ Instruction types, Formats, Instruction cycles and sub cycles.
❑ Micro-operations, execution of a complete instruction.
❑ Hardwired and micro programmed control.
❑ Microprogrammed sequencing.
❑ Wide branch addressing.
❑ Micro- instructions with next address field.
❑ Pre-fetching micro instructions.
❑ Concept of horizontal and vertical micro-programming.
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I ntroduction
❑ Every different processor type has its own design (different registers, buses, micro-
operations, machine instructions, etc)
❑ Modern processor is a very complex device. It contains
Many registers
Multiple arithmetic units, for both integer and floating point calculations
The ability to pipeline several consecutive instructions to speed execution
❑ However, to understand how processors work, we will start with a simplified
processor model
❑ This is similar to what real processors were like ~25 years ago
❑ M. Morris Mano introduced a simple processor model he calls the Basic Computer
❑ The memory has 4096 =212 words in it (i.e. 12 bits to select a word in memory)
❑ Each word is 16 bits long.
❑ We will use this to introduce processor organization and the relationship of the RTL
model to the higher level computer processor
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Instruction
❑ Program
▪ A sequence of (machine) instructions
❑ (Machine) Instruction
▪ A group of bits that tell the computer to perform a specific
operation (a sequence of micro-operation)
❑ The instructions of a program, along with any needed data are
stored in memory
❑ The CPU reads the next instruction from the memory
❑ It is placed in an Instruction Register (IR)
❑ Control circuitry in control unit then translates the instruction into
the sequence of micro-operations necessary to implement it.
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Instruction Types

❑ A computer has a set of instructions which can be classified as

➢ Data transfer Instructions
➢ Arithmetic Instructions
➢ Logical Instructions
➢ Shift and Rotate Instructions
➢ Program control Instructions
➢ Input/Output Instructions

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Data Transfer Instruction

Instruction Mnemonic Description

Load LDA It transfers data from specified location to
the processor register usually accumulator
Store STA It transfers data from the processor
register(usually accumulator) to the specified
memory location
Move MOV It transfers data between processor register
and memory or between two memory words
Exchange XCH It swaps data between two registers or a
register and a memory word

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Arithmetic Instruction

Instruction Mnemonic Description

Add ADD It adds the content of two operands
Subtract SUB It subtracts the contents of two operands
Increment INC It adds 1 to the value stored in the register or
a memory word
Decrement DEC It subtracts 1 from the value stored in the
register or a memory word
Multiply MUL It multiplies the content of two operands
Divide DIV It divides the content of two operands
Negate NEG It gives the 2’s Complement of the specified
operand
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Logical Instruction

Instruction Mnemonic Description

AND AND It logically ANDs the individual bits of the
operands
OR OR It logically ORs the individual bits of the
operands
Exclusive OR XOR It logically Ex-ORs the individual bits of the
operands
Clear CLR It causes the specified operand to be
replaced by 0s
Complement COM It gives the 1’s complement of the specified
operand
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Shift and Rotate Instruction

Instruction Mnemonic Description

Logical Shift Right SHR It shifts the contents of the specified register 1-bit
position towards right and fills the vacant bit with
zero
Logical Shift Left SHL It shifts the contents of the specified register 1-bit
position towards left and fills the vacant bit with zero
Arithmetic Shift Right ASHR It shifts the contents of the specified register 1-bit
position towards right and fills the vacant bit with
previous sign bit
Arithmetic Shift Left ASHL It shifts the contents of the specified register 1-bit
position towards left and fills the vacant bit with zero
Rotate Left ROL It rotates (circular shifts) left the contents of the
specified register
Rotate Right ROR It rotates (circular shifts) right the contents of the
specified register
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Program Control Instruction

Instruction Mnemonic Description

Branch BR It transfers program control to the specified
address
Jump JMP It transfers program control to the specified
address
Compare CMP It compares the content of two registers
Test TST It performs bitwise AND operation on two
operands
Skip SKP It skips the next instruction

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Input/Output Instruction

Instruction Mnemonic Description

Input INP Load a character in Accumulator register
from input port
Output OUT Send a character to output port from
Accumulator register
Skipping SKI It skips the next instruction if input flag=1
instruction
from input
Skipping SKO It skips the next instruction if output flag=1
instruction
from output

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Instruction Format
❑ A Computer instruction is often divided into two parts
❑ An opcode (Operation Code) that specifies the operation for that instruction
❑ An address that specifies the registers and/or locations in memory to use for that
operation
❑ In the Basic Computer, since the memory contains 4096 (= 212) words, we need 12 bit
to specify which memory address the instruction will use
❑ In the Basic Computer, bit 15 of the instruction specifies the addressing mode (0:
direct addressing, 1: indirect addressing)
❑ Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits
for the instruction’s opcode

Instruction Format
15 14 12 11 0
I Opcode Address

Addressing
mode
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Addressing Modes
The address field of an instruction can represent either
❑ Direct address: it has the address of the operand (direct access to operand)
❑ Indirect address: It is the address in memory from which the address of the operand can be fetched.
Direct addressing Indirect addressing
0 ADD 457 35 1 ADD 300
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300 1350

Operand
457
1350 Operand

+ +
AC AC

Effective Address (EA)

❑ The address, that can be directly used without modification to access an operand for a computation-
type instruction, or as the target address for a branch-type instruction 13
Basic Computer Registers
Registers in the Basic Computer

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Common Bus System

15
Common Bus System

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Common Bus System
❑ Three control lines, S2, S1, and S0 control which register the bus selects as its input

❑ Either one of the registers will have its load signal activated, or the memory will have its read signal
activated
❑ Will determine where the data from the bus gets loaded
❑ The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions
❑ When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on
the bus
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Basic Computer Instruction Format

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Basic Computer Instructions

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Control Unit of Basic Computer

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Timing Signal

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Instruction Cycle
❑ In Basic Computer, a machine instruction is executed in the following
cycle:
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction

❑ After an instruction is executed, the cycle starts again at step 1, for the
next instruction

❑ Note: Every different processor has its own (different) instruction cycle
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Elements of Instruction
❑Operation Code(OPCODE)
❑ Specifies the operation to be performed
❑ The operation is specified by a binary code, known as the operation code,
opcode do ADD, SUB,DIV,LOAD,.
❑Source Operand reference
❑The operation may involve one or more source operands, that is, operands
that are inputs for the operation
❑Result Operand reference
❑ The operation may produce a result
❑Next Instruction reference
❑This tells the processor where to fetch the next instruction after the
execution of this instruction is complete

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Instruction Cycle

Fetch

Decode

Execute

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Fetch Cycle
❑ The address of next instruction is fetched from the program counter
and stored in address register.

❑ AR PC
❑ IR M[AR], PC PC+1

❑ The instruction read from memory is then placed in the instruction

register.
❑ Program counter is incremented by 1.

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Decode Cycle
❑ In decode operation processor decode the instruction which
is fetched from memory

❑I IR(15), Decode IR(12-14) , AR IR(0-11)

❑ 0-11 bits in the instruction format are store in the address

register.
❑ 12-14 bits are decoded.

❑ 15 bit is I means direct or indirect address.

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Execute Cycle
❑ After decoding the instruction, the third timing signal is active.
❑ There are three types of instruction:-
➢ Memory Reference
➢ Register Reference
➢ I/O Reference

❑ If D=1 and IR(15)=0, that means the instruction is register reference.

❑ If D=1 and IR(15)=1, that means the instruction is I/O reference.

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Execute Cycle
❑ If D=0 and IR(15)=0, that means memory reference instruction is direct
address instruction.

❑ If D=0 and IR(15)=1, that means memory reference instruction is indirect

address instruction

❑ AR M[AR], AR holds the address part of the instruction

❑ After the instruction is executed, SC is cleared to 0 and control returns to
the fetch phase.

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Register Reference Instructions
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in b0 ~ b11 of IR
- Execution starts with timing signal T3

r = D7 I’ T3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11
r: SC <- 0 CLA: Clear Accumulator
CLA rB11: AC <- 0 CLE: Clear E
CLE rB10: E <- 0 CMA: Complement AC
CMA rB9: AC <- AC’
CME: Complement E
CME rB8: E <- E’
CIR rB7: AC <- shr AC, AC(15) <- E, E <- AC(0) CIR: Circulate right
CIL rB6: AC <- shl AC, AC(0) <- E, E <- AC(15) CIL: Circulate Left
INC rB5: AC <- AC + 1 INC: Increment AC
SPA rB4: if (AC(15) = 0) then (PC <- PC+1) SPA: Skip if positive
SNA rB3: if (AC(15) = 1) then (PC <- PC+1) SNA: Skip if negative
SZA rB2: if (AC = 0) then (PC <- PC+1) SZA: Skip if AC zero
SZE rB1: if (E = 0) then (PC <- PC+1) SZE: Skip if E zero
HLT rB0: S <- 0 (S is a start-stop flip-flop) HLT: Halt Computer
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Memory Reference Instructions
-The effective address of the instruction is in AR and is placed there during timing signal T2 when I = 0,
or during timing signal T3 when I = 1
- Memory cycle is assumed to be short enough to complete in a CPU cycle
- The execution of MR instruction starts with T4

Operation
Symbol Symbolic Description
Decoder
AND D0 AC <- AC ^ M[AR]
ADD D1 AC <- AC + M[AR], E <- Cout
LDA D2 AC <- M[AR]
STA D3 M[AR] <- AC
BUN D4 PC <- AR
BSA D5 M[AR] <- PC, PC <- AR + 1
ISZ D6 M[AR] <- M[AR] + 1, if M[AR] + 1 = 0 then PC <- PC+1

BUN: Branch Unconditionally

BSA: Branch and save return address
ISZ: Increment and Skip if Zero

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Input Output Instructions
D7IT3 = p => Input Output Instruction

IR(i) = Bi, i = 6, …, 11

p: SC <- 0 Clear SC
INP pB11: AC(0-7) <- INPR, FGI <- 0 Input char. to AC
OUT pB10: OUTR <- AC(0-7), FGO <- 0 Output char. from AC
SKI pB9: if(FGI = 1) then (PC <- PC + 1) Skip on input flag
SKO pB8: if(FGO = 1) then (PC <- PC + 1) Skip on output flag
ION pB7: IEN <- 1 Interrupt enable on
IOF pB6: IEN <- 0 Interrupt enable off

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Instruction Types(on the basis of addresses)
❑Stack type organization
❑0-Address instruction
❑Accumulator type organization
❑ 1-Address Instructions
❑General Register Organization
❑2-Address instructions
❑3-Address instructions

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Zero Address Instruction
❑ All addresses implicit, e.g. ADD
❑Uses a stack, e.g. POP A, POP B
X= (A+B)*(C+D)
PUSH A
PUSH B
ADD
PUSH C
PUSH D
ADD
MUL
POP X

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1- Address Instruction
One address instruction use an implied accumulator (AC) register for all data manipulation
now we see the same example
X= (A+B)*(C+D)
LOAD A
ADD B
STORE T
LOAD C
ADD D
MUL T
STORE X
All operation are done between the AC register and a memory operand
T is the address of a temporary memory location for storing intermediate result

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2- Address Instructions
One address is used as operand and result both.
Most common in commercial in computers . Each address field can specify either a
processes register or a memory word

X= (A+B)*(C+D)
MOV R1, A
ADD R1, B
MOV R2, C
ADD R2, D
MUL R1,R2
MOV X, R1
Reduces length of instruction
Requires some extra work , temporary storage
MOV instruction moves or transfers the operand to and from memory and processor
registers.
First symbol listed in an instruction is assumed to be both a source and destination . 35
3-Address Instructions
Computer with three address instructions formats can use each address field to specify
either a processor register or a memory operand .

X= (A+B)*(C+D)
ADD R1,A,B
ADD R2,C,D
MUL X,R1,R2

Needs very long words to hold everything

It is assumed that the computer has two processor registers R1 andR2
The advantage of three address format is that it results in short programs when
evaluating arithmetic expression .
The disadvantage is the binary coded instructions require too many bits to specify

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Instances for instructions

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Execution of Complete Instruction
❑ADD R1 (R3)
❑ Fetch the instruction from memory-IR
❑ Fetch the operand from memory
❑ Perform Addition operation
❑ Load the result into R1

STEP ACTION
1 PCout, MARin, Read, Select Constant 1, Add, Zin
2 Zout, PCin, Yin ,WMFC
3 MDRout, IRin
4 R3out, MARin, Read
5 R1out, Yin, WMFC
6 MDRout, select Y, Add, Zin
7 Zout, R1in, END

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Unconditional Branch

STEP ACTION
1 PCout, MARin, Read, Select Constant 1, Add, Zin
2 Zout, PCin, Yin ,WMFC
3 MDRout, IRin
4 Offset-field-of-IRout, Add, Zin
5 Zout, PCin, END

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Multiple Bus Organisation

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Generation of Control Signal

❑ To execute instructions, the processor must have some means of

generating the control signals needed in the proper sequence.

❑ Two categories:
❑ Hardwired Control
❑ Micro-programmed control
Hardwired system can operate at high speed but with little
flexibility

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Hardwired Control

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Hardwired Control

❑ The control unit uses fixed logic circuits to interpret instructions and
generate control signals for them
❑ The fixed logic circuits use contents of the control step counter,
contents of the instruction register, contents of conditional code
flag and the external input signals such as MFC and interrupts

requests to generate control signal.

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Hardwired Control Signal Example

• Zin = T1 + T6 • ADD + T4 • BR + …

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Micro-programmed Control

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Micro-programmed Control

❑ CONTROL MEMORY
❑ The micro routines for all the instructions in the instruction set of a
computer are stored in a special memory called the Control
Memory/Store
❑ CONTROL WORD
❑ It is a word whose individual bits represent the various control signals.
❑ MICRO-ROUTINE
❑ A sequence of control words corresponding to the control sequence of
a machine instruction constitutes the micro-routine for that instruction.
❑ MICRO-INSTRUCTION
❑ The individual control words in the micro-routine are referred to as
micro-instruction
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Micro-programmed Control

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Difference between Hardwired and Micro-programmed Control

HARDWIRED CONTROL MICRO-PROGRAMMED

ATTRIBUTE
UNIT CONTROL UNIT
SPEED FAST SLOW
COST OF
MORE CHEAPER
IMPLEMENTATION

NOT FLEXIBLE, DIFFICULT TO FLEXIBLE, NEW INSTRUCTIONS CAN BE

FLEXIBILITY
MODIFY FOR NEW INSTRUCTION ADDED

ABILITY TO HANDLE COMPLEX

DIFFICULT EASIER
INSTRUCTION

INSTRUCTION SET SIZE SMALL LARGE

CONTROL MEMORY ABSENT PRESENT

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Micro Instruction
❑A straightforward way to structure microinstructions is to assign one bit
position to each control signal.
❑However, this is very inefficient.
❑The length can be reduced: most signals are not needed simultaneously,
and many signals are mutually exclusive.
❑All mutually exclusive signals are placed in the same group in binary
coding.

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Partial Format for Micro Instruction

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Micro Instruction types
❑The grouping of control signals can be done in one of the two ways
❑Vertical Micro-programming
❑ Each micro-instruction specifies single (or few) micro-operations to be
performed.

❑Horizontal Micro-programming
❑Each micro-instruction specifies many different micro-operations to
be performed in parallel.

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Difference between Horizontal & Vertical Microprogramming

HORIZONTAL MICRO-PROGRAMMING VERTICAL MICRO-PROGRAMMING

Long formats Short formats

Ability to express a high degree of parallelism Limited ability to express parallel micro-operations

Considerable encoding of the control

Little encoding of the control information
information

Useful when higher operating speed is required Slower operating speed

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Addressing Modes
❑Specifies a rule for interpreting or modifying the address field of
the instruction (before the operand is actually referenced)
❑Variety of addressing modes
▪ to give programming flexibility to the user
▪ to use the bits in the address field of the instruction
efficiently

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Types of Addressing Modes
❑Implied Addressing Mode
❑Immediate Addressing Mode
❑Register Addressing Mode
❑Register Indirect Addressing Mode
❑Autoincrement/ Autodecrement Addressing Mode
❑Direct Addressing Mode
❑Indirect Addressing Mode
❑Relative Addressing Mode
❑PC Relative Addressing Mode
❑Indexed Addressing Mode
❑Base Register Addressing Mode
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Implied Addressing Mode
❑Address of the operands are specified implicitly in the definition
of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
Examples : CLA, CME, INP

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Immediate Addressing Mode
❑Instead of specifying the address of the operand, operand itself
is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
Example : ADD 5

opcode operand

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Register Addressing Mode
❑Address specified in the instruction is the register address
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory addressing
- EA = IR(R) (IR(R): Register field of IR)

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Register Indirect Addressing Mode
❑Instruction specifies a register which contains the memory
address of the operand
- Saving instruction bits since register address is shorter than
the memory address
- Slower to acquire an operand than both the register
addressing or memory addressing
- EA = [IR(R)] ([x]: Content of x)

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Autoincrement/Autodecrement Addressing Mode
❑When the address in the register is used to access memory, the
value in the register is incremented or decremented by 1
automatically
Example:
❑ Autoincrement: Load R1, (R2)+ is interpreted as R1 ← [[R2]]
followed by R2 ← [R2] + d where d is step size(step size is
dependent on size of operand).
❑ Autodecrement: Load R1, -(R2) is interpreted as R2 ← [R2] – d
followed by R1 ← [[R2]] where d is step size size(step size is
dependent on size of operand)

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Direct Addressing Mode
❑Instruction specifies the memory address which can be used
directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address for a large
physical memory space
- EA = IR(addr) (IR(addr): address field of IR)

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Indirect Addressing Mode
❑The address field of an instruction specifies the address of a
memory location that contains the address of the operand
- When the abbreviated address is used large physical memory
can be addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional
memory access
- EA = M[IR(address)]

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Relative Addressing Mode
❑The address field of an instruction specifies the part of the address
(abbreviated address) which can be used along with a designated
register to calculate the effective address of the operand
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of
address bits
- EA = f(IR(address), R), R is sometimes implied
❑3 different Relative Addressing Modes depending on R;
* PC Relative Addressing Mode (R = PC)
- EA = PC + IR(address)
* Indexed Addressing Mode (R = XR, where XR: Index Register)
- EA = XR + IR(address)
* Base Register Addressing Mode
(R = BAR, where BAR: Base Address Register)
- EA = BAR + IR(address)
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Addressing Modes Example

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Micro-Programmed Sequencing
❑If all micro-programs require only straightforward sequential execution of
microinstructions except for branches, letting a μPC governs the
sequencing would be efficient.
❑However, two disadvantages:
▪ Having a separate micro-routine for each machine instruction results
in a large total number of microinstructions and a large control store.
▪ Longer execution time because it takes more time to carry out the
required branches.
❑Example: Add src, Rdst
❑Four addressing modes: register, autoincrement, autodecrement, and
indexed (with indirect forms).

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Micro-Program for Add src Rdst

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Wide Branch Addressing
❑Generating branch addresses becomes more difficult as the number of
branches increases.
❑Programmable Logic Array can be used to generate the required branch
address.
❑The simple and inexpensive way of generating branch addresses is known
as wide branch addressing
❑This is achieved by connecting the opcode bits of the instruction register
as inputs to the PLA which acts as decoder.
❑The output of the PLA is the address of the desired micro-routine.

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Micro Instruction with Next Address Field
❑The micro-program requires several branch microinstructions, which
perform no useful operation in the datapath.
❑A powerful alternative approach is to include an address field as a part of
every microinstruction to indicate the location of the next microinstruction
to be fetched.
❑Pros: separate branch microinstructions are virtually eliminated; few
limitations in assigning addresses to microinstructions.
❑Cons: additional bits for the address field (around 1/6).
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Micro Instruction with Next Address Field

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Micro Instruction with Next Address Field

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Implementation of Micro-routine using next Micro-instruction address field

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Prefetching Microinstructions
❑The disadvantage of micro-programmed control is that it results slower
operating speed because of the time it takes to fetch micro-instructions
from the control memory.
❑This problem can be solved by prefetching the next microinstruction while
the current one is being executed.
❑In this technique, the execution time can be overlapped with the fetch
time.

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Complex Instruction Set Computer(CISC)
❑A computer system with large number of instructions.
❑Large number of addressing modes.
❑It uses Variable length instruction format.
❑It has some instructions that perform specialized task and are used
infrequently.
❑It has instructions that manipulate operands in memory.
❑Some examples are IBM 370/168, Intel 80386, Intel 80286, Sun-3/75.

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Reduced Instruction Set Computer(RISC)
❑It has relatively few instructions.
❑In comparison to CISC, it has few addressing modes.
❑The memory access is limited to load and store instructions.
❑All the operations are done within the registers of the CPU.
❑Single cycle instruction execution.
❑Fixed length easily decoded instruction format.
❑Hardwired control unit rather than micro-programmed control unit.
❑Some examples are MIPS R2000, SUN SPARC, Intel i860, Motorola 8800.
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Examples of C I S C and R I S C

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DIFF BETWEEN RISC AND CISC

RISC CISC
It is a Reduced Instruction Set Computer. It is a Complex Instruction Set Computer.

It emphasizes on software to optimize the instruction It emphasizes on hardware to optimize the instruction
set. set.
It is a hard wired unit of programming in the RISC Microprogramming unit in CISC Processor.
Processor.
It requires multiple register sets to store the It requires a single register set to store the instruction.
instruction.
RISC has simple decoding of instruction. CISC has complex decoding of instruction.

Uses of the pipeline are simple in RISC. Uses of the pipeline are difficult in CISC.
It uses a limited number of instruction that requires It uses a large number of instruction that requires
less time to execute the instructions. more time to execute the instructions.

It uses LOAD and STORE that are independent It uses LOAD and STORE instruction in the memory-to-
instructions in the register-to-register a program's memory interaction of a program.
interaction.
RISC has more transistors on memory registers. CISC has transistors to store complex instructions.

The execution time of RISC is very short. The execution time of CISC is longer.
RISC architecture can be used with high-end CISC architecture can be used with low-end
applications like telecommunication, image applications like home automation, security system,
processing, video processing, etc. etc.
It has fixed format instruction. It has variable format instruction.
The program written for RISC architecture needs to Program written for CISC architecture tends to take
take more space in memory. less space in memory.
Example of RISC: ARM, PA-RISC, Power Architecture, Examples of CISC: VAX, Motorola 68000 family,
Alpha, AVR, ARC and the SPARC. System/360, AMD and the Intel x86 CPUs.