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18 December 2019 1441 ‫الثان‬
‫ ربيع ي‬21
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Digital IC Design

Lecture 05
CMOS Layout (2)

Dr. Hesham A. Omran

Integrated Circuits Laboratory (ICL)
Electronics and Communications Eng. Dept.
Faculty of Engineering
Ain Shams University

This lecture is mainly based on “IC Mask Design” by C. Saint and J. Saint, 2002
 Padframe and IO Cells

CHIP CORE

05: CMOS Layout (2) 2

 ESD Protection
❑ Any ESD current will flow in the ESD diodes instead of flowing into the circuit
❑ The diodes should be large enough to handle high current spikes

05: CMOS Layout (2) 3

 Digital Layout
❑ Fixed height, variable width
❑ Continuous VDD, GND, and NWELL
Bad Good

05: CMOS Layout (2) 4

 Digital Layout
❑ Fixed height, variable width
❑ Share power rails between flipped rows
❑ No need for routing channels in modern technologies

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 Strapping Power Rails
❑ Distant cells see more resistance through the rails due to the length of wire
❑ By laying straps of metal across your power rails the overall resistance reduces

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 Directional Layer Technique
❑ Metal One runs horizontally and Metal Two runs vertically
❑ Allows wires to run in complex knots using few metal layers without becoming trapped
❑ Common for digital signals, but is not strictly followed for sensitive analog/RF signals

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 Directional Layer Technique
❑ This rule is not useful for short jumps
▪ Via resistance
▪ Blocking other wires
❑ Do NOT change metal layer for short jumps

05: CMOS Layout (2) 8

 Directional Layer Technique
❑ This rule is not useful for short jumps
▪ Via resistance
▪ Blocking other wires
❑ Do NOT change metal layer for short jumps

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 Digital vs Analog Layout
❑ Digital layout
▪ Primary objective is optimizing density
▪ Millions of gates
▪ Strict standard cell rules
❑ Analog layout
▪ Primary objective is matching and performance
▪ Few amplifiers
▪ Many options instead of many rules
▪ Strong interaction required between circuit and layout designers

05: CMOS Layout (2) 10

 Parasitic Capacitance
❑ Capacitance in the order of fF
❑ Important for high frequency and precision circuits
▪ Use short wire length
▪ Use isolated wire (far from everything else)
❑ You have to look at metal height from subs, width, and thickness

05: CMOS Layout (2) 11

 Parasitic Capacitance
❑ Capacitance in the order of fF
❑ Important for high frequency and precision circuits
▪ Use short wire length
▪ Use isolated wire (far from everything else)
❑ You have to look at metal height from subs, width, and thickness

05: CMOS Layout (2) 12

 Parasitic Capacitance
❑ Capacitance in the order of fF
❑ Important for high frequency and precision circuits
▪ Use short wire length
▪ Use isolated wire (far from everything else)
❑ You have to look at metal height from subs, width, and thickness

05: CMOS Layout (2) 13

 Parasitic Capacitance
❑ Avoid Routing over Circuitry
▪ Not important in digital, but may affect sensitive analog blocks/signals
❑ A good floorplan will help

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 Parasitic Resistance
❑ May cause large I*R drops
❑ Ex:
▪ 2mm long / 2 um width = 1000 squares
▪ R = 1000 squares * 50 mOhm/square = 50 Ohm
▪ Vdrop = I*R = 50 mV → definitely not acceptable
❑ Increase wire width to reduce resistance
▪ Max current density is not the only thing to worry about
❑ Or use thick metal in higher layers
❑ Or stack wires to save space

05: CMOS Layout (2) 15

 Parasitic Resistance
❑ May cause large I*R drops
❑ Ex:
▪ 2mm long / 2 um width = 1000 squares
▪ R = 1000 squares * 50 mOhm/square = 50 Ohm
▪ Vdrop = I*R = 50 mV → definitely not acceptable
❑ Increase wire width to reduce resistance
▪ Max current density is not the only thing to worry about
❑ Or use thick metal in higher layers
❑ Or stack wires to save space

05: CMOS Layout (2) 16

 MOS Capacitance/Resistance
❑ Use multi-finger layout
▪ Reduces gate resistance (multiple gate stripes in parallel)
• Splitting the device into two reduces RC time constant by 4
▪ Drain/source sharing reduces capacitance

05: CMOS Layout (2) 17

 Substrate Noise
❑ Very critical issue in mixed-signal chips

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 Substrate Noise: Go Far Away

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 Substrate Noise: Timing

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 Substrate Noise: Guard Rings

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 Substrate Noise: Guard Ring
❑ Avoid ANY current flow in guard rings
❑ Best practice: connect the substrate and guards with a separate star connection to the GND
pad (or use double bonds)

05: CMOS Layout (2) [www.eda-utilities.com] 22

 Substrate Noise: Guard Ring
❑ Avoid ANY current flow in guard rings
❑ Best practice: connect the substrate and guards with a separate star connection to the GND
pad (or use double bonds)

05: CMOS Layout (2) [www.eda-utilities.com] 23

 Substrate Noise: N-Well Barrier
❑ Separate analog and digital areas by an n-well
▪ High resistance path between analog and digital substrates
• The substrate has about 10 times higher doping at the surface
▪ Minimize the injection of noise from digital circuits into the substrate under the analog
circuit
❑ The well also acts as a bypass capacitor

05: CMOS Layout (2) [Johns and Martin, 2012] 24

 Substrate Noise: Double Guard Ring
❑ Conservative layout: VDD guard ring collect stray electrons in the substrate

05: CMOS Layout (2) [www.eda-utilities.com] 25

 Substrate Noise: Double Guard Ring
❑ Conservative layout: GND guard ring collect stray holes in the substrate

05: CMOS Layout (2) [www.eda-utilities.com] 26

 Substrate Noise: Shielding

❑ The GND line used for shielding must have quite low resistance

05: CMOS Layout (2) 27

 Shielding Sensitive/Noisy Signals

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 Routing Power Rails
❑ Better to place high current blocks near power pad
❑ Wire width can be tapered

05: CMOS Layout (2) 29

 Routing Power Rails
❑ Better to place high current blocks near power pad
❑ Wire width can be tapered
❑ Better technique: high current power line should be routed independently
▪ Star vs bus

05: CMOS Layout (2) 30

 Routing Power Rails
❑ Use lowest resistance metal layer
❑ Use FAT wires
▪ Do not use min width
▪ Do not stress the wire at its max current density
▪ Roughly 10% of the cell height

05: CMOS Layout (2) 31

 Supply Decoupling
❑ Decoupling provide low resistance path for high frequency noise
❑ Fill any white space in the layout with decoupling caps (should you use MOSCAP?)
❑ Stacked power rails give some free decoupling caps

05: CMOS Layout (2) 32

 Vias
❑ For analog and high current signals
▪ Do NOT use min metal width
▪ Do NOT use single via

Bad (for analog) Good (for analog)

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 Floorplanning: Wiring
❑ Neat flylines indicate good floorplanning
❑ Bad

❑ Good

05: CMOS Layout (2) 34

 Floorplanning: Wiring
❑ Minimizing the area is good
▪ But you must leave enough space for wiring
❑ Remember that “in general” you cannot route over other blocks
❑ Shielding, differential routing, power and clock routing, guard rings, etc., all take a lot of
area

05: CMOS Layout (2) 35

 Floorplanning: Wiring
❑ Bigger area, but more realistic

05: CMOS Layout (2) 36

 Floorplanning: Wiring
❑ Leave some free space for wiring, decoupling caps, last minute updates, etc.

Bad Good

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 Floorplanning: Pinout
❑ Inputs and outputs should be located near their appropriate cell block

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 Floorplanning: ESD
❑ Bad

❑ Good

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 Iterative Floorplanning
Bad Good

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 Clock Tree
❑ The clock should tick at all elements exactly at the same time

05: CMOS Layout (2) 41

 The Package
❑ The package type must be planned even before floorplanning
▪ The pinout (floorplanning)
▪ Chip area (the chip must fit inside the package)

05: CMOS Layout (2) 42

 Wire Bonding
❑ The bond wire is ultra-thin (~25um) Gold or Aluminum wire
❑ Ultrasonic wedge bonding
▪ Uses brute force (pressure) and ultrasound (vibration)

❑ Ultrasonic ball bonding

▪ Uses high voltage and ultrasonic to melt the wire

05: CMOS Layout (2) 43

 Wire Bonding Rules
❑ No sharp angles are allowed in wire bonding (< 45o)
❑ Keep wires as short as possible
▪ The bondwire could droop causing a short circuit

05: CMOS Layout (2) 44

 Bonding Diagram
❑ No sharp angles are allowed in wire bonding (< 45o)
❑ Keep wires as short as possible

Bad Good

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 Pad-limited vs Core-limited Design

Pad-limited Core-limited

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 Flip-chip Packaging
❑ Deposit bump of solder on each pad
❑ Flip, press, and heat
❑ Pads are not restricted to the periphery

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 Dicing
❑ Diamond saw cuts wafer into chips
▪ Seal ring around the whole chip
▪ Keep some room for the saw to run (~ 50 – 100um) → “Scribe Lanes”
▪ Keep a “scribe margin” away from the scribe lanes

05: CMOS Layout (2) 48

 Dicing
❑ The final size is what will go inside the package!

05: CMOS Layout (2) 49

 Thank you!

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 Layout Designer Questions
❑ What does this circuit do (function, frequency, precision, etc.)?
❑ How much current does it take (current density, min wire width)?
❑ Where are the high and low current paths (not all wires will carry high current)?
❑ What matching requirements are there?
❑ Is there anything else?

05: CMOS Layout (2) 51

 Layout Designer Questions

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 Ex: Routing with Multi-finger Device
❑ Ex: four-finger MOSFET
▪ 4 mA current
▪ 0.5 mA/um max density
▪ 8 um min wire
▪ 3 source regions
▪ 2 drain regions
▪ Source/drain metallization must handle the required
current
❑ Route from center not from sides
▪ Current spread out evenly

05: CMOS Layout (2) 53

 Matching: Orientation
❑ orientation-specific processing errors will severely degrade matching
❑ Use the same orientation for matched devices
❑ Also good practice to use the same orientation all over the chip
▪ Now a design rule for FinFET

05: CMOS Layout (2) 54

 Matching: Orientation
❑ Current should be flowing in same direction

05: CMOS Layout (2) [F. Maloberti, Layout of Analog CMOS IC] 55
 Matching: Unit Elements
❑ Applies to all components: transistors, resistors, capacitors, etc.

05: CMOS Layout (2) 56

 Matching: Unit Elements
❑ Terrible

❑ Good (use lowest common multiple)

05: CMOS Layout (2) 57

 Matching: Unit Elements
❑ Terrible

❑ Better (use middle value)

▪ Less contact resistance (their variation is worse)
▪ Larger area (less mismatch) (overall area is roughly the same)
▪ Note: Do NOT connect unit caps/transistors in series

05: CMOS Layout (2) 58

 Matching: Interdigitation
❑ Place the root component (LSB) in the center

05: CMOS Layout (2) 59

 Matching: Interdigitation
❑ Each of A and B is 4 fingers
▪ AABBAABB
▪ ABBAABBA
2 3
A B

05: CMOS Layout (2) [F. Maloberti, Layout of Analog CMOS IC] 60
 Matching: Dummies
❑ Structures at the ends have different boundary conditions compared to structures in the
middle
❑ Edges suffer from a big difference

05: CMOS Layout (2) 61

 Matching: Dummies
❑ Dummy structures MUST be used
❑ Applies for transistors, resistors, and capacitors
❑ Dummy devices connected to GND (NMOS) or VDD (PMOS)
❑ Dummy gate should not be connected to input to avoid increasing capacitive loading

05: CMOS Layout (2) [F. Maloberti, Layout of Analog CMOS IC] 62
 Matching: Dummies
❑ 2D arrays need dummies all around

05: CMOS Layout (2) 63

 Matching: Common Centroid
❑ Reduces the effect of process and thermal gradients (1st order)
❑ Essential for differential input pair
❑ Cross-quad matches better than linear, but takes more time to do

05: CMOS Layout (2) 64

 Matching: Common Centroid
❑ Reduces the effect of process and thermal gradients (1st order)
❑ Essential for differential input pair
❑ Cross-quad matches better than linear, but takes more time to do
❑ Ex: diff pair with AABBBBAA arrangement

05: CMOS Layout (2) [Johns and Martin, 2012] 65

 Matching: Common Centroid
❑ Reduces the effect of process and thermal gradients (1st order)
❑ Essential for differential input pair
❑ Cross-quad matches better than linear, but takes more time to do

05: CMOS Layout (2) [F. Maloberti, Layout of Analog CMOS IC] 66
 Matching: Common Centroid
❑ Reduces the effect of process and thermal gradients (1st order)

05: CMOS Layout (2) [Johns and Martin, 2012] 67

 Matching: Common Centroid
❑ Reduces the effect of process and thermal gradients

05: CMOS Layout (2) [F. Maloberti, Layout of Analog CMOS IC] 68
 Matching: Match the Parasitics
❑ Use extra metal overlaps to match wiring capacitance

05: CMOS Layout (2) 69

 Matching: Symmetry
❑ A is supposed to talk to B and C in the same way
❑ Capacitance to B and C should be matched

❑ Bad

❑ Good

05: CMOS Layout (2) 70

 Matching: Symmetry
❑ A is supposed to talk to B and C in the same way
❑ Capacitance to B and C should be matched

❑ Bad

❑ Good

05: CMOS Layout (2) [F. Maloberti, Layout of Analog CMOS IC] 71
 Matching: Differential Routing
❑ Bad

❑ Good

05: CMOS Layout (2) 72

 Matching: Differential Routing

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 Matching: Go Large
❑ Remember Pelgrom’s model
❑ Never use min feature sizes

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 Matching: Summary

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