This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCAD.2020.3035133, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems

Storage-Based Built-In Self-Test for Gate-Exhaustive f.e.

7
Faults 100% 6
5
Irith Pomeranz 4
3
2
Abstract— Built-in self-test (BIST ) approaches are suitable for in-field 1
testing since they do not require a tester for storage and application 0
of test data. They also reduce the security vulnerabilities associated
with loading and unloading of external test data into scan chains. As bits
technologies evolve, in-field testing needs to address more complex defect
and aging mechanisms that require specific deterministic tests. This can Fig. 1. Tradeoff between fault efficiency and stored test data.
be addressed by BIST approaches that store test data on-chip, and use
the data for on-chip generation of both random and deterministic tests.
In this case, there is a tradeoff between the amount of stored test data
and the comprehensiveness of the test set that can be applied. This paper In addition to stuck-at faults, the set of target faults includes
explores this tradeoff in a specific context that has the following main single-cycle (static) gate-exhaustive faults [19]. These are used for
features. (1) The initial stored test data is based on a stuck-at test set. (2) representing the need to cover a large number of defects with specific
The target faults are single-cycle gate-exhaustive faults. (3) The stored behaviors that are more difficult to detect than stuck-at faults. Gate-
test data is enhanced gradually by test data based on a gate-exhaustive
test set to increase the coverage of gate-exhaustive faults. exhaustive faults are suitable for this purpose since their number is
large, and they require more values to be assigned by a test. The
Index Terms— Built-in self-test (BIST ), gate-exhaustive faults, on-chip
set of detectable gate-exhaustive faults is denoted by Fgexh , and a
test generation, stuck-at faults.
deterministic test set for gate-exhaustive faults is denoted by Tgexh .
It is also possible to consider a test set for transition faults as an
I. I NTRODUCTION initial source for test data, and two-cycle (dynamic) gate-exhaustive
Built-in self-test (BIST ) approaches are suitable for in-field faults as additional target faults.
testing since they do not require a tester for storage and application When the pair (S0 , T0,dtrm ) is used for on-chip test generation,
of test data [1]-[10]. They also reduce the security vulnerabilities the coverage of gate-exhaustive faults may not be complete. An
associated with loading and unloading of external test data into scan iterative software procedure produces a series of pairs (S0 , T0,dtrm ),
chains [3]. (S1 , T1,dtrm ), ..., (Sm−1 , Tm−1,dtrm ). For i > 0, the procedure
As technologies evolve, in-field testing needs to address more obtains Si from Si−1 by adding at least one new scan vector based
complex defect and aging mechanisms that require specific tests [11]- on Tgexh . The scan vectors added to Si allow the coverage of gate-
[14]. This can be addressed by BIST approaches that store test data exhaustive faults to be increased when the on-chip test generation
on-chip, and use the data for on-chip generation of both random and logic is used for (Si , Ti,dtrm ). With (Sm−1 , Tm−1,dtrm ), complete
deterministic tests. coverage of gate-exhaustive faults is achieved. In many cases, the
Different from hybrid approaches that combine test data compres- increased fault coverage is achieved by random tests that use scan
sion with on-chip test generation [15]-[18], a BIST approach stores vectors from Si , and Ti,dtrm = ∅.
all the test data on-chip. This is the type of approach considered in Figure 1 illustrates the tradeoff explored by the software procedure
this paper. In this approach, there is a tradeoff between the amount that produces the pairs (Si , Ti,dtrm ) for i ≥ 0. Figure 1 is based on
of stored test data and the comprehensiveness of the test set that can the results obtained later for benchmark circuit s1423. A circle with
be applied. The paper explores this tradeoff in the following context. i above it corresponds to a test set Ti . The horizontal axis in Figure
The circuit under consideration has n scan chains of length l. One 1 shows the number of storage bits for Ti . The vertical axis shows
component of the stored test data is a set Si of scan vectors. Using the fault efficiency, which is the percentage of detected faults out of
only scan vectors from Si , an on-chip test generation logic applies a the detectable faults, achieved for gate-exhaustive faults by Ti . The
fixed number of tests referred to as random, where scan vectors are fault efficiency reaches 100% in iteration i = 7.
selected randomly from Si , and a small number of tests referred to In Figure 1, when the pair (S1 , T1,dtrm ) is computed in iteration
as deterministic that consist of specific scan vectors from Si . The set 1, it has a lower number of storage bits than (S0 , T0,dtrm ), and a
of deterministic tests is denoted by Ti,dtrm , and it requires additional higher fault efficiency. Therefore, the solution obtained in iteration 1
storage of test data (indices of scan vectors from Si that form the tests is preferred over the solution obtained in iteration 0. Overall, there
in Ti,dtrm ). The test set produced on-chip is denoted by Ti , and it are seven viable solutions in Figure 1, corresponding to (Si , Ti,dtrm )
changes with Si and Ti,dtrm . The on-chip test generation logic is the for i = 1, 2, 3, 4, 5, 6 and 7.
same for every Si and Ti,dtrm , and every circuit. Only its parameters The approach described in this paper is developed for the case
(e.g., memory and multiplexer sizes) are circuit-dependent. where a circuit has a large number of scan chains, making the scan
A deterministic test set Tsa for single stuck-at faults is used as an chain length small enough for storage of scan vectors to be feasible.
initial source for test data. The test data is a set S0 of scan vectors A large number of scan chains is also used by test data compression
based on Tsa , and a set T0,dtrm of deterministic tests to complement approaches to control the test application time.
the random tests based on S0 . With S0 and T0,dtrm , and the on- The paper is organized as follows. The on-chip test generation logic
chip test generation logic, T0 detects all the detectable single stuck- is described in Section II. A software procedure for computing the
at faults. The set of single stuck-at faults is denoted by Fsa . The sets Si and Ti,dtrm is described in Section III. Experimental results
effectiveness of the random tests is enhanced by using stored scan for benchmark circuits are presented in Section IV.
vectors from Tsa .
II. O N -C HIP T EST G ENERATION
Irith Pomeranz is with the School of Electrical and Computer Engineer-
ing, Purdue University, West Lafayette, IN 47907, U.S.A. (e-mail: pomer-
The scan configuration assumed in this paper has n scan chains.
[email protected]). For simplicity it is assumed that all the scan chains have the same
The work was supported in part by NSF Grant No. CCF-2041649. length, l. This can be achieved by padding each scan chain until its

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Transactions on Computer-Aided Design of Integrated Circuits and Systems

TABLE I
E XAMPLE T EST S ET

(a) Scan Vectors T i,dtrm TGL

p 0 1 2 3 4 5
sp 011 110 000 101 010 001
0, k 1, k . . . d − 1,
k
(b) Test Set
j πj j0 j1 j2 tj,0 tj,1 tj,2 LFSR
0 0 4 1 5 010 110 001
1 0 1 1 3 110 110 101
2 0 2 1 5 000 110 001
3 0 2 2 0 000 000 011 c 0 1 d −1 d
4 1 5 4 5 001 010 001 n MUX1k
5 1 5 5 5 001 001 001 t

addr k
length reaches l. Padding is not needed for the physical circuit, only
for the model used by the software procedure to compute the test
data for the on-chip test generation logic.
One component of the test data stored on-chip is a set of scan scan chain k
vectors, Si = {s0 , s1 , ..., sv−1 }. For illustration, Table I(a) shows Si MUX2k
the set S0 obtained for a circuit with n = 3 scan chains of length
l = 3.
A test tj is formed by selecting n scan vectors from Si , one for
every scan chain. With scan vectors sj0 , sj1 , ..., sjn−1 , we have that
tj = sj0 , sj1 , ..., sjn−1 . For 0 ≤ k < n, the scan vector for scan Fig. 2. On-chip test generation logic.
chain k is denoted by tj,k = sjk .
Table I(b) shows a test set T0 obtained for the circuit from Table
I(a). For every test tj , Table I(b) shows the indices j0 , j1 , j2 , and every scan chain, resides close to the memories, within the outline
the subtests tj,0 , tj,1 and tj,2 . The variable πj is explained next. marked T GL in Figure 2. Each scan chain is driven by a single
The on-chip test generation logic applies two types of tests. A line, represented by the output of M U X2k in Figure 2. The routing
random test tj = sj0 , sj1 , ..., sjn−1  is designated by πj = 0. In overhead is similar to that of test data decompression logic that drives
this case, for 0 ≤ k < n, the scan vector sjk for the subtest tj,k is all the scan chains.
selected randomly. For the output response it is assumed that sequential output
A deterministic test tj = sj0 , sj1 , ..., sjn−1  is designated by compaction will be performed by output compaction logic such as a
πj = 1. In this case, the set of indices j0 , j1 , ..., jn−1 is stored in an multiple-input shift-register (M ISR) [1].
on-chip memory.
The on-chip test generation logic is illustrated by Figure 2. The III. P ROCEDURE FOR C OMPUTING S TORED T EST DATA
lower part of Figure 2 shows the memory storing the set of scan
This section describes an iterative software procedure for comput-
vectors Si . The size of the memory is v × l. It also shows scan chain
ing sets of scan vectors Si and deterministic tests Ti,dtrm for on-chip
k of length l. A multiplexer called M U X2k selects one of the scan
test generation. For simplicity of discussion, Si is associated with a
vectors from Si depending on the variable called addrk. The number
test set Ti that consists of both random and deterministic tests. The
of bits in addrk is log2 (v). The selected scan vector is scanned into
non-random tests in Ti define Ti,dtrm .
scan chain k. For a test tj it defines the subtest tj,k .
The value of addrk is computed by the logic in the upper part of
Figure 2. If only random tests are applied, the dashed part of Figure A. Overview
2 is not needed, and an LF SR produces the values for addrk. In The procedure accepts a test set Tsa for single stuck-at faults, and
general, the deterministic part of the test set Ti , Ti,dtrm , is stored a test set Tgexh for gate-exhaustive faults. It produces sets of scan
in a memory of size d × n × log2 (v), where d is the number of vectors S0 , S1 , ..., Sm−1 , with test sets T0 , T1 , ..., Tm−1 .
deterministic tests. The entries inside Ti,dtrm in Figure 2 correspond At the beginning of iteration i = 0, the procedure initializes S0
to scan chain k. These are indices of scan vectors that need to be based on Tsa , as follows. All the distinct scan vectors of Tsa are
loaded into scan chain k under the deterministic tests t0 , t1 , ..., td−1 . included in S0 , and T0 = Tsa initially. With this initialization, every
A counter denoted by cnt determines which test is applied through test in T0 can be expressed in terms of scan vectors from S0 .
a multiplexer denoted by M U X1k. A count value between 0 and At the beginning of iteration i > 0, Si = Si−1 and Ti = Ti−1 .
d − 1 corresponds to a deterministic test from Ti,dtrm . A count value At the end of iteration 0 ≤ i ≤ m − 2, the procedure adds at least
of d corresponds to a random test. In this case, the LF SR provides one scan vector to Si . It adds tests that use the new scan vectors to
log2 (v) bits selecting a scan vector randomly from Si . The counter Ti . The procedure terminates when, at the end of iteration m − 1, it
stays at d to apply R random tests, for a parameter R. does not add any scan vectors to Sm−1 .
The memories Si and Ti,dtrm , as well as the counter and LF SR, An arbitrary iteration i proceeds as described next. The procedure
are common to all the scan chains. In the case of the LF SR, each referred to as Procedure 0 is applied first to remove unnecessary scan
scan chain uses a distinct subset of bits to obtain a different random vectors from Si . The test set Ti is modified to ensure that it uses only
number. In addition, each scan chain requires two multiplexers. scan vectors from Si .
The overall storage requirements for the two memories are v · l + The procedure referred to as Procedure 1 first stores the current
d · n · log2 (v) bits. The memories dominate the size of the on-chip test set Ti in a test set denoted by Tcand , and initializes Ti to be
test generation logic. empty. All the target single stuck-at faults are included in Fsa , and
The entire test generation logic, including both multiplexers for all the target gate-exhaustive faults are included in Fgexh .

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For a parameter R, Procedure 1 includes R random tests in Ti . For C. Procedure 1

every test it performs fault simulation with fault dropping of Fsa and Procedure 1 initially assigns Tcand = Ti , Ti = ∅, and includes all
Fgexh . It then uses deterministic tests from Tcand to detect additional the target faults in Fsa and Fgexh .
faults from Fsa and Fgexh using only scan vectors from Si . Procedure 1 includes R random tests in Ti , for a parameter R.
All the detectable stuck-at faults from Fsa are guaranteed to be A random test tj is constructed by selecting tj,k randomly from Si
detected by Ti after Procedure 1 is applied. The procedure terminates (or using the LF SR in Figure 2), for 0 ≤ k < n. The procedure
if all the detectable gate-exhaustive faults from Fgexh are detected performs fault simulation with fault dropping of tj under Fsa ∪Fgexh ,
by Ti as well. Otherwise, Procedure 2 adds to Ti a limited number for every random test tj .
of additional deterministic tests based on Tgexh to detect additional Next, the procedure uses tests from Tcand as deterministic tests
gate-exhaustive faults. As much as possible, Procedure 2 uses only to detect additional faults from Fsa ∪ Fgexh . The goal is to ensure
scan vectors that are already included in Si . When this is not possible, that both the stuck-at and gate-exhaustive fault coverages of Ti
Procedure 2 adds to Ti tests that require new scan vectors, which are are not lower than those of Tcand . This ensures that the stuck-at
added to Si . The procedure prefers tests that require the smallest fault coverage is maintained, and the gate-exhaustive fault coverage
possible numbers of new scan vectors. increases monotonically with every iteration until all the detectable
As Ti is modified, the procedure maintains fault detection in- gate-exhaustive faults are detected in the last iteration. For every test
formation for Ti . Fault detection information is obtained by fault tj ∈ Tcand , the procedure applies the following steps.
simulation with fault dropping of Fsa ∪ Fgexh under Ti . For a fault The procedure simulates Fsa ∪ Fgexh under tj . If no faults are
f ∈ Fsa ∪ Fgexh , the first test in Ti that detects it is denoted by detected, the procedure does not consider tj further. Otherwise, it
tdet(f ) . For an undetected fault, det(f ) = −1. Fault simulation with attempts to modify tj to increase the number of faults it detects out
fault dropping is also applied at the end of every procedure. of Fsa ∪ Fgexh . For this purpose, the procedure includes in F (tj )
all the faults that tj detects. It then considers every scan chain 0 ≤
k < n, and every scan vector sp ∈ Si . If tj,k = sp , the procedure
B. Procedure 0 defines a test tmod
j that is equal to tj , except that tmodj,k = sp . It
For Procedure 0 all the tests in Ti are considered as deterministic. simulates the faults in F (tj ) under tmod
j,k . If all the faults are detected,

Procedure 0 associates with every scan vector sp ∈ Si the number of it also simulates the faults in Fsa ∪ Fgexh under tj . Let the subset of
times it is used by a test in Ti . This number is denoted by a(sp ). The detected faults be F (tmod
j ). The procedure accepts the modification
procedure considers the scan vectors by increasing order of a(sp ). of tj if F (tj ) ⊆ F (tmod
j ). In this case, it assigns tj = tmod j and
This is based on the expectation that it will be easier to remove F (tj ) = F (tj ). Otherwise, it discards tmod
mod
j .
from Si a scan vector that is used fewer times by tests from Ti . The If the number of faults detected by tj was increased, the procedure
procedure maintains the variables a(sp ) up-to-date as it modifies the performs another pass over all the scan chains and all the scan vectors
test set. A scan vector sp with a(sp ) = 0 is removed from Si . in Si . The final test tj is added to Ti , and the faults it detects are
When the procedure considers sp for removal, let the subset of removed from Fsa and Fgexh .
tests where sp appears be T (sp ). Let the subset of faults that the After considering every test tj ∈ Tcand , Ti detects all the faults
tests in T (sp ) detect be F (sp ). To facilitate the modification of the from Fsa ∪ Fgexh that Tcand detects, and possibly additional faults
tests in T (sp ), the procedure simulates F (sp ) under Ti \ T (sp ). If a from Fgexh .
fault f ∈ F (sp ) is detected by a test tj ∈ Ti \ T (sp ), the procedure
assigns det(f ) = j, and removes the fault from F (sp ). D. Procedure 2
The procedure considers every subtest tj,k such that tj,k = sp Procedure 2 adds to Ti a limited number of tests based on Tgexh .
separately. For tj,k , it considers as an alternative every scan vector Its goal in selecting which tests will be added is to detect as many
sq ∈ Si such that a(sq ) = 0 and q = p. To check whether sq is additional gate-exhaustive faults as possible using only scan vectors
an acceptable alternative, the procedure assigns tj,k = sq . It then that are already included in Si , or require the addition of as few new
simulates every fault f ∈ Fsa ∪ Fgexh such that det(f ) = j under scan vectors to Si as possible. It stops after a limited increase in the
the modified tj . The modification of tj is accepted if all the faults gate-exhaustive fault efficiency is achieved to avoid a large increase
with det(f ) = j are detected. Otherwise, the procedure reassigns in the storage requirements in a single iteration. The number of tests
tj,k = sp . If none of the alternatives to sp is acceptable, the procedure from Tgexh that the procedure uses depends on the circuit and the
concludes that sp cannot be removed, and it does not consider other iteration. The tests are modified as described below to ensure that as
subtests where sp appears. few new scan vectors as possible are added to Si .
The procedure considers the tests in T (sp ) by decreasing order of Procedure 2 is applied iteratively until it achieves its goal. In each
the number of faults they detect. This is based on the expectation pass of Procedure 2, it considers every test tj ∈ Tgexh . When it
that tests with larger numbers of detected faults are more difficult considers tj , it first performs fault simulation of Fgexh under tj . If
to modify. If such a test cannot be modified, the procedure will not any faults are detected, the procedure continues with tj as follows.
consider other tests in T (sp ). It assigns tnew j = tj , and includes the faults detected by tj in a
The procedure considers the replacement scan vectors sq by set F (tnew
j ). It also assigns jknew = −1 for 0 ≤ k < n to indicate
increasing order of the number of appearances in Ti , a(sq ). This that the scan vectors of tnew j may not be included in Si . It then
is based on the expectation that a more uniform use of scan vectors considers every scan chain 0 ≤ k < n, and every scan vector sp ∈ Si .
allows faults to be detected more uniformly, and makes it easier to The procedure defines a test tmod j that is equal to tnew
j , except that
modify the test set. tmod
j,k = s p and j mod
k = p. It simulates the faults in F (tj ) under
After considering all the scan vectors in Si for removal, if any tmod
j . If all the faults are detected, it also simulates the faults in Fgexh
scan vector was removed from Si , the procedure performs another under tj . Let the subset of detected faults be F (tmod j ). The procedure
pass over the scan vectors in Si , in case additional scan vectors can accepts the modification of tnew j if F (tnew
j ) ⊆ F (tmod
j ). In this
be removed after modifying the test set. Procedure 0 terminates after case, it assigns tnew j = tmod
j and F (tnew
j ) = F (tmod
j ). Otherwise,
a pass that does not reduce the number of scan vectors in Si . it discards tmod j .

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Transactions on Computer-Aided Design of Integrated Circuits and Systems

TABLE II
If the procedure modified jknew = −1 into jknew ≥ 0 for at least
E XPERIMENTAL R ESULTS
one scan chain k, it performs another pass over all the scan chains
with jknew = −1. When modification of tnew j ends, let n(tnew
j ) be the bits gexh
number of detected gate-exhaustive faults, and m(tnew j ) the number circuit K n i dtrm vect tot tot/gexh f.e. ntime
s35932 1764 42 0 0 444 18648 0.392 100.000 9505.74
of scan chains k for which jknew = −1. b04 81 9 1 1 30 315 0.017 100.000 1394.00
If m(tnew
j ) = 0, tnew
j uses only scan vectors from Si , and detects des area 400 20 0 0 431 8620 0.057 100.000 1659.84
n(tj ) gate-exhaustive faults. In this case, the procedure adds tnew
new
j
sasc 144 12 0 0 112 1344 0.089 100.000 1023.12
simple spi 169 13 1 0 47 611 0.015 100.000 8612.06
to Ti , and removes the faults it detects from Fgexh . Otherwise, the spi 289 17 4 1 241 4233 0.008 100.000 63387.09
procedure defers the decision on tnew j to the end of the pass. systemcdes 324 18 0 0 224 4032 0.125 100.000 1753.96
At the end of the pass, if no test with m(tnew j ) = 0 was added usb phy 121 11 0 0 43 473 0.049 100.000 484.20
i2c 169 13 1 0 60 780 0.022 99.339 3217.24
to Ti , the procedure selects the test tnewj with the smallest value of i2c 169 13 3 2 57 897 0.025 99.807 7068.20
m(tnew
j ), and the largest value of n(tnewj ). It adds to Si all the new i2c 169 13 4 5 60 1170 0.032 100.000 8998.16
scan vectors used by tnew j , i.e., Si = Si ∪ {tnew j,k : 0 ≤ k < n, jk =
tv80 400 20 1 128 260 28240 0.049 99.574 12073.79
tv80 400 20 2 129 262 28460 0.050 99.778 24388.65
−1}. It also adds tnewj to Ti . tv80 400 20 4 134 287 29860 0.052 100.000 33120.68
After adding at least one new scan vector to Si , Procedure 2 b15 484 22 1 1503 221 269390 0.261 99.539 52786.41
terminates if the gate-exhaustive fault efficiency is increased by a b15 484 22 2 1626 214 290884 0.282 99.705 76645.83
b15 484 22 3 1768 212 315832 0.306 99.932 115207.67
parameter denoted by Δgexh . This parameter is needed to ensure b15 484 22 4 1802 206 321684 0.312 100.000 146831.08
that the gate-exhaustive fault efficiency increases substantially with wb dma 784 28 1 14 209 8988 0.039 99.455 11906.35
every iteration. Procedure 2 also terminates when all the faults in wb dma 784 28 2 17 229 10220 0.044 99.660 19847.86
wb dma 784 28 3 17 257 11480 0.049 99.865 25788.47
Fgexh are detected. Before using Ti in iteration i + 1, the procedure wb dma 784 28 4 22 266 12992 0.056 100.000 30586.44
performs forward-looking reverse order fault simulation to remove s5378 225 15 1 0 159 2385 0.028 98.833 3729.10
s5378 225 15 3 0 171 2565 0.030 99.238 9174.20
unnecessary tests from Ti . s5378 225 15 4 0 179 2685 0.031 99.440 10663.98
s5378 225 15 5 0 183 2745 0.032 99.642 13204.55
IV. E XPERIMENTAL R ESULTS s5378 225 15 7 0 193 2895 0.034 100.000 16628.05
s9234 256 16 0 145 303 25728 0.117 98.493 2576.53
The software procedure for computing the sets Si and Ti was s9234 256 16 1 213 232 30976 0.141 99.181 8841.67
applied to benchmark circuits. s9234 256 16 2 234 222 33504 0.152 99.632 14736.02
s9234 256 16 3 262 224 37120 0.169 99.941 20309.77
The following parameter values were used. For a circuit with K s9234 256 16 4 264 221 37328 0.170 100.000 25101.02
flip-flops, the flip-flops were partitioned into n scan chains such that s1423 100 10 1 0 53 530 0.067 98.609 1241.20
n2 ≥ K. If necessary, n2 − K flip-flops were added for padding. s1423 100 10 2 1 53 590 0.075 98.851 1936.00
s1423 100 10 3 1 57 630 0.080 99.093 2473.00
The length of a scan chain was l = n. This yields a large number of s1423 100 10 4 1 59 650 0.082 99.335 3153.60
short scan chains. Other configurations with the same property can s1423 100 10 5 1 63 690 0.087 99.577 3681.20
be used instead. s1423 100 10 6 1 67 740 0.093 99.819 4205.00
s1423 100 10 7 1 69 760 0.096 100.000 4861.20
The required increase in the gate-exhaustive fault efficiency for s13207.1 729 27 1 0 484 13068 0.026 90.974 26106.04
every iteration, Δgexh , was set as follows. When the gate-exhaustive s13207.1 729 27 2 0 498 13446 0.027 91.992 40675.93
s13207.1 729 27 3 0 522 14094 0.028 93.148 49713.95
fault efficiency after the first application of Procedure 1 is at least s13207.1 729 27 4 0 548 14796 0.030 94.176 62855.36
95%, Δgexh = 0.2%. Otherwise, Δgexh = 1%. The circuit name s13207.1 729 27 5 0 586 15822 0.032 95.232 73768.11
is followed by ”.1” in this case. These values prevent the procedure s13207.1 729 27 6 0 611 16497 0.033 96.345 87076.30
s13207.1 729 27 7 0 633 17091 0.034 97.420 96723.46
from performing an excessive number of iterations. s13207.1 729 27 8 0 648 17496 0.035 98.444 103565.09
When the fault efficiency after the first application of Procedure s13207.1 729 27 9 0 714 19278 0.039 99.472 112481.73
1 is lower than 95%, Procedure 2 selects a deterministic test after s13207.1 729 27 10 0 737 19899 0.040 100.000 122845.27
s15850.1 625 25 0 3 288 7875 0.013 86.801 1509.86
considering ten tests from Tgexh that detect new faults. This is s15850.1 625 25 1 32 349 15925 0.025 88.121 5625.45
important for limiting the computational effort of the procedure. s15850.1 625 25 2 60 433 24325 0.039 89.297 10849.58
s15850.1 625 25 3 46 521 24525 0.039 90.465 19150.70
To define gate-exhaustive faults, the circuit was partitioned into s15850.1 625 25 4 59 607 29925 0.048 91.554 25021.39
two-level subcircuits with at most 10 inputs. Each subcircuit was used s15850.1 625 25 5 75 699 36225 0.058 92.622 31400.64
as a gate, and all its gate-exhaustive faults were added to Fgexh . Test s15850.1 625 25 7 72 908 40700 0.065 94.663 46743.86
s15850.1 625 25 8 66 1002 41550 0.066 95.694 59461.09
generation was carried out to produce the test set Tgexh . Undetectable s15850.1 625 25 10 66 1233 48975 0.078 97.706 83019.74
faults were eliminated from Fgexh . s15850.1 625 25 11 81 1356 56175 0.089 98.709 96543.31
The number of random tests was R = 4000|Tsa |. This number s15850.1 625 25 12 88 1420 59700 0.095 99.733 114753.56
s15850.1 625 25 13 95 1448 62325 0.099 100.000 127918.80
was selected based on experimental results indicating that a small b14.1 289 17 0 216 250 33626 0.045 85.838 7310.89
number of deterministic tests is typically needed for complementing b14.1 289 17 1 287 218 42738 0.057 86.705 16520.68
this number of random tests. b14.1 289 17 2 377 225 55097 0.074 87.892 25899.69
b14.1 289 17 3 477 243 69003 0.093 88.984 36228.38
The results for iteration i of the procedure are reported before b14.1 289 17 4 662 278 106012 0.142 90.216 49101.41
Procedure 2 adds new scan vectors to Si . Up to this point, the b14.1 289 17 5 804 281 127789 0.172 91.122 64176.50
b14.1 289 17 6 991 284 156451 0.210 92.200 77742.39
procedure utilizes the scan vectors in Si for both random and b14.1 289 17 7 1148 309 180897 0.243 93.202 92378.23
deterministic tests (new scan vectors that are added to Si are utilized b14.1 289 17 8 1287 341 202708 0.272 94.152 109924.09
for random tests only in iteration i + 1). b14.1 289 17 9 1453 346 228191 0.306 95.172 126674.31
b14.1 289 17 10 1602 349 251039 0.337 96.212 148285.70
Referring to Figure 1, not every iteration yields improved results b14.1 289 17 11 1793 366 280551 0.377 97.381 170142.53
compared with later iterations. The results are reported only for b14.1 289 17 12 1928 377 301393 0.405 98.318 190629.62
b14.1 289 17 13 2057 398 321487 0.432 99.242 219983.75
iterations with improved results. b14.1 289 17 14 2181 414 340731 0.457 100.000 240957.95
The results are reported in Table II as follows. For most of the s38417 1681 41 0 53 1393 81016 0.029 96.530 20061.56
circuits in Table II, there is a row for every iteration that yields an s38584 1521 39 0 36 577 36543 0.043 99.509 5836.27
improved solution until 100% fault efficiency is reached for gate-
exhaustive faults. These circuits are arranged by increasing number

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Transactions on Computer-Aided Design of Integrated Circuits and Systems

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are considered with a single iteration to demonstrate the results demonstrated this tradeoff for benchmark circuits.
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0278-0070 (c) 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Authorized licensed use limited to: University of Ghana. Downloaded on December 18,2020 at 22:08:15 UTC from IEEE Xplore. Restrictions apply.