Model Question Bank

VLSI Circuits and Systems (EC30005)

Module-1: Introduction to VLSI Design

Short Answer Type Question:

1.​ When an IC designer chooses a full custom IC design methodology, mention two reasons.
2.​ Mention the Importance of Behavioral simulation and synthesis in VLSI design
3.​ When a functionally equivalent off-the-shelf component is not available in the market,
which design methodology an IC designer can choose when time to market is a concern,
mention the reason for choosing it.
4.​ When a functionally equivalent off-the-shelf component is not available in the market,
there are no existing cell libraries available. Which design methodology an IC designer
can choose when time to market is not a concern, mention the reason for choosing it.
Descriptive type:
1.​ Draw a neat labeled diagram of Gajski’s Y-chart and explain how the VLSI chip design is
perceived.
2.​ A video processing IC with enhanced features is desired, but the constraints for this
design are low power, high performance, and small area. State and explain the VLSI
design style that is to be used keeping in mind the above constraints.
3.​ A large-scale fast prototyping system has been produced by using FPGA.
(a)​ Discuss the pros and cons of such prototyping systems for proof of design
concepts and verification given the effort and speed performance of the design.
(b)​How would you compare the hardware prototyping method with the computer
simulation model?
4. With a neat sketch, show the steps of a VLSI design flow consisting of synthesis and
verification.
5. With a neat sketch discuss FPGA architecture by highlighting the following: CLB, I/O Block
and switch matrix.

Module-2: MOS Transistor and its operations

Short answer type questions:

1.​ Define the flat band condition and flat band voltage of MOSFET.
2.​ Why is negative body bias (VSB) not applied for NMOS transistors?
3.​ Mention the approximation made in the Gradual Channel Approximation technique.
4.​ Draw a graph indicating variation in threshold voltage with body bias for n-channel MOS
transistors.
5.​ Why is the channel length modulation effect prominent in short-channel MOSFETs?
6.​ How is the output resistance of a MOS transistor affected by channel length modulation?
7.​ Consider a nMOS as shown in Figure below. What will be the change in I_DS if V_DD
changes from 3.3 V to 1.8 V. Assume Vth=0.5 V and μn Cox (W/L)=100 μA/V^2.
 8.​ The threshold voltage of a nMOS is 0.5 V. If the device is biased at a 𝑉𝐺𝑆 of 3 V, then at
what drain voltage pinch-off would occur?

Descriptive type:

1.​ An enhancement-type nMOS transistor has the following parameters:

Vt0=0.8V
Ƴ=0.2 V1/2
λ=0.05 V-1 ​ `
|2φF |= 0.58 V
μn.Cox= 30 μA/V2
(a) When the transistor is biased with VG= 2.8 V, VD= 5 V, Vs =1 V,
and VB =1 V, the drain current is ID = 0.24 mA. Determine W/L.
(b) Calculate ID for VG= 4 V, VD= 4 V, Vs= 2 V, and VB= 1V

2.​ The following parameters are used for an NMOS transistor. Substrate doping ND = 1015
cm-3, polysilicon gate doping density ND = 1020 cm-3, gate
oxide thickness tox = 400 A0, and oxide-interface charge density NOX=2 x 1010 cm-2.
εsi = 11.7ε0 and εox = 3.97ε0 for the dielectric coefficients of silicon and silicon dioxide,
respectively.

3.​ The reported experimental data of one n- n-MOSFET is listed in the table below.
Determine the device parameters VTO, γ, κ=µ.Cox.(W/L) and λ. Assume |2Φf|=0.7
Volt. [6]

VDS(V) VGS(V) VBS(V) ID

(µA)
5 2 0 10
5 5 0 400
5 5 -3 280
8 5 0 480
 4.​ Compare full scaling and voltage scaling in terms of drive current, power dissipation,
power density, and gate capacitance. Which type of scaling is preferred for low power
and which one is preferred for high-speed applications? Justify your answers.
5.​ A CMOS process is scaled down by a factor of 1.5. What will be the oxide capacitance,
drain current, power dissipation and power density if (a) full scaling is used and (b)
voltage scaling is used?
6.​ The following parameters are given for an nMOS process.
●​ tox=500Å
●​ Substrate doping NA=1016 cm-3
●​ Polysilicon gate doping ND=1020cm-3
●​ Oxide interface charge density Nox=2x1010cm-2
(a)​ Calculate VT for unimplanted transistors.
(b)​What type and what doping concentration of impurities must be implanted to achieve a
threshold voltage VT=+2V and VT=-2V?

6. An enhancement nMOS has the following parameters:

Electron mobility (µn)=300cm2/Vs, Gate oxide thickness (tox=500Å), surface potential at strong
inversion (|2phi_f|)=0.64V, depletion charge density (at zero VSB) =4.81x10-8C/cm2, (W/L)=10,
poly-silicon gate doping (ND)=1020cm-3. The drain and gate terminal of MOSFET are connected,
and the source and body are connected to the ground. Under this condition, it delivers a drain
current of 2mA. Solve the current equation and find the required value of gate voltage (VG) and
drain voltage (VD). Ignore CLM effect if any.

7. An enhancement nMOS has the following parameters.

µn=340cm2/Vs, tox=210Å, |2Φf|=0.74V, polysilicon gate doping =ND=1020cm-3,
Neglect the effect of bulk charge and oxide interface charge densities. Calculate VGS if
VD=3.3V, VS=0.4V, VB=0V, 𝞬=0.1V-1/2, (W/L)=2 and ID=2mA. Assuming the transistor operates
in a linear region.
8. An enhancement nMOS has the following parameters:
Electron mobility (µn)=400cm2/Vs, Gate oxide thickness (tox=300Å), surface potential at strong
inversion (|2Φf|)=0.82V, depletion charge density (at zero VSB) =5.0x10-8C/cm2, (W/L)=10,
poly-silicon gate doping (ND)=1020cm-3.

The MOSFET is connected in a circuit as shown in Figure. Under this condition, it delivers a
drain current of 2 mA. Solve the current equation and find the required value of gate voltage
(VG) and drain voltage (VD). Ignore the channel length modulation effect, if any. Symbols have
their usual meanings.
 Module-3: CMOS Inverter and its operations

1.​ Define the noise margin of an inverter.

2.​ Identify the operating region of NMOS and PMOS in a CMOS inverter if Vin=Vdd/2 is
applied. Assume Vdd=5V.
3.​ State the condition required for one CMOS inverter to be symmetrical.
4.​ At which condition will one NMOS and PMOS conduct the same amount of current for
the same magnitude of terminal voltages?
5.​ Define rise and fall time in CMOS inverter
6.​ What is the purpose of using a super buffer?
7.​ What do you mean by short-circuit power dissipation in CMOS circuits?
8.​ For a combinational logic gate α = 0. 2, 𝐶𝐿 = 150 𝑓𝐹, 𝑉𝐷𝐷 = 2 𝑉, 𝑓𝑐𝑙𝑘 = 2 𝐺𝐻𝑧.
Calculate the switching power dissipation of the gate.

Descriptive type:

1.​ With a suitable sketch, describe the operation of the CMOS inverter. Also, highlight
different operating regions in the voltage transfer characteristics curve.
2.​ What do you mean by a symmetrical CMOS inverter? State the necessary conditions
required for symmetry.
3.​ Design one CMOS inverter by determining the ratio of the width of the NMOS and
PMOS transistor (Wn/Wp) to achieve a switching threshold voltage of 1.9V. The power
supply of the inverter is 3.3V, and other parameters related to NMOS and PMOS are:
μnCox=30μA/V2, VT0,n=0.7V and μpCox=10μA/V2, VT0,p=-0.6V. Assume channel
length L=500 nm for both transistors.
4.​ Discuss the CMOS inverter by drawing its VTC and derive the expression for its
switching power dissipation and switching threshold voltage for a symmetric inverter.
Find the switching threshold voltage if VT0n=|VT0p|=1.0V, VDD=5V. Given
μnCox=30μA/V2, and μpCox=10μA/V2.
5.​ Discuss different types of power dissipation that occur in CMOS circuits. Which
component is prominent during the switching operation?
6.​ What is a super buffer, and why is it used?
7.​ Estimate the average power dissipation of a CMOS inverter with supply voltage VDD =
1.8 V that operates at 240MHz and drives a load capacitance of 2.2pF.
8.​ One CMOS inverter’s DC characteristics (Vout vs Vin) show unit slope points at
Vin=1.7V and Vin=2.4V. If the supply voltage of the inverter is 5V then find out the
noise margin of the inverter.
9.​ For the circuit below, three CMOS inverters are connected in a cascade. The input ‘A’ to
the 1st inverter is logic-0. The inverter has VIH=2.9V, VIL=2.1V, and VDD=5V. During
operation, a noise signal is induced in the circuit node as shown in the figure and as a
result, effective node voltage reduces. With justification, find out the output ‘Y’ of the
 logic circuit when the magnitude of the noise signal is (I) 3.1V and (II)1.5V respectively.

10.​Consider the RC-tree network in the Figure, calculate the propagation delay at nodes 3
and 5, respectively.

11.​Consider a CMOS inverter with the following parameters:

Calculate the noise margins and the switching threshold of this CMOS inverter. The
power supply voltage is 1.2 V.

12.​ Consider the RC-equivalent delay model of the CMOS inverter. Calculate the rise and
𝑊𝑝 𝑊𝑛
fall times of the output voltage if the load capacitance 𝐶 = 1 𝑝𝐹 and
𝐿 𝐿𝑝
=2 𝐿𝑛
,
where 𝐿 = 𝐿 = 2λ and 𝑊 = 4λ.
𝑝 𝑛 𝑛