MODULE 2

Processor Design and Control Unit: Basic Processor Organization:

CPU structure and functions, Instruction format, types, and execution
cycle, RISC vs. CISC architectures, Register organization.
Control Unit Design: Hardwired control, Microprogrammed control,
Design of control unit, Control memory and address sequencing.
Instruction Set Architecture (ISA): Characteristics of instruction
sets, Addressing modes, Instruction types - Data transfer, arithmetic,
logical, control, I/O, Examples of typical instruction set architecture.

CPU (CENTRAL PROCESSING UNIT)

 The part of the computer that performs the bulk of data processing
operations is called the Central Processing Unit (CPU)
 It is the central component of a digital computer.
 Its purpose is to interpret instruction cycles received from memory and
perform arithmetic, logic and control operations with data stored in
internal register, memory words and I/O interface units.
 A CPU is usually divided into two parts
o processor unit (Register Unit and Arithmetic Logic Unit)
o control unit.

Processor Unit:
 The processor unit consists of arithmetic unit, logic unit, a number of
registers and internal buses that provides data path for transfer of
information between register and arithmetic logic unit.
 The block diagram of processor unit is shown in figure below where all
registers are connected through common buses.
  The registers communicate each other not only for direct data transfer but
also while performing various micro-operations.
 Here two sets of multiplexers select register which perform input data for
ALU.
 A decoder selects destination register by enabling its load input.
 The function select in ALU determines the particular operation that to be
performed.
 For an example to perform the operation: R3 R1 + R2
1. MUX A selector (SELA): to place the content of R1 into bus A.
2. 2.MUX B selector (SELB): to place the content of R2 into bus B.
3. 3.ALU operation selector (OPR): to provide arithmetic addition A
+ B.
4. 4.Decoder destination selector (SELD): to transfer the content of
the output bus into R3.
Control Unit

The control unit (CU) is a critical component of the CPU that directs the
operations of the processor. Here's a breakdown of its functionality based on the
description you provided:

Components of the Control Unit

1. Program Counter (PC):

o The program counter holds the address of the next instruction to be
fetched for execution.
2. Instruction Register (IR):
o The instruction register holds the instruction currently being
executed. It contains the opcode, which is essential for determining
which operation the CPU needs to perform.
3. Timing and Control Logic:
o This logic is responsible for generating the necessary signals to
control the execution flow. Depending on whether the control unit
is hardwired or micro-programmed, the control logic can function
in different ways:
 Hardwired Control Unit:
 Uses a fixed set of decoders and logic gates to
produce control signals. These signals tell the
processor what actions to take based on the current
instruction.
 Micro-programmed Control Unit:
 Uses a control memory (typically ROM or RAM) to
store microinstructions. Each microinstruction
specifies a sequence of operations and is fetched in
sequence, with control signals produced based on
the current instruction.

Roles of the Control Unit

The control unit's primary function is to interpret instructions and orchestrate the
necessary operations within the CPU. Here's how it works:

1. Interpreting Instructions:
o The CU decodes the opcode in the instruction register to
understand the operation that needs to be performed.
2. Directing Data Movement:
o It determines the movement of data between the ALU (Arithmetic
Logic Unit), memory, and registers. It ensures that data is properly
routed to the correct components for the operation.
3. Coordinating Operations:
o The control unit manages all activities of the processor, including:
 Interfacing with the ALU for computation tasks.
 Communicating with main memory for data fetching and
storing.
 Managing interactions with peripheral devices and storage
devices.
4. Handling System States:
o The CU ensures that the processor operates correctly by
monitoring system states, which include the status of the processor
flags (e.g., zero flag, carry flag, etc.) and triggering necessary
actions based on the current state of the system.
Inputs to the Control Unit

1. Flags:
o These flags (like zero, carry, overflow, etc.) hold information about
the result of the last ALU operation. They are used to make
decisions during program execution.
2. Clock:
o The clock signal synchronizes the operations of the processor,
ensuring that all micro-operations happen at specific time intervals
or clock cycles.
3. Instruction Register (IR):
o The opcode from the instruction register tells the control unit what
micro-operations to carry out during the execution cycle.
4. Control Signals from the Control Bus:
o These signals indicate external events like interrupts or I/O
operations, which can prompt the CU to take specific actions, such
as halting the CPU or acknowledging peripheral devices.

Outputs from the Control Unit

1. Control Signals within the Processor:

o These are signals that control the internal components of the CPU,
such as triggering data transfers between registers, activating ALU
operations, or setting flags.
2. Control Signals to the Control Bus:
o These signals are directed to external components like memory or
I/O devices, directing them on what actions to perform. For
example, the CU might generate a read or write signal to interact
with memory.

Summary of the CU's Functions:

 Input Analysis: The CU receives data like flags, the clock pulse, the
instruction register's opcode, and external control signals.
 Processing: Based on the input, the CU decodes the instruction and
orchestrates the sequence of micro-operations, interacting with the ALU,
registers, memory, and peripherals.
 Output Generation: The CU outputs control signals that ensure correct data
transfer and execution of tasks.

CPU Structure and Function

The Central Processing Unit (CPU) is the core component of a computer that
performs most of the processing inside. It executes instructions from a program,
making it the "brain" of the computer. The CPU's structure can be broken down
into several key components, and its functions involve a series of tasks to ensure
that instructions are processed and data is manipulated correctly. These tasks
include fetching instructions, interpreting instructions, fetching data, processing
data, and writing data.
Processor Organization

The CPU typically consists of the following main components:

1. Control Unit (CU):

o Role: Directs the operation of the processor by interpreting
instructions and coordinating the other components (ALU,
registers, memory).
2. Arithmetic and Logic Unit (ALU):
o Role: Performs mathematical, logical, and comparison operations
(e.g., addition, subtraction, AND, OR, etc.).
3. Registers:
o Role: Small, high-speed storage locations used to hold data and
instructions temporarily during processing. These can include the
Program Counter (PC), Accumulator (AC), Instruction Register
(IR), etc.
4. Clock:
o Role: Synchronizes the processor's operations by sending clock
pulses to various components, ensuring they work together in a
coordinated fashion.
5. Bus System (Data, Address, Control Buses):
o Role: These are communication pathways that transfer data,
addresses, and control signals between the CPU and other
components (such as memory and I/O devices).

Fig: The CPU with the System Bus

The following are the five critical functions that a CPU performs during the
execution of a program:

1. Fetch Instructions:

 Action: The CPU fetches the next instruction from memory (RAM). The
address of this instruction is stored in the Program Counter (PC).
 How It Works:
 o The PC provides the address of the next instruction to the memory
unit.
o The instruction is then fetched from memory and loaded into the
Instruction Register (IR) for decoding and execution.
o The Program Counter (PC) is incremented after the instruction is
fetched, so it points to the next instruction.

2. Interpret Instructions:

 Action: The CPU decodes the instruction to understand what action is

required.
 How It Works:
o The Instruction Register (IR) holds the fetched instruction, which
contains the opcode (operation code) and possibly an operand (data
or memory address).
o The control unit (CU) interprets the opcode and determines which
operation needs to be performed. This could involve arithmetic
operations, data transfer, or controlling other hardware
components.

3. Fetch Data:

 Action: The CPU fetches any data required for the operation (for example,
operands for arithmetic operations).
 How It Works:
o The data may be located in registers, main memory (RAM), or I/O
devices.
o If data is in memory, the CPU uses the Address Bus to get the
address of the data and fetches it through the Data Bus.

4. Process Data:

 Action: The CPU performs the actual operation on the fetched data (like
performing a calculation or logical comparison).
 How It Works:
o The Arithmetic and Logic Unit (ALU) performs the required
operations, such as addition, subtraction, multiplication, logical
comparisons, etc.
o The ALU may also involve shifting data, performing bitwise
operations, or other operations depending on the instruction.

5. Write Data:

 Action: The CPU writes the processed data back to memory or a register,
or it may output the data to an I/O device.
 How It Works:
o The Data Bus is used to send the results to either a register,
memory, or I/O port.
o If data is written back to memory, the address of the location is
specified by the Address Bus.

Summary of the Cycle:

The CPU follows an instruction cycle (also known as the fetch-decode-execute

cycle), which is broken down into several steps:
 1. Fetch: The CPU retrieves the instruction from memory.
2. Decode: The instruction is decoded to understand what needs to be done.
3. Fetch Data: If the instruction involves data, it fetches the necessary data
from memory or registers.
4. Execute: The CPU executes the operation on the data.
5. Write Data: The result is written back to memory or stored in a register.

This process repeats continuously, ensuring that the CPU can carry out a sequence
of tasks efficiently.

Fig: Internal Structure of the CPU

Instruction Format
Computers execute tasks based on a sequence of instructions. These instructions
are grouped into fields, each containing specific information that guides the CPU
in performing operations. The layout of these instruction bits is called an
instruction format. This format determines how the instruction is structured and
executed by the processor.
Definition of Instruction Format
An instruction format is a sequence of bits that defines the structure of a machine
language instruction. It consists of:
 Opcode (Operation Code): Specifies the operation to be executed.
 Operand: Represents the data or memory location involved in the
operation.
 Addressing Mode: Determines how the operand is interpreted (e.g., direct,
indirect, register addressing).
The instruction format influences the efficiency and complexity of the CPU’s
instruction set. The length of an instruction is typically maintained in multiples of
8 bits (1 byte).
Types of Instruction Formats
Based on the number of addresses present in an instruction, instruction formats
can be classified into four main types:
1. Zero (0) Address Instruction Format
 No address field is present in the instruction.
 Uses stack-based architecture for operations.
 Operands are implicitly on the stack (e.g., PUSH A, POP B).

Example:
 Assembly Language: PUSH A, PUSH B
 Stack Operation: TOS <- A, TOS <- B
2. One (1) Address Instruction Format
 Contains only one address field.
 One operand is stored in the accumulator, and the other in memory.
 Requires special instructions like LOAD (to fetch data) and STORE (to
save data).

Example:
 Assembly Language: LOAD C, ADD B, STORE T
 Register Operation: AC <- M[T], AC <- M[C]
3. Two (2) Address Instruction Format
 Contains two address fields.
 The result of the operation can be stored in a different location.
 Requires shorter assembly language instructions compared to three-
address formats.

Example:
 Assembly Language: MOV R1, A, ADD R1, B
 Register Operation: R1 <- M[A], R2 <- M[C]
4. Three (3) Address Instruction Format
 Contains three address fields.
 Requires shorter assembly instructions but more bits to store the
instruction.

Example:
 Assembly Language: ADD R1, A, B
 Register Operation: R1 <- M[A] + M[B]
Parts of an Instruction Format
Each instruction format consists of the following essential components:
1. Addressing Mode: Defines how an operand is accessed (e.g., direct,
indirect, register, or immediate addressing).
2. Operation Code (Opcode): Specifies the operation to be performed by the
processor.
3. Operand: Represents the data or memory address required for execution.
The number of operands varies based on the instruction format.

Instruction Execution Cycle

 Instruction Cycle A program that exists inside a computer's memory unit
consists of a series of instructions. The processor executes these instructions
through a cycle for each instruction.
 In a basic computer, each instruction cycle consists of the following phases:
o Instruction fetches: fetch instruction from memory
o Decode the instruction: what operation to be performed.

Read the effective address from memory

Execute the instruction

Registers Involved in Each Instruction Cycle:

 Memory address registers (MAR): It is connected to System Bus address lines.
It specifies the address of a read or write operation in memory. Memory
Buffer
 Register (MBR): It is connected to the data lines of the system bus.: It is
connected to the system bus Data Lines. It holds the memory value to be
stored, or the last value read from the memory.
 Program Counter (PC): Holds the address of the next instruction to be fetched.
 Instruction Register (IR): Holds the last instruction fetched.

Fetch cycle

The address of the next instruction to execute is in the Program Counter (PC) at
the beginning of the fetch cycle.
Step 1: The address in the program counter is transferred to the Memory Address
Register (MAR), as this is the only register that is connected to the system bus
address lines.
Step 2: The address in MAR is put on the address bus, now a Read order is
provided by the control unit on the control bus, and the result appears on the data
bus and is then copied into the memory buffer register. Program counter is
incremented by one, to get ready for the next instruction. These two acts can be
carried out concurrently to save time.
Step 3: The content of the MBR is moved to the instruction register (IR).

Instruction fetch cycle consist of four micro-operations:

T1: MAR ← PC
T2: MBR ← memory
PC ← PC + stepsize or length of instruction
T3: IR ←MBR

Decode instruction cycle

After an instruction is fetched, the next step is to get the required data (source
operand) for execution. In this case, indirect addressing is used, meaning the
instruction contains a reference to a memory location where the actual data is
stored. Other addressing modes could also be used, but here, indirect addressing is
applied. If the operand is stored in a register, no additional fetching is needed.
Once the instruction is executed, a similar process is followed to store the result
back into memory if necessary.
Microoperations take place:
T1: MAR ←IR (address)
T2: MBR ←Memory T3:
IR (address) ← (MBR(Address))

Step 1: The instruction address field is passed to the MAR. This is used to fetch
the operand 's address.
Step 2: The address field of the IR is updated from the MBR.
Step 3: The IR is now in the state. Now IR is ready for the execute cycle

Execute instruction Cycle

The initial three cycles (Fetch, Indirect, and Interrupt) are predictable and quick.
Each requires simple, small, and fixed micro-operation sequences. The same
micro-operation is repeated every time around in each event. Execute instruction
cycle is different from them. Like, there is N different series of micro-operations
that can occur for a computer with different N opcodes.
Example ADD R, X
T1: MAR ← (IR (address))
T2: MBR ← Memory
T3: R ← (R) + (MBR)
Step 1: The address portion of IR is loaded into the MAR.
Step 2: The address field of the IR is updated from the MBR, so the reference
memory location is read.
Step 3: Now, the contents of R and MBR are added by the ALU

RISC Processor v/s CISC Processor

RISC Processor
 RISC stands for Reduced Instruction Set Computer Processor, a
microprocessor architecture with a simple collection and highly customized
set of instructions.
 It is built to minimize the instruction execution time by optimizing and
limiting the number of instructions.
 It means each instruction cycle requires only one clock cycle, and each cycle
contains three parameters: fetch, decode and execute.
 The RISC processor is also used to perform various complex instructions by
combining them into simpler ones.
 RISC chips require several transistors, making it cheaper to design and reduce
the execution time for instruction.
Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC
processors, RISC-V.
Advantages of RISC Processor
1. The RISC processor's performance is better due to the simple and limited
number of the instruction set.
2. It requires several transistors that make it cheaper to design.
3. RISC allows the instruction to use free space on a microprocessor because
of its simplicity.
4. RISC processor is simpler than a CISC processor because of its simple and
quick design, and it can complete its work in one clock cycle.
Disadvantages of RISC Processor
1. The RISC processor's performance may vary according to the code
executed because subsequent instructions may depend on the previous
instruction for their execution in a cycle.
2. Programmers and compilers often use complex instructions.
3. RISC processors require very fast memory to save various instructions that
require a large collection of cache memory to respond to the instruction in
a short time.

RISC Architecture
It is a highly customized set of instructions used in portable devices due to system
reliability such as Apple iPod, mobiles/smartphones, Nintendo DS,
Features of RISC Processor
Some important features of RISC processors are:
1. One cycle execution time: For executing each instruction in a computer,
the RISC processors require one CPI (Clock per cycle). And each CPI
includes the fetch, decode and execute method applied in computer
instruction.
2. Pipelining technique: The pipelining technique is used in the RISC
processors to execute multiple parts or stages of instructions to perform
more efficiently.
3. A large number of registers: RISC processors are optimized with
multiple registers that can be used to store instruction and quickly respond
to the computer and minimize interaction with computer memory.
4. It supports a simple addressing mode and fixed length of instruction for
executing the pipeline.
5. It uses LOAD and STORE instruction to access the memory location.
6. Simple and limited instruction reduces the execution time of a process in a
RISC.
CISC Processor
 CISC (Complex Instruction Set Computer) is a microprocessor architecture
developed by Intel.
 It has a large collection of complex instructions ranging from simple to
specialized assembly-level instructions.
 Takes longer to execute instructions due to complex operations.
 Reduces the number of instructions in each program but ignores the number of
cycles per instruction.
 Emphasizes building complex instructions in hardware, as hardware is faster
than software.
 Slower than RISC but requires fewer instructions to perform tasks.
 Examples: VAX, AMD, Intel x86, System/360.
Characteristics of CISC Processor
Following are the main characteristics of the RISC processor:
 Shorter code length, requiring less RAM.
 Complex instructions may take multiple clock cycles to execute.
 Fewer instructions needed to write an application.
 Easier assembly language programming.
 Supports complex data structures and compilation of high-level languages.
 Has fewer registers (typically 5 to 20) and more addressing modes.
 Instructions can be larger than a single word.
 Focuses on hardware-based instruction execution for speed.

CISC Processors Architecture

The CISC architecture helps reduce program code by embedding multiple
operations on each program instruction, which makes the CISC processor more
complex. The CISC architecture-based computer is designed to decrease memory
costs because large programs or instruction required large memory space to store
the data, thus increasing the memory requirement, and a large collection of
memory increases the memory cost, which makes them more expensive.
Advantages of CISC Processors
1. The compiler requires little effort to translate high-level programs or
statement languages into assembly or machine language in CISC
processors.
2. The code length is quite short, which minimizes the memory requirement.
3. To store the instruction on each CISC, it requires very less RAM.
4. Execution of a single instruction requires several low-level tasks.
5. CISC creates a process to manage power usage that adjusts clock speed
and voltage.
6. It uses fewer instructions set to perform the same instruction as the RISC.
Disadvantages of CISC Processors
1. CISC chips are slower than RSIC chips to execute per instruction cycle on
each program.
2. The performance of the machine decreases due to the slowness of the
clock speed.
3. Executing the pipeline in the CISC processor makes it complicated to use.
4. The CISC chips require more transistors as compared to RISC design.
5. In CISC it uses only 20% of existing instructions in a programming event.

Difference between the RISC and CISC Processors

RISC CISC
It is a Reduced Instruction Set It is a Complex Instruction Set
Computer. Computer.
It emphasizes on software to optimize It emphasizes on hardware to optimize
the instruction set. the instruction set.
It is a hard-wired unit of programming Microprogramming unit in CISC
in the RISC Processor. Processor.
It requires multiple register sets to It requires a single register set to store
store the instruction. the instruction.
RISC has simple decoding of CISC has complex decoding of
instruction. instruction.
Uses of the pipeline are simple in Uses of the pipeline are difficult in
RISC. CISC.
 It uses a limited number of It uses a large number of instructions
instructions that requires less time to that requires more time to execute the
execute the instructions. instructions.
It uses LOAD and STORE that are It uses LOAD and STORE instruction
independent instructions in the in the memory-to-memory interaction
register-to-register a program's of a program.
interaction.
RISC has more transistors on memory CISC has transistors to store complex
registers. instructions.
The execution time of RISC is very The execution time of CISC is longer.
short.
RISC architecture can be used with CISC architecture can be used with
high-end applications like low-end applications like home
telecommunication, image processing, automation, security system, etc.
video processing, etc.
It has fixed format instruction. It has variable format instruction.
The program written for RISC Program written for CISC architecture
architecture needs to take more space tends to take less space in memory.
in memory.
Example of RISC: ARM, PA-RISC, Examples of CISC: VAX, Motorola
Power Architecture, Alpha, AVR, 68000 family, System/360, AMD and
ARC and the SPARC. the Intel x86 CPUs.

Register Organization
 Registers are temporary storage locations inside the CPU.
 A register is a very very fast memory that is built into the CPU.
 Registers are used to store data temporarily.
 Different processors have different register.
 Registers are normally measured by the number of bits they can hold, for
example, an 8-bit register means it can store 8 bits of data or a 32-bit register
means it can store 32 bits of data.

The basic computer has 8 registers.

The registers in the processor can be put in two categories:

1. User-visible registers
2. Control and status registers
User-visible registers
These registers help minimize memory access by keeping frequently used
values inside the CPU.
1. General-Purpose Registers
 These can hold both data and addresses.
 Can be used in various instructions for performing calculations, storing
values, or holding temporary data.
 Example: AX, BX, CX, DX in x86 processors.
2. Data Registers
 Specifically used to store data values.
 Cannot hold addresses or be used for calculations.
 Example: Accumulator (AC) stores results of arithmetic and logic
operations.
3. Address Registers
 Hold memory addresses used in instructions.
 Examples:
o Segment Pointer: Holds the base address of a memory segment.
o Index Register: Used in indexed addressing for efficient data
retrieval.
o Stack Pointer (SP): Points to the top of the stack and is used in
push/pop operations.
Control and Status Registers
These registers help the CPU manage execution flow and internal operations.
1. Program Counter (PC)
 Stores the address of the next instruction to be executed.
 Automatically increments after fetching an instruction.
2. Instruction Register (IR)
 Holds the current instruction being executed.
 The CPU decodes and processes the instruction stored here.
3. Memory Address Register (MAR)
 Stores the memory location of the data to be read or written.
 Works closely with the Memory Buffer Register (MBR).
4. Memory Buffer Register (MBR)
 Holds the actual data that is being transferred to/from memory.
 Acts as a temporary storage before data is moved to the CPU or memory.

Control unit design

The Control Unit (CU) is a part of the Central Processing Unit (CPU) that
manages and directs the operations of a computer. It does not process data but
ensures that all parts of the computer work together smoothly.
Key Points About the Control Unit:
 It is a part of the CPU and was introduced in the Von Neumann
Architecture by John von Neumann.
 It tells different computer components (memory, arithmetic/logic unit,
input/output devices) how to execute instructions.
 It fetches program instructions from main memory, stores them in the
instruction register, and generates control signals to execute them.
 It converts input information into control signals and sends them to the
processor, which then directs hardware operations.
  The design of the Control Unit depends on the CPU architecture, which
varies between manufacturers.
Examples of Devices That Use a Control Unit:
 Central Processing Units (CPUs)
 Graphics Processing Units (GPUs)
Functions of the Control Unit (CU):
1. Manages Data Movement – Directs the transfer of data within the
processor and between different components.
2. Interprets Instructions – Decodes commands received from memory to
determine what actions to perform.
3. Controls Data Flow – Ensures data moves correctly inside the processor.
4. Processes External Commands – Receives instructions and converts them
into a series of control signals.
5. Manages Execution Units – Coordinates ALU (Arithmetic Logic Unit),
data buffers, and registers for efficient processing.
6. Handles Multiple Tasks – Performs fetching, decoding, execution, and
storing of results.
7. Optimizes System Performance – Ensures all components work efficiently
together for smooth system operation.

Types of Control Unit

There are two types of control units:
 Hardwired
 Micro programmable control unit.

Hardwired Control Unit

The Hardwired Control Unit is a type of control unit in a computer system that
generates control signals through specially designed logical circuits. These
circuits are fixed in hardware, meaning any modification to the way signals are
generated requires physically changing the circuit structure.
Functioning of the Hardwired Control Unit:
1. Instruction Decoding:
o The operation code (opcode) of an instruction provides the basic
data required for generating control signals.
o The instruction decoder decodes the opcode using multiple
decoding circuits, each responsible for decoding different fields of
the instruction.
o Some output lines from the instruction decoder become active
based on the decoded instruction.
2. Control Signal Generation:
o The active output lines of the decoder are connected to a control
signal generator matrix, which produces control signals needed for
executing instructions.
o This matrix creates logical combinations using:
 Decoded signals from the instruction opcode.
 Outputs from another matrix responsible for generating
signals that define the control unit’s internal states.
 External processor signals like interrupts.
o These matrices function similarly to programmable logic arrays
(PLAs).
3. Timing and Execution Control:
o Control signals are generated throughout the instruction execution
cycle, not just at a single moment.
o The control unit organizes internal states to match the instruction
execution cycle.
o Some signals from the control signal generator matrix are sent back
as inputs to another matrix that generates the next control state.
o This matrix integrates feedback signals with timing signals, which
are generated using a quartz oscillator.
4. Instruction Execution Process:
o When a new instruction arrives, the control unit starts in the fetch
stage, where it retrieves the instruction.
o After decoding the instruction, the control unit moves into the
execution stage, maintaining this state as long as timing signals and
system conditions (such as flags and state information) remain
unchanged.
o If any of these signal’s change, the control unit transitions to a new
state accordingly.
5. Handling Interrupts and External Signals:
o If an external signal, such as an interrupt, appears, the control unit
transitions to an interrupt-handling state to process it.
o The computer’s flags and state variables determine the correct
control states for executing the instruction.
6. Fetching the Next Instruction:
 o The final states of an instruction execution cycle include steps to
fetch the next instruction:
 The program counter (PC) content is sent to the memory
address buffer register.
 The instruction is read into the instruction register (IR).
7. Handling the Stop Instruction:
o If the current instruction is a STOP instruction, meaning it marks
the end of program execution, the control unit moves to an
operating system state.
o In this state, the system waits for the next user command before
proceeding further.
Summary:
The hardwired control unit operates using fixed logical circuits to generate control
signals based on instruction decoding. It follows a structured sequence of states
during instruction execution, incorporating timing signals and external inputs. The
process ensures smooth transition between fetching, decoding, executing
instructions, and handling external interrupts. If the instruction is a stop command,
the control unit enters an idle state, waiting for user input.

Microprogrammed Control Unit

A Microprogrammed Control Unit differs from a Hardwired Control Unit
primarily due to the presence of a control store. This control store holds words
containing encoded control signals, which are necessary for executing
instructions. Instead of directly decoding the operation code (opcode) to generate
control signals immediately, the opcode provides the starting address of a
microprogram stored in the control store.
1. Single-Level Control Store
In a single-level control store, instruction execution follows these steps:
 The instruction opcode from the instruction register is sent to the control
store address register.
  Using this address, the first microinstruction of the corresponding
microprogram is fetched from the control store and placed in the
microinstruction register.
 This microinstruction contains:
o Encoded control signals stored in bit fields.
o A set of microinstruction field decoders that decode the control
signals.
o The address of the next microinstruction in the instruction's
microprogram.
o A control field responsible for directing the microinstruction
address generator to determine the next microinstruction address.
 The control field decides the addressing mode to be used for the next
microinstruction. If conditional addressing is used, this address is modified
based on processor condition flags, which store the status of computations
in the program.
 The final microinstruction in the instruction’s microprogram is responsible
for fetching the next instruction from the main memory and loading it into
the instruction register for execution.

2. Two-Level Control Store

In a two-level control store, an additional nano-instruction memory is included
alongside the microinstruction memory. The key differences are:
 Microinstructions do not directly contain encoded control signals. Instead,
their operation part contains the address of a word in the nano-instruction
memory.
 The nano-instruction memory holds all possible control signal
combinations used in microprograms. Each unique combination of control
signals is stored as a nano-instruction, which prevents redundant storage of
the same signals across multiple microinstructions.
 This design reduces memory usage, as microinstruction words can be
much shorter than in a single-level control store. Consequently, the total
control memory size is significantly smaller.
  The microinstruction memory mainly determines the sequence of
microinstructions, while the nano-instructions generate the actual control
signals.
 In nano-instructions, control signals are often encoded using a 1-bit per
signal method, meaning each signal is represented by a single bit,
eliminating the need for decoding.

Advantages of a Well-Designed Control Unit

1. Efficient instruction execution: Ensures instructions are processed quickly
with minimal delays.
2. Improved CPU performance: Enhances processing speed, reducing
bottlenecks in execution.
3. Support for complex instructions: Can handle multiple operations within a
single instruction.
4. Better power efficiency: Optimizes resource usage to reduce power
consumption.
5. Enhanced security features: Implements mechanisms to prevent
unauthorized access and errors.
6. Optimized parallel processing: Allows multiple instructions to be executed
simultaneously in modern multi-core processors.
7. Improved reliability: Detects and corrects potential execution errors.
8. Scalability: Can support higher computing demands by adjusting to newer
architectures.
9. Reduced latency: Minimizes the time taken between instruction fetching
and execution.
10. Better branch prediction: Predicts the next instruction to execute, reducing
delays in pipelines.
Disadvantages of a Poorly-Designed Control Unit
1. Reduced CPU performance: Inefficient control can slow down execution.
2. Increased complexity and power consumption: Poor design can lead to
excessive power usage and unnecessary operations.
 3. Limited instruction handling: May not support modern instruction sets
efficiently.
4. Scalability issues: May not adapt well to growing computational needs.
5. Security vulnerabilities: Can introduce potential risks such as unauthorized
access and execution errors.
6. Pipeline inefficiencies: Poor handling of instruction pipelines can lead to
delays and bottlenecks.
7. Higher cost: Complex designs may require additional resources, increasing
manufacturing costs.
8. Interrupt mismanagement: Poorly managed interrupts can lead to
inefficient execution and delays.
9. Inefficient use of registers and memory: Leads to resource wastage and
suboptimal performance.
10. Limited support for parallel processing: Reduces the ability of the CPU to
execute multiple instructions at once.

Control Memory
 The control function that specifies a microoperation is called as control
variable.
 When control variable is in one binary state, the corresponding
microoperation is executed. For the other binary state the state of registers
does not change.
 The active state of a control variable may be either 1 state or the 0 state,
depending on the application.
 For bus-organized systems the control signals that specify microoperations
are groups of bits that select the paths in multiplexers, decoders, and
arithmetic logic units.
 Control Word: The control variables at any given time can be represented
by a string of 1’s and 0's called a control word.
 All control words can be programmed to perform various operations on
the components of the system.
 Microprogram control unit: A control unit whose binary control variables
are stored in memory is called a microprogram control unit.
 The control word in control memory contains within it a microinstruction.
 The microinstruction specifies one or more micro-operations for the
system.
 A sequence of microinstructions constitutes a microprogram.
 The control unit consists of control memory used to store the
microprogram.
 Control memory is a permanent i.e., read only memory (ROM).
 The general configuration of a micro-programmed control unit
organization is shown as block diagram below.
 The control memory is ROM so all control information is permanently stored.
 The control memory address register (CAR) specifies the address of the
microinstruction and the control data register (CDR) holds the
microinstruction read from memory.
 The next address generator is sometimes called a microprogram sequencer. It
is used to generate the next micro instruction address.
 The location of the next microinstruction may be the one next in sequence or it
may be located somewhere else in the control memory.
 So, it is necessary to use some bits of the present microinstruction to control
the generation of the address of the microinstruction.
 Sometimes the next address may also be a function of external input
conditions.
 The control data register holds the present microinstruction while next address
is computed and read from memory. The data register is times called a
pipeline register.
 A computer with a microprogrammed control unit will have two separate
memories: a main memory and a control memory
 The microprogram consists of microinstructions that specify various internal
control signals for execution of register microoperations
 These microinstructions generate the microoperations to:
o fetch the instruction from main memory
o evaluate the effective address
o execute the operation
o return control to the fetch phase for the next instruction

Address Sequencing
 Microinstructions are stored in control memory in groups, with each group
specifying a routine.
 Each computer instruction has its own microprogram routine to generate the
microoperations.
 The hardware that controls the address sequencing of the control memory
must be capable of sequencing the microinstructions within a routine and be
able to branch from one routine to another
 Steps the control must undergo during the execution of a single computer
instruction:
o Load an initial address into the CAR when power is turned on in the
computer. This address is usually the address of the first
microinstruction that activates the instruction fetch routine – IR holds
instruction
o The control memory then goes through the routine to determine the
effective address of the operand – AR holds operand address
o The next step is to generate the microoperations that execute the
instruction by considering the opcode and applying a mapping process.
 The transformation of the instruction code bits to an address in
control memory where the routine of instruction located is
referred to as mapping process.
o After execution, control must return to the fetch routine by executing
an unconditional branch
 In brief the address sequencing capabilities required in a control memory are:
o Incrementing of the control address register.
o Unconditional branch or conditional branch, depending on status bit
conditions.
o A mapping process from the bits of the instruction to an address for
control memory.
 o A facility for subroutine call and return.
 The below figure shows a block diagram of a control memory and the
associated hardware needed for selecting the next microinstruction address.


 The microinstruction in control memory contains a set of bits to initiate

microoperations in computer registers and other bits to specify the method by
which the next address is obtained.
 In the figure four different paths form which the control address register
(CAR) receives the address.
o The incrementer increments the content of the control register address
register by one, to select the next microinstruction in sequence.
o Branching is achieved by specifying the branch address in one of the
fields of the microinstruction.
o Conditional branching is obtained by using part of the microinstruction
to select a specific status bit in order to determine its condition.
o An external address is transferred into control memory via a mapping
logic circuit.
o The return address for a subroutine is stored in a special register, that
value is used when the micoprogram wishes to return from the
subroutine.

Conditional Branching
 Conditional branching is obtained by using part of the microinstruction to
select a specific status bit in order to determine its condition.
 The status conditions are special bits in the system that provide parameter
information such as the carry-out of an adder, the sign bit of a number, the
mode bits of an instruction, and i/o status conditions.
 The status bits, together with the field in the microinstruction that specifies a
branch address, control the branch logic.
 The branch logic tests the condition, if met then branches, otherwise,
increments the CAR.
 If there are 8 status bit conditions, then 3 bits in the microinstruction are used
to specify the condition and provide the selection variables for the multiplexer.
 For unconditional branching, fix the value of one status bit to be one load the
branch address from control memory into the CAR.
Mapping of Instruction
 A special type of branch exists when a microinstruction specifies a branch to
the first word in control memory where a microprogram routine is located.
 The status bits for this type of branch are the bits in the opcode.
 Assume an opcode of four bits and a control memory of 128 locations. The
mapping process converts the 4-bit opcode to a 7-bit address for control
memory shown in below figure.

 Mapping consists of placing a 0 in the most significant bit of the address,

transferring the four operation code bits, and clearing the two least significant
bits of the control address register.
 This provides for each computer instruction a microprogram routine with a
capacity of four microinstructions.
Subroutines
 Subroutines are programs that are used by other routines to accomplish a
particular task and can be called from any point within the main body of the
microprogram.
 Frequently many microprograms contain identical section of code. 
Microinstructions can be saved by employing subroutines that use common
sections of microcode.
 Microprograms that use subroutines must have a provision for storing the
return address during a subroutine call and restoring the address during a
subroutine return.
 A subroutine register is used as the source and destination for the addresses

Instruction Set Architecture (ISA)

 An Instruction Set Architecture (ISA) defines the set of basic operations that a
computer must support.
 This includes the functional definition of operations and precise descriptions
of how to invoke and access them.
 An ISA is independent from microarchitecture, which refers to the
implementation of an ISA in a processor.
 A single ISA can have different microarchitecture implementations, meaning
multiple processors can use the same ISA but have different designs.
o Typically, an ISA includes instructions for the following operations:
o Data handling and memory operations (e.g., load, store).
o Arithmetic and logic operations (e.g., addition, subtraction, AND,
OR).
o Control flow operations (e.g., jump, call, return).
o Coprocessor instructions (for specialized processing, such as floating-
point operations).
 An ISA also defines the maximum bit length for all instructions.
 It also specifies how an instruction is encoded, determining the format and
structure of machine instructions.
 The definition of an ISA allows hardware and software development to be
separated.
 This enables a company to develop hardware, while multiple other companies
can develop software, knowing that it will run on that hardware.
 There are two major classifications of ISA:
 CISC (Complex Instruction Set Computer)
o Has a large number of complex instructions.
o Uses variable-length instruction formats.
 RISC (Reduced Instruction Set Computer)
o Has a smaller set of simple instructions.
o Uses fixed-length instructions, making execution more efficient.

Characteristics Of Instruction Set

1. Operand Storage: Specifies where operands (data) are stored (e.g.,
registers, memory).
2. Number of Explicit Operands: Defines the number of operands an
instruction can have (0, 1, 2, or 3).
3. Operand Types: Includes data types such as integer, floating point,
characters, and addresses.
4. Instruction Format: Determines the structure of machine instructions,
including opcode and operand fields.
5. Addressing Modes: Specifies how operands are accessed (registers,
memory, or immediate values).
6. Instruction Types: Categories like data transfer, arithmetic, logical,
control, and I/O instructions.
7. Instruction Length: Can be fixed-length (RISC) or variable-length (CISC).

Addressing Modes
Instruction Types
Instruction types in computer architecture can be classified into several categories
based on the operation they perform. Here's a breakdown of each:
1. Data Transfer Instructions:
o These instructions move data between registers, memory, and I/O
devices.
o Examples include:
 MOV: Move data from one location to another (e.g., from a
register to memory).
 PUSH/POP: Push data onto the stack or pop data from the
stack.
 LOAD/STORE: Load data from memory into a register or
store data from a register into memory.
2. Arithmetic Instructions:
o These instructions perform basic arithmetic operations like
addition, subtraction, multiplication, and division.
o Examples include:
 ADD: Add two operands.
 SUB: Subtract one operand from another.
 MUL: Multiply two operands.
 DIV: Divide one operand by another.

3. Logical Instructions:
o These instructions perform logical operations, typically bitwise, on
data.
o Examples include:
 AND: Perform a bitwise AND between two operands.
 OR: Perform a bitwise OR between two operands.
 XOR: Perform a bitwise exclusive OR between two
operands.
 NOT: Perform a bitwise NOT (invert all bits of an
operand).

4. Control Instructions:
o These instructions alter the sequence of execution in a program,
usually through branching or loops.
o Examples include:
 JUMP (JMP): Jump to another part of the program.
 CALL: Call a function or subroutine.
 RET: Return from a function or subroutine.
 NOP (No Operation): A placeholder instruction that does
nothing (used for timing or debugging).
 5. Input/Output (I/O) Instructions:
o These instructions are responsible for data transfer between the
processor and external devices (like keyboards, displays, or disks).
o Examples include:
 IN: Read data from an input device or port.
 OUT: Write data to an output device or port.
 READ/WRITE: Instructions for more complex I/O
operations, such as reading from or writing to a file or a
network socket.

Each of these instruction types plays a vital role in enabling the processor to
perform a wide range of tasks and interact with various hardware components.

Example of typical ISA

Example 1: Adding Two Numbers and Storing the Result

LOAD R1, 1000 ; Load value from memory address 1000 into R1
LOAD R2, 1004 ; Load value from memory address 1004 into R2
ADD R3, R1, R2 ; R3 = R1 + R2
STORE R3, 2000 ; Store result in memory address 2000
HALT ; Stop execution

Example 2: Checking if a Number is Even or Odd

IN R1, PORT1 ; Read number from input

AND R2, R1, #1 ; Check last bit (R2 = R1 AND 1)
BEQ R2, #0, EVEN ; If R2 == 0, jump to EVEN label
PRINT "Odd" ; Print "Odd" if not even
JMP END ; Jump to END
EVEN: PRINT "Even" ; Print "Even"
END: HALT ; Stop execution