SRV05-4

ESD Protection Diode Array

Low Clamping Voltage
The SRV05−4MR6 surge protection is designed to protect high
speed data lines from ESD, EFT, and lighting.

Features www.onsemi.com
• Protects 4 I/O Lines
• Low Working Voltage: 5 V LOW CAPACITANCE
• Low Clamping Voltage SURGE PROTECTION ARRAY
• Low Capacitance (<5 pF) for High Speed Interfaces 300 WATTS PEAK POWER
• Transient Protection for High Speed Lines to: 6 VOLTS
IEC61000−4−2 (ESD) ±15 kV (air), ±8 kV (contact)
PIN CONFIGURATION
IEC61000−4−4 (EFT) 40 A AND SCHEMATIC
IEC61000−4−5 (Lightning) 12 A
• TSOP−6 is Footprint Compatible with SOT−23 6 Lead,
I/O 1 6 I/O
SC−59 6 Lead and SC−74
• UL Flammability Rating of 94 V−0
VN 2 5 VP
• This is a Pb−Free Device

Typical Applications I/O 3 4 I/O

• High Speed Communication Line Protection
• USB 1.1 and 2.0 Power and Data Line Protection
6
• Digital Video Interface (DVI)
• Monitors and Flat Panel Displays
1
TSOP−6
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
CASE 318G
Rating Symbol Value Unit PLASTIC
Peak Power Dissipation Ppk 300 W
8 x 20 ms @ TA = 25°C (Note 1) MARKING DIAGRAM
Operating Junction Temperature Range TJ −55 to +125 °C
Storage Temperature Range Tstg −55 to +150 °C
63 G
M

Lead Solder Temperature − TL 260 °C G

Maximum (10 Seconds)

Human Body Model (HBM) ESD 16000 V

Machine Model (MM) 400 63 = Specific Device Code
IEC 61000−4−2 Air (ESD) 30000 M = Date Code
IEC 61000−4−2 Contact (ESD) 30000 G = Pb−Free Package
(Note: Microdot may be in either location)
IEC 61000−4−4 (5/50 ns) EFT 40 A
*Date Code orientation may vary
IEC 61000−4−5 (8 x 20 ms) − 12 A depending upon manufacturing location.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected. ORDERING INFORMATION
1. Non−repetitive current pulse per Figure 5 (Pin 5 to Pin 2)
Device Package Shipping
See Application Note AND8308/D for further description of
survivability specs. SRV05−4MR6T1G TSOP−6 3000/Tape & Reel
(Pb−Free)

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2011 1 Publication Order Number:

November, 2017 − Rev. 3 SRV05−4/D
 SRV05−4

ELECTRICAL CHARACTERISTICS I
(TA = 25°C unless otherwise noted)
IF
Symbol Parameter
IPP Maximum Reverse Peak Pulse Current
VC Clamping Voltage @ IPP
VRWM Working Peak Reverse Voltage VC VBR VRWM
V
IR Maximum Reverse Leakage Current @ VRWM IR VF
IT
VBR Breakdown Voltage @ IT
IT Test Current
IF Forward Current
IPP
VF Forward Voltage @ IF
Ppk Peak Power Dissipation
C Capacitance @ VR = 0 and f = 1.0 MHz
Uni−Directional

*See Application Note AND8308/D for detailed explanations of

datasheet parameters.

ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise specified)

Parameter Symbol Conditions Min Typ Max Unit
Reverse Working Voltage VRWM (Note 2) 5.0 V
Breakdown Voltage VBR IT=1 mA, (Note 3) 6.0 V
Reverse Leakage Current IR VRWM = 5 V 5.0 mA
Clamping Voltage VC IPP = 1 A (Note 4) 12.5 V
Clamping Voltage VC IPP = 5 A (Note 4) 17.5 V
Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins and GND 3.0 5.0 pF
Junction Capacitance CJ VR = 0 V, f=1 MHz between I/O Pins 1.5 3.0 pF
Clamping Voltage VC Per IEC 61000−4−2 (Note 5) Figure 1 and 2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Surge protection devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater
than the DC or continuous peak operating voltage level.
3. VBR is measured at pulse test current IT.
4. Non−repetitive current pulse per Figure 5 (Any I/O Pin to Ground)
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.

Figure 1. ESD Clamping Voltage Screenshot Figure 2. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2 Negative 8 kV Contact per IEC61000−4−2

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 SRV05−4

IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
First Peak
Test Volt- Current Current at Current at 100%
Level age (kV) (A) 30 ns (A) 60 ns (A) 90%
1 2 7.5 4 2
2 4 15 8 4 I @ 30 ns
3 6 22.5 12 6
4 8 30 16 8 I @ 60 ns

10%

tP = 0.7 ns to 1 ns

Figure 3. IEC61000−4−2 Spec

Device
Under
ESD Gun Oscilloscope
Test

50 W
50 W
Cable

Figure 4. Diagram of ESD Test Setup

The following is taken from Application Note systems such as cell phones or laptop computers it is not
AND8308/D − Interpretation of Datasheet Parameters clearly defined in the spec how to specify a clamping voltage
for ESD Devices. at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the protection diode over the time domain of an ESD pulse in the
voltage that an IC will be exposed to during an ESD event form of an oscilloscope screenshot, which can be found on
to as low a voltage as possible. The ESD clamping voltage the datasheets for all ESD protection diodes. For more
is the voltage drop across the ESD protection diode during information on how ON Semiconductor creates these
an ESD event per the IEC61000−4−2 waveform. Since the screenshots and how to interpret them please refer to
IEC61000−4−2 was written as a pass/fail spec for larger AND8307/D.

100
tr PEAK VALUE IRSM @ 8 ms
90
% OF PEAK PULSE CURRENT

80 PULSE WIDTH (tP) IS DEFINED

AS THAT POINT WHERE THE
70 PEAK CURRENT DECAY = 8 ms
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0 20 40 60 80
t, TIME (ms)
Figure 5. 8 x 20 ms Pulse Waveform

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 SRV05−4

TYPICAL PERFORMANCE CURVES

(TJ = 25°C unless otherwise noted)

5.0 30
4.5
JUNCTION CAPACITANCE (pF)

25
4.0

CLAMPING VOLTAGE (V)

3.5
20
3.0 I/O−Ground
2.5 15
2.0
I/O lines 10
1.5
1.0
5
0.5
0.0 0
0 1 2 3 4 5 0 2 4 6 8 10 12
VBR, REVERSE VOLTAGE (V) PEAK PULSE CURRENT (A)
Figure 6. Junction Capacitance vs Reverse Voltage Figure 7. Clamping Voltage vs. Peak Pulse Current
(8 x 20 ms Waveform)

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 SRV05−4

APPLICATIONS INFORMATION

The new SRV05−4MR6 is a low capacitance surge Option 2

protection diode array designed to protect sensitive Protection of four data lines with bias and power supply
electronics such as communications systems, computers, isolation resistor.
and computer peripherals against damage due to ESD events
or transient overvoltage conditions. Because of its low I/O 1
capacitance, it can be used in high speed I/O data lines. The I/O 2
integrated design of the SRV05−4MR6 offers surge rated, VCC
low capacitance steering diodes and a surge protection diode 1 6
integrated in a single package (TSOP−6). If a transient 10 k
condition occurs, the steering diodes will drive the transient 2 5
to the positive rail of the power supply or to ground. The
surge protection device protects the power line against 3 4
overvoltage conditions to avoid damage to the power supply
and any downstream components. I/O 3
I/O 4
SRV05−4MR6 Configuration Options
The SRV05−4MR6 is able to protect up to four data lines The SRV05−4MR6 can be isolated from the power supply
against transient overvoltage conditions by driving them to by connecting a series resistor between pin 5 and VCC. A
a fixed reference point for clamping purposes. The steering 10 kW resistor is recommended for this application. This
diodes will be forward biased whenever the voltage on the will maintain a bias on the internal surge protection and
protected line exceeds the reference voltage (Vf or VCC + steering diodes, reducing their capacitance.
Vf). The diodes will force the transient current to bypass the
sensitive circuit. Option 3
Data lines are connected at pins 1, 3, 4 and 6. The negative Protection of four data lines using the internal surge
reference is connected at pin 2. These pins must be protection diode as reference.
connected directly to ground by using a ground plane to
I/O 1
minimize the PCB’s ground inductance. It is very important
I/O 2
to reduce the PCB trace lengths as much as possible to
minimize parasitic inductances.
1 6
Option 1
Protection of four data lines and the power supply using 2 5 NC
VCC as reference.
3 4
I/O 1
I/O 2 I/O 3
I/O 4

1 6 In applications lacking a positive supply reference or

those cases in which a fully isolated power supply is
2 5 VCC required, the internal surge protection can be used as the
reference. For these applications, pin 5 is not connected. In
3 4 this configuration, the steering diodes will conduct
I/O 3
whenever the voltage on the protected line exceeds the
working voltage of the surge protection plus one diode drop
I/O 4
(Vc = Vf + VRWM).
For this configuration, connect pin 5 directly to the
positive supply rail (VCC), the data lines are referenced to ESD Protection of Power Supply Lines
the supply voltage. The internal surge protection diode When using diodes for data line protection, referencing to
prevents overvoltage on the supply rail. Biasing of the a supply rail provides advantages. Biasing the diodes
steering diodes reduces their capacitance. reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:

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 SRV05−4

Power
Even with good board layout, some disadvantages are still
Supply IESDpos present when discrete diodes are used to suppress ESD
VCC events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
D1 IESDpos therefore higher capacitance. This capacitance becomes
Protected Data Line IESDneg problematic as transmission frequencies increase. Reducing
Device capacitance generally requires reducing die size. These
D2
small die will have higher forward voltage characteristics at
IESDneg VF + VCC typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
−VF
The ON Semiconductor SRV05−4MR6 was developed to
Looking at the figure above, it can be seen that when a overcome the disadvantages encountered when using
positive ESD condition occurs, diode D1 will be forward discrete diodes for ESD protection. This device integrates a
biased while diode D2 will be forward biased when a surge protection diode within a network of steering diodes.
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
D1 D3 D5 D7
For positive pulse conditions:
Vc = VCC + VfD1
For negative pulse conditions:
Vc = −VfD2 D2 D4 D6 D8
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
0
Power Figure 8. SRV05−4MR6 Equivalent Circuit
Supply IESDpos
During an ESD condition, the ESD current will be driven
VCC
to ground through the surge protection diode as shown
D1 IESDpos below.
Protected IESDneg
Device
Data Line
Power
D2 VC = VCC + Vf + (L diESD/dt) Supply
IESDneg
VCC

D1 IESDpos

VC = −Vf − (L diESD/dt) Protected

An approximation of the clamping voltage for these fast Device
Data Line
transients would be: D2
For positive pulse conditions:
Vc = VCC + Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L diESD/dt)
As shown in the formulas, the clamping voltage (Vc) not The resulting clamping voltage on the protected IC will
only depends on the Vf of the steering diodes but also on the be: Vc = VF + VRWM.
L diESD/dt factor. A relatively small trace inductance can The clamping voltage of the surge protection diode is
result in hundreds of volts appearing on the supply rail. This provided in Figure 7 and depends on the magnitude of the
endangers both the power supply and anything attached to ESD current. The steering diodes are fast switching devices
that rail. This highlights the importance of good board with unique forward voltage and low capacitance
layout. Taking care to minimize the effects of parasitic characteristics.
inductance will provide significant benefits in transient
immunity.

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 SRV05−4

TYPICAL APPLICATIONS

UPSTREAM
USB PORT

VBUS
VBUS
VBUS
RT VBUS
D+ D+
RT DOWNSTREAM
D− D− USB PORT
VBUS USB VBUS
GND Controller SRV05−4MR6
GND
CT CT

VBUS

VBUS
NUP2201DT1 RT
D+ DOWNSTREAM
RT USB PORT
D−
GND
CT CT

Figure 9. ESD Protection for USB Port

RJ45
Connector

TX+ TX+

TX−
TX−
Coupling
PHY Transformers
Ethernet RX+
RX+
(10/100)

RX−

RX−

SRV05−4MR6
VCC

GND
N/C N/C

Figure 10. Protection for Ethernet 10/100 (Differential mode)

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 SRV05−4

R1
RTIP

R3
R2
RRING
T1
VCC

T1/E1
TRANCEIVER
SRV05−4MR6

R4
TTIP

R5
TRING
T2

Figure 11. TI/E1 Interface Protection

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 SRV05−4

PACKAGE DIMENSIONS

TSOP−6
CASE 318G−02
ISSUE V

NOTES:
D 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
H 2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM

ÉÉÉ
LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL.
6 5 4 L2 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR

ÉÉÉ
GAUGE
E1 E PLANE GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D
AND E1 ARE DETERMINED AT DATUM H.
1 2 3 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE.
L
MILLIMETERS
NOTE 5
M C SEATING
b PLANE DIM MIN NOM MAX

e DETAIL Z A 0.90 1.00 1.10

A1 0.01 0.06 0.10
b 0.25 0.38 0.50
c 0.10 0.18 0.26
D 2.90 3.00 3.10
c E 2.50 2.75 3.00
0.05 A E1 1.30 1.50 1.70
e 0.85 0.95 1.05
L 0.20 0.40 0.60
A1 L2 0.25 BSC
DETAIL Z
M 0° − 10°

RECOMMENDED
SOLDERING FOOTPRINT*
6X
0.60

3.20 6X
0.95

0.95
PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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9