Solution Manual For Fundamentals of Logic Design 7th Edition by Roth - Full Book Is Now Available For Download
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and applications as well as providing help with some of the more difficult topics. Since all
of the units have study guides, it would be possible to assign some of the easier topics for
self-study and devote the lectures to the more difficult topics.
2
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hardware description language. These units may be omitted if desired since no other units depend
on them.
Sequential circuits are given proper emphasis, with over half of the text devoted to this
subject. The pedagogical strategy the text uses in teaching sequential circuits has proven to be very
effective. The concepts of state, next state, etc. are first introduced for individual flip-flops, next
for counters, then for sequential circuits with inputs, and finally for more abstract sequential circuit
models. The use of timing charts, a subject neglected by many texts, is taught both because it is
a practical tool widely used by logic design engineers and because it aids in the understanding of
sequential circuit behavior.
The most important and often most difficult part of sequential circuit design is formulating
the state table or graph from the problem statement, but most texts devote only a few paragraphs
to this subject because there is no algorithm. This text devotes a full unit to the subject, presents
guidelines for deriving state tables and graphs, and provides programmed exercises that help the
student learn this material. Most of the material in the text is treated in a fairly conventional manner
with the following exceptions:
(1) The diagonal form of the 5-variable Karnaugh map is introduced in Unit 5. (We find
that students make fewer mistakes when using the diagonal form of 5-variable map in
comparison with the side-by-side form.) Unit 5 also presents a simple algorithm for finding
all essential prime implicants from a Karnaugh map.
(2) Both the state graph approach (Unit 18) and the SM chart approach (Unit 19) for designing
sequential control circuits are presented.
(3) The introduction to the VHDL hardware description language in Units 10, 17, and 20
emphasizes the relation between the VHDL code and the actual hardware.
The PSI method of instruction and its implementation are described in detail in the following
references:
1. Keller, Fred S. and J. Gilmour Sherman, The Keller Plan Handbook, W. A. Benjamin, Inc.,
1974.
2. Sherman, J.G., ed., Personalized System of Instruction: 41 Germinal Papers, W. A.
Benjamin, Inc., 1974.
3. Roth, C. H., The Personalized System of Instruction – 1962 to 1998, presented at the 1999
ASEE Annual Conference. (Go to http://search.asee.org and search under Conference
Papers for “The Personalized System of Instruction”.)
Results of applying PSI to a first course in logic design of digital systems are described in
Roth, C.H., Continuing Effectiveness of Personalized Self-Paced Instruction in Digital Systems
Engineering, Engineering Education, Vol. 63, No. 6, March 1973.
The instructor in charge of a self-paced course will serve as course manager in addition to
his role in the classroom. For a small class, he may spend a good part of his time acting as proctor
in the classroom, but as class size increases he will have to devote more of his time to supervision
of course activities and less time to individual interaction with students. In his managerial role, the
instructor is responsible for organizing the course, selection and training of proctors, supervision
of proctors, and monitoring of student progress. The proctors play an important role in the success
of a self-paced course, and therefore their selection, training, and supervision is very important.
After an initial session to discuss proper ways of grading readiness tests and interacting with
students, weekly proctor meetings to discuss course procedures and problems may be appropriate.
A progress chart showing the units completed by each student is very helpful in
monitoring student progress through the course. The instructor may wish to have individual
conferences with students who fall too far behind. The instructor needs to be available in the
classroom to answer individual student questions and to assist with grading of readiness tests
as needed. He should make a special point to speak with the weak or slow students and give
them a word of encouragement. From time to time he may need to settle differences which arise
between proctors and students.
Various strategies for organizing a PSI course are described in the Keller Plan
Handbook. The procedures previously used for operating the self-paced digital logic course
at the University of Texas are described in “Unit 0”, which is available from Prof. Charles H.
Roth, [email protected]. At the first class meeting, we handed out a copy of Unit 0. The
students were asked to read through Unit 0 and take a short test on the course procedures.
This test was immediately evaluated so that the student could complete Unit 0 before the
end of the first class period. In this way, the student was exposed to the basic way the course
operated and was ready to proceed immediately with Unit 1 in the textbook.
During a typical class period, some of the students spent their time studying but most
of the students came prepared to take a unit test. At the beginning of the period, the instructor
or a proctor was available to answer student questions on an individual basis. Later in the
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period, most of the time was spent evaluating unit tests. We found that a standard 50 minute
class period was not long enough for a PSI session. We usually scheduled sessions of 1½ or
2 hours or longer depending on class size. This allowed adequate time for students to have
their questions answered, take a unit test, and have their tests graded. Interactive grading of
the tests with the student present is an important part of the PSI system and adequate time must
be allowed for this activity. If you have a large number of students and proctors, you may
wish to prepare a manual for guidance of your proctors. The procedures that we used for
evaluating unit tests are described in a Proctor’s Manual, which can be obtained by writing
to Professor Charles H. Roth.
SimUaid provides an easy way for students to test their logic designs by simulating them.
We first introduce SimUaid in Unit 4, where we ask the students to design a simple logic circuit such
as problem 4.13 or 4.14, and simulate it. SimUaid is easy to learn, and it is highly interactive so that
students can flip a simulated switch and immediately observe the result. In Unit 8, students design a
multiple-output combinational logic circuit using NAND and NOR gates and test its operation using
SimUaid. Students can use the simulator to help them understand the operation of latches and flip-flops
in Unit 11. In Unit 12, we ask them to design a counter and simulate it (one part of problem 12.10). In
Unit 16, students use SimUaid to test their sequential circuit designs. They can also generate VHDL
code from their SimUaid circuit, synthesize it, and download it to a circuit board for hardware testing.
In Unit 18, students can use the advanced features of SimUaid to simulate a multiplier or divider
controlled by a state machine.
LogicAid provides an easy way to introduce students to the use of the computer in the logic
design process. It enables them to solve larger, more practical design problems than they could by
hand. They can also use LogicAid to verify solutions that they have worked out by hand. Instructors
can use the program for grading homework and quizzes. We first introduce LogicAid in Unit 5. The
program has a Karnaugh Map Tutorial mode that is very useful in teaching students to solve Karnaugh
map problems. This tutorial mode helps students learn to derive minimum solutions from a Karnaugh
map by informing them at each step whether that step is correct or not. It also forces them to choose
essential prime implicants first. When in the KMap tutor mode, LogicAid prints “KMT” at the top of
each output page, so you can check to see if the problems were actually solved in the tutorial mode.
Students can use LogicAid to help them solve design problems in Units 8, 16, 18, 19 and other
units. For designing sequential circuits, they can input a state graph, convert it to a state table, reduce
the state table, make a state assignment, and derive minimized logic equations for outputs and flip-flop
inputs.
The LogicAid State Table Checker is useful for Units 14 and 16, and for other units in which
students construct state tables. It allows students to check their solutions without revealing the correct
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answers. If the solution is wrong, the program displays a short input sequence for which the student’s
table fails. The LogicAid folder on the CD contains encoded copies of solutions for most of the state
graph problems in Fundamentals of Logic Design, 7th Ed. If you wish to create a password-protected
solution file for other state table problems, enter the state table into LogicAid, syntax check it, and
then hold down the Ctrl key while you select Save As on the file menu. The Partial Graph Checker
serves as a state graph tutor that allows a student to check his work at each step while constructing
a state graph. If the student makes a mistake, it provides feedback so that the student can correct his
answer. The partial graph checker works with any state graph problem for which an encoded state table
solution file is provided.
The DirectVHDL simulator helps students learn VHDL syntax because it provides immediate
visual feedback when they make mistakes. Our students use it for simulating VHDL code in Units 10,
17, and 20. Students can simulate and debug their code at home and then bring the code into lab for
synthesis and hardware testing.
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6
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Unit 1 Solutions
II. SOLUTIONS TO HOMEWORK PROBLEMS
Unit 1 Problem Solutions
1.1 (a) 757.2510 1.1 (b) 123.1710
16 | 757 0.25 16 | 123 0.17
16 | 47 r5 16 16 | 7 r11 16
16 | 2 r15=F16 (4).00 0 r7 (2).72
0 r2 16
(11).52
∴ 757.2510 = 2F5.4016 16
= 0010 1111 0101.0100 00002 (8).32
2 F 5 4 0
1.1 (c) 356.89 ∴123.1710 = 7B.2B16
2
10
16 | 356 0.89 = 0111 1011.0010 1011
7 B 2 B
16 | 22 r4 16
16 | 1 r6 (14).24 1.1 (d) 1063.510
0 r1 16 16 | 1063 0.5
(3).84 16 | 66 r7 16
16 16 | 4 r2 (8).00
(13).44 0 r4
16
(7).04 ∴1063.510 = 427.816
= 0100 0010 0111.10002
∴ 356.8910 = 164.E316 4 2 7 8
7
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Unit 1 Solutions
464
6 5B1.1C16 = 010110110001.00011100 2=2661.070 8
(1).4784 2 6 6 1 0 7 0
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Unit 1 Solutions
1.5 (a) 1 11
1111 (Multiply) 1.5 (b, c) See FLD p. 730 for solutions.
1111 (Add) ×1010
+1010 0000
11001 1111 1.6, 1.7, See FLD p. 730 for solutions.
11110 1.8, 1.9
1111 (Sub) 0000
1.10 (a) 1305.37510
−1010 011110
0101 1111 16 | 1305 0.375
10010110 16 | 81 r9 16
5 r1 (6).000
6 r15 = F16 16 5 1 9 6 0 0
(5).28 1.10 (c) 301.1210
16 16 | 301 0.12
(4).48 16 | 18 r13 16
1 r2 (1).92
∴ 111.3310 = 6F.5416 16
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Unit 1 Solutions
4|1 r2 (3).84 9 | 15 r5 (8).46
0 r1 4 9|1 r6 9
(3).36 0 r1 (4).14
∴ 384.7410 = 12000.2331134...
∴ A52.A411 = 1267.9410 = 1657.84279...
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Unit 1 Solutions
1.13 544.1 = 5 × 92 + 4 × 91 + 4 × 90 + 1 × 9–1 1.14 (a), (c) 16 | 97 .7
9
= 5 × 81 + 4 × 9 + 4 + 1/9 (b), (c) 16 | 6 r1 16
= 445 1/910 0 r6 (11).2
16 | 445 1/9 16
16 | 27 r13 16 (3).2
16 | 1 r11 (1)7/9 ∴ 97.710 = 61.B3333....16
0 r1 16 (a) 61.B3333..16
(12)4/9 = 110 0001.1011 0011 0011 0011 0011... 2
16 (b) 1 100 001.101 100 110 011 001 100 11... 2
(7)1/9 = 141.5 4631 4631.... 8
∴ 544.19 = 1BD.1C716
= 1 1011 1101.0001 1100 01112...
∴ 2983 63/6410 = 5647.768 (or 5647.778) ∴ 93.7010 = 135.548 = 001 011 101.101 1002
= 101 110 100 111.111 1102
(or 101 110 100 111.111 1112)
11
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Unit 1 Solutions
1.17 (a) 111 111 1.17 (b) 1 11 11
1111 (Add) 1111 (Subtract) 1101001(Add) 1101001 (Sub)
1001 1001 110110 110110
11000 0110 10011111 110011
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Unit 1 Solutions
1.20(b) 100011 Quotient 1.20(c) 1011 Quotient
1011 )110000011 1010 )1110100
1011 1010
10001 10010
1011 1010
1101 10000
1011 1010
10 Remainder 110 Remainder
1.21 (a) 4 + 3 is 10 in base 7, i.e., the sum digit is 1.22 If the binary number has n bits (to the right of the
0 with a carry of 1 to the next column. 1 + 5 + radix point), then its precision is (1/2n+1). So to
4 is 10 in base 7. 1 + 6 + 0 is 10 in base 7. This have the same precision, n must satisfy
overflows since the correct sum is 10007.
(b) 4 + 3 + 3 + 3 = 13 in base 10 and 23 in base (1/2n+1) < (1/2)(1/104) or n > 4/(log 2) = 13.28 so n
5. Try base 10. 1 + 2 + 4 + 1 + 3 = 11 in base 10 so must be 14.
base 10 does not produce a sum digit of 2. Try base
5. 2 + 2 + 4 + 1 + 3 = 22 in base 5 so base 5 works.
1.23
(c) 4 + 3 + 3 + 3 = 31 in base 4, 21 in base 6,
.363636....
and 11 in base 12. Try base 12. 1 + 2 + 4 + 1 + 3 =
= (36/102)(1 + 1/102 + 1/104 + 1/106 + …)
B in base 12 so base 12 does not work. Try base 4.
= (36/102)[1/(1 – 1/102)] = (36/102)[102/99]
3 + 2 + 4 + 1 + 3 = 31 in base 4 so base 4 does not
= 36/99 = 4/11
work. Try base 6. 2 + 2 + 4 + 1 + 3 = 20 so base 6
8(4/11) = 2 + 10/11
is correct.
8(10/11) = 7 + 3/11
8(3/11) = 2 + 2/11
8(2/11) = 1 + 5/11
1.24 (a) Expand the base b number into a power series
8(5/11) =3 + 7/11
N = d3k-1b3k-1 + d3k-2b3k-2 + d3k-3b3k-3 + …. + d5b5
8(7/11) = 5+ 1/11
+ d4b4 + d3b3 + d2b2 + d1b1 + d0b0 + d-1b-1 + d b- 8(1/11) = 0 + 8/11
-2
2 + d-3b-3 + …. + d-3m+2b-3m+2 + d-3m+1b-3m+1 8(8/11) = 5 + 9/11
+ d-3mb-3m where each di has a value from 0 to 8(9/11) = 6 + 6/11
(b-1). (Note that 0’s can be appended to the number 8(6/11) = 4 + 4/11
so that it has a multiple of 3 digits to the left and 8(4/11) = 2 + 10/11
right of the radix point.) Factor b3 from each group Repeats: .27213505642…….
of 3 consecutive digits of the number to obtain
N = (d3k-1b2 + d3k-2b1 + d3k-3b0)(b3)(k-1) + ….
1.24 (b) Expand the base b3 number into a power series
+ (d5b2 + d4b1 + d3b0)(b3)1 + (d2b2 + d1b1 +
N = dk(b3)k + dk-1(b3)k-1 + … + d1(b3)1 + d0(b3)0
d0b0 )(b3)0 + (d-1b2 + d-2b1 + d-3b0)(b3)-1 + …. +
+ d-1(b3)-1 + …. + d-m(b3)-m
(d-3m+2b2 + d-3m+1b1 + d-3mb0)(b3)-m where each di has a value from 0 to (b3 -1).
Each (d3i-1b2 + d3i-2b1 + d3i-3b0) has a value from Consequently, di can be represented as a base b
0 to [(b-1)b2 + (b-1)b1 + (b-1)b0] number in the form
= (b-1)( b2 + b1 + b0) = (b3-1) (e3i-1b2 + e3i-2b1 + e3i-3b0) Where each e
j
so it is a valid digit in a base b3 number. has a value from 0 to (b-1). Substituting these
Consequently, the last expression is the power expressions for the di produces a power series
series expansion for a base b3 number. expansion for a base b number.
1.25(a) (5 - 1) = 45, (52 - 1) = 445 and (53 - 1) = 4445 1.26(a) (b + 1)2 = b2 + 2b + 1 so (11b)2 = 121b if b > 2.
15
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Unit 1 Solutions
1.27(a) (0.12)3 = (1/3 + 2/9)10 = (2/6 + 8/36)10 1.28 1.29
= (3/6 + 2/36)10 = (0.32)6 5-3-1-1 is possible, but
43 2 1
1.27(b) (0.375)10 = (3/8)10 = (0.3)8 6-4-1-1 is not, because
0 00 0 0 there is no way to
1.27(c) (a-1R-1 + a-2R-2 + ... + a-mR-m)Sn will be an 1 00 0 1 represent 3 or 9.
integer for every N only if Rm divides Sn for 2 00 1 0 Alternate
some n. Hence, each factor of R must be a factor Solutions:
of S, not necessarily the same number of times. 3 01 0 0
1.27(d) 4 10 0 0 5311
For a specific number N, (a-1R-1 + a-2R-2 + ...
+ a-mR-m)Sn will be an integer if each factor of 5 10 0 1 0 0000
Rm is a factor of either Sn or 6 10 1 0 1 0001 (0010)
(a-1Rm-1 + a-2Rm-2 + ... + a-m) 2 0011
7 11 0 0
1.30 5-4-1-1 is not possible, because there is no way to 3 0100
8 11 0 1
represent 3 or 8. 6-3-2-1 is possible: 4 0101
9 11 1 0 (0110)
6321 5 1000
9154 = 6 1001 (1010)
0 0000 1110 0001 1001 1000 7 1011
1 0001
8 1100
2 0010
9 1101 (1110)
3 0100
4 0101 1.32
5 0110 1.31 Alternate Alternate
6 1000 Solutions: Solutions:
7 1001 62 21 5221
8 1010 0 00 00 0 0000
9 1100 1 00 01 1 0001
2 00 10 (0100) (0100)
1.33 Alternate 2 0010
3 00 11 (0101) (0101)
Solutions: 3 0011
4 01 10 4 0110
73 21 5 01 11 5 1000
0 00 00 6 10 00 6 1001
1 00 01 7 10 01 7 1010 (1100)
8 10 10 (1100) (1101)
2 00 10 8 1011
9 10 11 (1101)
3 01 00 (0011) 9 1110
4 01 01 1100 0011 = 83 1110 0110 = 94
5 01 10
6 01 11 (a) 8 4 -2-1 (b)
1.34
7 10 00 The 9’s
0 00 00
8 10 01 complement
1 01 11 of a decimal
9 10 10
2 01 10 number
A 11 00 represented
3 01 01
B 11 01 (1011) with this
4 01 00
weighted code
5 10 11
can be obtained
B4A9 = 1101 0101 1100 1010 6 10 10 by replacing
Alt.: = " " 1011 " 7 10 01 0's with 1's
8 10 00 and 1's with
0's (bit-by-bit
9 11 11
16
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Unit 1 Solutions
complement).
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Unit 1 Solutions
1.35 (a) 222.2210 1.35 (b) 183.8110
16 | 222 0.22 16 | 183 0.81
16 | 13 r14 16 16 | 11 r7 16
0 r13 (3).52 0 r11 (12).96
16 16
(8).32 (15).36
1.36 (a) In 2’s complement In 1’s complement 1.36 (b) In 2’s complement In 1’s complement
(–10) + (–11) (–10) + (–11) (–10) + (–6) (–10) + (–6)
110110 110101 110110 110101
110101 110100 111010 111001
(1)101011 (–21) (1)101001 (1)110000 (–16) (1)101110
1 1
101010 (–21) 101111 (–16)
1.36 (c) In 2’s complement In 1’s complement 1.36(d) In 2’s complement In 1’s complement
(–8) + (–11) (–8) + (–11) 11 + 9 11 + 9
111000 110111 001011 001011
110101 110100 001001 001001
(1)101101 (–19) (1)101011 010100 (20) 010100 (20)
1
101100 (–19)
1.36 (e) In 2’s complement In 1’s complement 1.37 (a) 01001-11010
(–11) + (–4) (–11) + (–4) In 2’s complement In 1’s complement
110101 110100 01001 01001
111100 111011 + 00110 + 00101
(1)110001 (–15) ( )101111 01111 01110
1 1
110000 (–15)
1.37 (b) In 2’s complement In 1’s complement 1.37 (c) In 2’s complement In 1’s complement
11010 11010 10110 10110
+ 00111 + 00110 + 10011 + 10010
(1)00001 (1)00000 (1)01001 (1)01000
1 overflow 1
00001 01001
overflow
1.37 (d) In 2’s complement In 1’s complement 1.37 (e) In 2’s complement In 1’s complement
11011 11011 11100 11100
+ 11001 + 11000 + 01011 + 01010
(1)10100 (1)10011 (1)00111 (1)00110
1 1
10100 00111
1.38 (a) In 2’s complement In 1’s complement 1.38 (b) In 2’s complement In 1’s complement
11010 11010 01011 01011
+ 01100 + 01011 + 01000 + 00111
(1)00110 (1)00101 10011 10010
1
00110
18
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Unit 1 Solutions
1.38 (c) In 2’s complement In 1’s complement 1.38 (d) In 2’s complement In 1’s complement
10001 10001 10101 10101
+ 10110 + 10101 + 00110 + 00101
(1)00111 (1)00110 11011 11010
overflow 1
00111
overflow
1.39 (a) add subt 1.40 (a) complement
101010 101010 i) 00000000 (0) 11111111 (-0)
+ 011101 - 011101 ii) 11111110 (-1) 00000001 (1)
(1)000111 001101 iii) 00110011 (51) 11001100 (-51)
1 overflow iv) 10000000 (-127) 01111111 (127)
001000
(b)
(b) add subt i) 00000000 (0) 00000000 (0)
101010 101010 ii) 11111110 (-2) 00000010 (2)
+ 011101 - 011101 iii) 00110011 (51) 11001101 (-51)
(1)000111 001101 iv) 10000000 (-128) 10000000 (-128)
overflow
1.41 (a) (16)(4) = 64, add 2 0’s to get 6400 1.42 (a) If A + B < 2n-1 - 1, then the sign bit of A + B is
(10)(2) = 20, add 1 0 to get 200 0 indicating a positive number with magnitude
(7)(1) = 7 A + B. If A + B > 2n-1 - 1, then the sign bit
6400 + 200 + 7 = 6607 of A + B is 1 indicating a negative number with
n
magnitude 2 - (A + B).
(b) (dn-1dn-2 … d1d0)20 = dn-1(20)n-1 +
1.43 A and B positive: Overflow does not occur if result represents a negative number with magnitude (B - A).
A + B < 2n - 1 - 1 in which case A + B has a sign
bit of 0 and has a magnitude of A + B.
A positive and B negative and A > |B|: A + 2n -
1 - B = 2n - 1 + (A - B) > 2n - 1 so there is a carry
from the sign position and, after the end-around
carry, the result is (A - B).
A positive and B negative and A < |B|: A + 2n -
1 - B = 2n - 1 - (B - A) < 2n - 1 so there is no carry
from the sign position and the sign bit is 1 so the
19
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.43 if A + B < 2n - 1 - 1 in which case
cont. 2n - 1 - (A + B) > 2n - 1 so the sign bit is
A and B 1 and the result represents a negative
negative: number with magnitude (A + B).
(2n - 1 - A)
+ (2n - 1 -
B) =
2
n
-
1
-
(
A
+
B
)
a
f
t
e
r
t
h
e
e
n
d
-
a
r
o
u
n
d
c
a
r
r
y
.
T
h
e
r
e
i
s
n
o
o
v
e
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f
l
o
w 20
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
1.44 Two positive numbers 1.45 There is no overflow if the carry into the sign
No overflow: 0x…x + 0x…x = 0x…x position equals the carry out of the sign position.
carry in = 0 = carry out There is overflow if the carry into the sign position
Overflow: 0x…x + 0x…x = 1x…x does not equal the carry out of the sign position
carry in = 1, carry out = 0 unless an end around carry causes a carry into the
sign position.
Two negative numbers
No overflow: 1x…x + 1x…x = 1x…x No overflow Overflow
21
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
Unit 1 Solutions
16
© 2014 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.
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Le Commissaire.
En ce cas, Monsieur, j'ai mille excuses à vous faire. Je vous avois
fait avertir, parce que ce jeune homme, chargé d'une accusation
assez grave, avoit pris votre nom et se disoit votre fils; mais sa
déclaration étoit fausse. Je suis fâché qu'on vous ait dérangé.
Le Marquis, au commissaire.
Comment! sa déclaration étoit fausse? Mais ne vous ai-je pas
prié, Monsieur, de laisser ce nom de Faublas sur votre procès-verbal?
(Tout bas au chevalier.) Vous ne sentez donc pas les conséquences
de cela, vous? Si une fois ce commissaire écrit votre véritable nom, il
enverra chercher votre véritable père, et cela fera une scène… Priez
ce monsieur de Faublas de vous laisser son nom, cela finira tout.
Le Chevalier de Faublas, au marquis.
Je n'ose.
Le Marquis.
Je vais lui dire, moi!… (Au baron.) Dites qu'il est votre fils.