Module 1

Mallunt And techwe

ystem Softiart
bpph oth'on
p Coion
s9twarl l
*DiHexente betwneen System
Sotwai.
Dnstuctional
ComPudes)

ST (SimpLigied hat hon ben

ta Compte
SIC is a hypo theti hadwene
h n c d wcne
deatunef
deatuae
to Include He
Covnefulby deoigned hnglu nes,
Ohi e aavojolirg
kOki Je voidi'ng
on head
MOSt od'tendy dound
Complexities.
unusua d i o l e vant

too vesrand
Tt hou
booic Version

Standaad STC
VAOn
SIC XXE (highu enpendine
entha
eeeui Pmenk |
L endr
e n na
t

Aachtentwne

Standad STC Mauine

Memo
Conast 8 - bit by
n std SC,
ooAd
they tam the
3 on Sequhhe by tes
Cau brt) M
addae on
SLC byte addae
A
addrom ed by ta oCoki on oheit
Odf ae

coa total 32 68
ambereod byte, +here
JoJeot
CAPutel memouy
(a by te in the
 Reg'ste3-
s au bi
Theie ne 5 egisteh eath hegsteg
n length

Mnemoril Ou m b e S Peual ugeR

A wwed ta
t c c u m Jatoh,
aithmout'c operah'on

X Thdex negiste, o e d FA

addnemi
3 L e, o e dFa
inkage7agist
Jump to SubnoutireSUB
Pnytuh'on StoneD hhe
tuan add. in tu's neg.

Pc Pho9Aam Countes, Contain

r t aution fo e t e t d d

foA eention

statud ooad, Contoind

SW
Vauety ntmahon

fncludina a Condr hion Code

(cc)
ote C c s clhe Ck
a
dloe,9hh s Set to e
Condton (Lke a<b, a=b, etc-)

Tota dehmot
Cped ta totoN He
I t iS fmot h i h iS

ota
 no. is not Suppoalcd in TC.
% lo eingPoint
Dada Can be a integu a uhonalteA
(3 byta)
integosoUe Stoaed ag bit binay om
Coda
8 -bit ASCII Coo
(1byt
hoautu, ae Stoaed wwing
p n e e n t tn 3 Conmplment
egative vali a

htauhion FoAmat

s nctting but aa
but aMem by
Tn8tnucttdn fAmet

fnytau hion
anguog
.

is u bit TAmet
It a

L5 ntA'm tomat
addae
epCode
indeded
cate
is e d to indi
F l a g 6it
FA
Moolo by
addreM° intrution
S not
undetable

ASSem bl Ang. Convettd into objet Code

ComP t & j So S
fiddres ng Modej
'nn SIC
SEC
ingModes
ae d adLN
There

Dihet adds. mode X

Dise X= 1
Indexed add m ade
aoldao) Caluntaton (TA)
Toget
T ATA OddneM
TA = addnem+(X)

, Pt9ed Only
WhLX) > Content heg'Ste
i'nde erJte
e
HePAogAam Sct
Tant addoss a dokdy,Ohere
soded Tt s a a bit tamet 3 byte fomot
 eg Diaet adds. modle

LDA TEN
add

( O000
objecco

y
&u byt (hexa

oPCode TE N
(add nen)
( o - 9 A t o F )

Ihdine t addds mode

STCH BUFF ER , X

olol
Oloo 1 ool
H

OpCode BuFFER

Tn&taulion Se
SIC PAON iole baptc &et intauci ory thet ce
Sufcet ta 87Mple took
Load Stoe negtea: LDA, LDX, STA, STX
Drdergu aithmec ADD, SUB, MUL , DIV

n A a koAd ih memoe
ComP-Cormpooe vale aag.
Set Condi ton Code cc (<.5,)

jump nytxuchn -SLT,JEG, JaT

)Conditional

uboutinecnkage : SSDB, PSOB

6Inpt output : Eak device is Cigned a Urige
opoand Llo ingts"
8 bit Code, ay an

Teot Divice (TD) (heady) , =( not Aeaoly

Pead Data ( PD) , Lot Data (D).
Appendix A

SICXE Instruction Set and

Addressing Modes

Instruction Set
In the following descriptiorns, uppercase letters refer to specific
notation m indicates a memory address, n indicates an registers. The
integer between
16, and rl and r2 represent register identifiers. Parentheses are used
1 and
to denote
the contents of a register or location. Thus
memory A-(1.m+2) specifies that
the contents of the memory locations m
through m+2 are loaded into register A;
m.m+2 -(A) specifies that the contents of
register A are stored in the word
that begins at address m.
The letters in the Notes column have the following meanings:

P Privileged instruction

X Instruction available only on XE version

F Floating-point instruction

Condition code CC set to indicate result of operation (<, =, or >)

C

SIC/XE instruction format is to be used in

The Format column indicates which
mearns that either Format 3 or Format 4
can
assembling each instruction; 3/4 using
instructions for the standard version of SIC are assembled
be used. All with Format 3).
in Section 1.3.1 (which is compatible
the format described such as the address field for an
Instruction subfields
that are not required,
are set to z e r o .
instruction.
RSUB
Mnemonic Format Opcode Effect Notes

ADD m 18 A-(A) + (m.m+2)

3/4
ADDF mn 3/4 58 F-(F)+ (m..m+5) XF
ADDR r1,12 2 90 r2-(2) +(r1) X
AND m 3/4 40 A-(A) & (m.m+2)

CLEAR rl 2 B4 r1-0 X

COMP m 3/4 28 (A): (m..m+2) C

COMPF m 3/4 88 (F) (m.m+5) XFC
COMPR r1,r2 2 A0 (r1): (2) XC
DIV m 3/4 24 A-(A)/ (m.m+2)
DIVF mn 3/4 64 F-(F) / (m..m+5) XF
DIVR r1,12 2 9C r2-(r2)/(r1) X
FIX 1 C4 A-(F) [convert to integer] XF
FLOAT CO F-(A) [convertto floating] XF
HIO F4 Halt I/O channel number (A) PX
Jm 3/4 3C PC-m
JEQ m 3/4 30 PC mif CC set to =
JGT m 3/4 34 PC-mif CC set to >
JLT m 3/4 38 PCm if CC set to<
JSUB m 3/4 48 L-(PC); PC-m
LDA mn 3/4 00
A-(m.m+2)
LDB m 3/4 68 B-(m..m+2) X
LDCH m 3/4 50
A[rightmost byte]-(m)
LDF m 3/4 70 F-(m.m+5) XF
LDL m 3/4 08 L-(m..m+2)
LDS m 3/4 6C S-(m.m+2) X
LDT m 3/4 74 T-(m.m+2) X
LDX m 3/4 04 X-(m.m+2)
LPS m 3/4 DO Load processor status from PX
information beginning at
address m (see Section 6.2.1)
MUL m 3/4 20 A-(A) * (m.m+2)
M n e m o n i c Format Opcode Effect
Notes
MULF m 3/4 60
F-(F)* (m..m+5) XF
MULR r1,r2 2 98
r2-(2)*(r1)
NORM 1 C8 F-(F) [normalized] XF
OR m 3/4 44 A-(A) | (m.m+2)
RD m 3/4 D8 A[rightmost byte]- data P
from device specified by (m)
RMO r1,r2 2 AC r2-(rl) X

RSUB 3/4 4C PC-(L)

SHIFTL r1,n 2 A4 rl-(r1); left circular shift
n bits. {In assembled
instruction, r2 = n-1}

SHIFTR r1,n 2 A8 rl-(r1); right shift n bits, X

with vacated bit positions set
equal to leftmost bit of (r1).
{In assembled instruction,
r2=n-1
PX
1 FO Start 1/O channel number (A);
SIO
address of channel program
is given by (S)
Protection key for address m PX
SSK m 3/4 EC
(A) (see Section 6.2.4)
m..m+2 - (A)
STA m 3/4 OC
m.m+2 - (B)
STB m 3/4 78
54
m-(A) [ightmostbyte]
STCH m 3/4 XF
m.m+5 - (F)
80
STF m 3/4 PX
Interval timer value
-
D4
STI m 3/4 (m.m+2) (see Section 6.2.1)
m..m+2 - (L)
14
STL m 3/4 X
m..m+2 (S)
7C
STS m 3/4 m.m+2 - (SW) P
E8
STSW m 3/4 X
m..m+2 ( 1 )
84
STT m 3/4 m.m+2- (X)
10
STX m 3/4 A-(A) -(m.m+2)
1C
SUB m 3/4 XF
F-(F)-(m.m+5)
5C
SUBF mn 3/4
 Mnemonic Format Opcode Effect Notes
SUBR r1,r2 2 94 r2-(r2)-(r1) X
SVC n 2 BO Generate SVC interrupt. {In X
assembled instruction, rl =
n}
TD m 3/4 EO Test device specified by (m) P C
TIO 1 F8 Test I/O channel number (A) PX C
TIX m 3/4 2C X-(X) +1; (X): (m..m+2) C
TIXR r1 2 B8 X-(X) +1; (X): (r1) XC
WD m 3/4 DC Device specified by (m) - (A) P
rightmost byte]