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DIGITAL LOGIC DESIGN

SUBMITTED BY

Rani sharafat (01-135211-068)

Maaz akram (01-135211-092)
Rumman haider (01-135211-104)
Zarmeen Fatima (01-135211-068)
BSIT-2A
SUBMITTED TO
MAM Maryam Aslam

ACTIVTY

Abstract- We have to make a project that is an implementation of the theoretical

concepts delivered to us by our lab instructor. So we designed a 2x2 multiplier
that multiplies 2-bit binary numbers and generates a specific result.

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 OBJECTIVE:

The objective of this complex engineering activity is to carry out research,

analysis, design, investigation, and implementation of a real-world complex
software engineering project that has the following attributes:

1. Depth of Analysis Required: The activity requires abstract thinking,

originality in analysis to formulate suitable software models of the activity;

2. Innovation: The activity involves creative use of engineering principles and

research- based knowledge in novel ways;

3. Familiarity: The activity can extend beyond previous experiences by

applying principles-based approaches.

Table of Contents:

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Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Project Details ............................................... 4

Chapter 1: INTRODUCTION - Concept Used . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1) AND gate .........................5

1.2) Half Adders .........................6
1.3) Binary Multiplier ...............................7
1.4) Seven segment display .............................. 8

Chapter 2: Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1) Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10

2.2) Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3) Software Simulations along with hardware results . . . . . . . . . . . . . 12

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Project Details

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The project we that we have chosen for Complex engineering activity is a “2 × 2
Multiplier”. It is basically a circuit that multiplies 2 bit binary number and
generates a specific result.

INPUTS

OUTPUTS

Following things are used in our project:

• SSD’s (Common Anode)

• XOR IC (74HC86) – contains 4 XOR’s
• AND IC (7408)
• Power supply
• Breadboard
• Connecting wires

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Chapter.01 “Concept Used”

1.1) AND GATE:

The output state of a digital logic AND gate only returns “LOW” again when ANY
of its inputs are at a logic level “0”. In other words for a logic AND gate, any LOW
input will give a LOW output.

The logic or Boolean expression given for a digital logic AND gate is that for
Logical Multiplication which is denoted by a single dot or full stop symbol, ( . )
giving us the Boolean expression of: A.B = Q.

Then we can define the operation of a digital 2-input logic AND gate as being:

“If both A and B are true, then Q is true”

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1.2) Half Adders:

Half adder is a combinational arithmetic circuit that adds two numbers and
produces a sum bit (S) and carry bit (C) as the output. If A and B are the input
bits, then sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND
of A and B. From this it is clear that a half adder circuit can be easily constructed
using one X-OR gate and one AND gate. Half adder is the simplest of all adder
circuit, but it has a major disadvantage. The half adder can add only two input
bits (A and B) and has nothing to do with the carry if there is any in the input. So if
the input to a half adder have a carry, then it will be neglected it and adds only
the A and B bits. That means the binary addition process is not complete and
that’s why it is called a half adder.

NAND gates or NOR gates can be used for realizing the half adder in universal

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logic and the relevant circuit diagrams are shown in the figure below.

1.3) Binary Multipliers:

A binary multiplier is a combinational logic circuit or digital device used for

multiplying two binary numbers. The two numbers are more specifically known as
multiplicand and multiplier and the result is known as a product. The multiplicand
& multiplier can be of various bit size. The product’s bit size depends on the bit
size of the multiplicand & multiplier. The bit size of the product is equal to the
sum of the bit size of multiplier & multiplicand.

Binary multiplication method is same as decimal multiplication. Binary

multiplication of more than 1-bit numbers contains 2 steps. The 1st step is single
bit-wise multiplication known as partial product and the 2nd step is adding all
partial products into a single product. Partial products or single bit products can
be obtained by using AND gates. However, to add these partial products we need
full adders & half adders.

2×2 Bit Multiplier

This multiplier can multiply two numbers having bit size = 2 i.e. the multiplier and
multiplicand can be of 2 bits. The product bit size will be the sum of the bit size of
the input i.e. 2+2=4. The maximum range of its output is 3 x 3 = 9. So we can

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accommodate decimal 9 in 4 bits. It is another way of finding the bit size of the
product.

1.4) Seven segment Display:

The 7-segment display, also written as “seven segment display”, consists of seven
LEDs (hence its name) arranged in a rectangular fashion as shown. Each of the
seven LEDs is called a segment because when illuminated the segment forms part
of a numerical digit (both Decimal and Hex) to be displayed. An additional 8th LED
is sometimes used within the same package thus allowing the indication of a
decimal point, (DP) when two or more 7-segment displays are connected
together to display numbers greater than ten.

Each one of the seven LEDs in the display is given a positional segment with one
of its connection pins being brought straight out of the rectangular plastic
package. These individually LED pins are labelled from a through to g representing
each individual LED. The other LED pins are connected together and wired to form
a common pin.

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The displays common pin is generally used to identify which type of 7-segment
display it is. As each LED has two connecting pins, one called the “Anode” and the
other called the “Cathode”, there are therefore two types of LED 7-segment
display called: Common Cathode (CC) and Common Anode (CA).

1. The Common Cathode (CC) : In the common cathode display, all the
cathode connections of the LED segments are joined together to logic “0”
or ground. The individual segments are illuminated by application of a
“HIGH”, or logic “1” signal via a current limiting resistor to forward bias the
individual Anode terminals (a-g).

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 2. The Common Anode (CA) : In the common anode display, all the anode
connections of the LED segments are joined together to logic “1”. The
individual segments are illuminated by applying a ground, logic “0” or
“LOW” signal via a suitable current limiting resistor to the Cathode of the
particular segment (a-g).

Chapter.02”Demonstration”
2.1) Solution:

Truth table for a BCD to 7-SEGMENT DISPLAY FOR COMMON ANNODE

A B C D a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 0 0 1 0 0 0 0 0
0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0

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1 0 0 1 0 0 0 0 1 0 0
TABLE FOR 2X2 MULTIPLIER:

INPUTS OUTPUTS
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 0 0 0 1

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2.2) Circuit Design:
Following Is the circuit designs of our project:

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2.3) Software Simulation along with hardware results:

For Inputs 0000:

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Complex Engineering Activity( DLD ) Air University

For I

nputs 0001:
For Inputs 0010:

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For I
nputs 0011:

For Inputs 0101:

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 nputs 0110:

For Inputs 0111:

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For I
nputs 1110:

For Inputs 1111:

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Complex Engineering Activity( DLD ) Air University

CONCLUSIONS:

We successfully implemented the concepts and designed a 2x2 multiplier. We

verified all the results by comparing them with proteus simulations.

Bibliography:

 Digital Design, 5th Edition by M Morris Mano and Michael Ciletti 

DLD Lab Manual

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