IIR Filter Architectures and Biquad Filters
IIR Filter Architectures and Biquad Filters
The students [at Rice University] in the "Signal Theory" course [in 1971]
were required to do a project and since Chebyshev approximation was a
major topic in the course, the implementation of this new algorithm
became James McClellan's course project. This ultimately led to the
Parks–McClellan algorithm, which involved the theory of optimal
Chebyshev approximation and an efficient implementation. By the end of
the spring semester, McClellan and Parks were attempting to write a
variation of the Remez exchange algorithm for FIR filters. It took about six
weeks to develop and some optimal filters had been designed
successfully by the end of May.
Important insights
𝑥𝑛
𝑝3 𝑝2 𝑝1 𝑝0
+ + + + 𝑦𝑛
+ Z-1 + Z-1 + Z-1 +
+ + + +
Alternate Form adapted to IIR Filter
𝑥𝑛
𝑝3 𝑝2 𝑝1 𝑝0
+ + + + 𝑦𝑛
+ Z-1 + Z-1 + Z-1 +
+ + + +
𝑌 𝑧 𝑎0 + 𝑎1 𝑧 −1 + 𝑎2 𝑧 −2 = 𝑋 𝑧 𝑏0 + 𝑏1 𝑧 −1 + 𝑏2 𝑧 −2
1
𝑌 𝑧 = 𝑋 𝑧 𝑏0 + 𝑏1 𝑧 −1 + 𝑏2 𝑧 −2 − 𝑌 𝑧 𝑎1 𝑧 −1 + 𝑎2 𝑧 −2
𝑎0
1
𝑦 𝑛 = 𝑏0 𝑥 𝑛 + 𝑏1 𝑥 𝑛 − 1 + 𝑏2 𝑥 𝑛 − 2 − 𝑎1 𝑦 𝑛 − 1 − 𝑎2 𝑦 𝑛 − 2
𝑎0
Normalized (divide all coefficients by 𝑎0 )
𝑦 𝑛 = 𝑏0 𝑥 𝑛 + 𝑏1 𝑥 𝑛 − 1 + 𝑏2 𝑥 𝑛 − 2 − 𝑎1 𝑦 𝑛 − 1 − 𝑎2 𝑦 𝑛 − 2
BiQuad Direct Form I Implementation
𝑦 𝑛 = 𝑏0 𝑥 𝑛 + 𝑏1 𝑥 𝑛 − 1 + 𝑏2 𝑥 𝑛 − 2 − 𝑎1 𝑦 𝑛 − 1 − 𝑎2 𝑦 𝑛 − 2
https://en.wikipedia.org/wiki/Digital_biquad_filter
Biquad Direct Form II Implementation
𝑦 𝑛 = 𝑏0 𝑥 𝑛 + 𝑏1 𝑥 𝑛 − 1 + 𝑏2 𝑥 𝑛 − 2 − 𝑎1 𝑦 𝑛 − 1 − 𝑎2 𝑦 𝑛 − 2
https://en.wikipedia.org/wiki/Digital_biquad_filter
Some considerations with integer math
• Multiplying a sample of n bits by a coefficient of m bits results in a
product of length m + n bits.
• Adding two of these m + n bit products can result in a sum that is
m + n + 1 bits long.
• With the chain of adders we need to support m + n + 3 bits.
• With the multiplication of the 𝑦 𝑛 values the results will continue to
grow each time interval unless truncation (rounding) happens with
fixed-point implementations.
• With floating-point implementations, rounding is automatic based on
the precision of the floating-point values
Transposition of Direct Form I
https://en.wikipedia.org/wiki/Digital_biquad_filter
Transposition of Direct Form II
https://en.wikipedia.org/wiki/Digital_biquad_filter
Fixed vs Floating Point Implementations
Fixed point DSP usually prefers the non transposed forms and
has an accumulator with a large number of bits and is
rounded when stored in main memory. Floating point DSP
usually prefers the transposed form, each multiplication and
potentially each addition are rounded; the additions are
higher precision result, when both operands have similar
magnitude.
https://en.wikipedia.org/wiki/Digital_biquad_filter
Add Quantizer Q(z) to Direct Form I
Truncation to
reduce bit length
This adds
quantization noise
https://en.wikipedia.org/wiki/Digital_biquad_filter
Adding Quantization to the Direct Form II
https://en.wikipedia.org/wiki/Digital_biquad_filter
Cascading Biquads
𝑦0 𝑛 𝑤1 𝑛 𝑦1 𝑛 𝑤2 𝑛 𝑦2 𝑛 𝑤3 𝑛 𝑦3 𝑛
𝑏01 𝑏02 𝑏03
𝑥𝑛 y𝑛
𝑧 −1 𝑧 −1 𝑧 −1
𝑎11 𝑏11 𝑎12 𝑏12 𝑎13 𝑏13
𝑧 −1 𝑧 −1 𝑧 −1
𝑎21 𝑏21 𝑎22 𝑏22 𝑎23 𝑏23
𝑁𝑠
𝑏0𝑘 + 𝑏1𝑘 𝑧 −1 + 𝑏2𝑘 𝑧 −2
𝐻 𝑧 =ෑ
1 − 𝑎1𝑘 𝑧 −1 − 𝑎2𝑘 𝑧 −2
𝑘=1
𝑦0 𝑛 𝑤1 𝑛 𝑦1 𝑛 𝑤2 𝑛 𝑦2 𝑛 𝑤3 𝑛 𝑦3 𝑛
𝑏01 𝑏02 𝑏03
𝑥𝑛 y𝑛
𝑧 −1 𝑧 −1 𝑧 −1
𝑎11 𝑏11 𝑎12 𝑏12 𝑎13 𝑏13
𝑧 −1 𝑧 −1 𝑧 −1
𝑎21 𝑏21 𝑎22 𝑏22 𝑎23 𝑏23
𝑦0 𝑛 = 𝑥 𝑛
𝑦 𝑛 = 𝑦𝑁𝑠 𝑛
Combining Pairs
• There are many ways of pairing poles and zeros in these second order
sections.
• In theory all combinations will produce the same result when infinite-
precision arithmetic is used.
• Given the limitations of finite-precision arithmetic, the results may be
quite different with different pairings.