Aim

Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance

8. Tweak parameter

9. Apply ac signal, Analyze ac performance, small

Bits, pilani
signal model BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Task 5---DC Load Line

Q point location on VTC

Q point location on MOSFET

characteristics????????

Bits, pilani
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Actual operating region
of amplifier on voltage
Transfer Curve as Vin>=
Vin- VTN

𝑽𝑮𝑺 − 𝑽𝑻
linear
DC Load line for resistive load

The load line, superimposed on the transistor

characteristics, can be used to visualize the
bias condition and operating mode of the
transistor
Impact of changing Rd
Load line shifts

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Why Vds
half???
• Class A

• Class AB
Vov.=0.2 V

• Class B

Class A- Q point--- 𝑰𝑫 , 𝑽𝑮𝑺 , 𝑽𝑫𝑺 = 𝟏𝟐 𝑽𝑫𝑫 nearly

BITS Pilani, Pilani Campus

Q point on Output charac.—
load line
Corresponds to nearly center of VTC
Vdd/ Rd

Vdd

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Q point on Output charac
Signal swing on load line

I2

I1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Q point on Transfer charac.

I2
Id=1 mA

I1

-2mV
2mV Anu Gupta BITS Pilani, Pilani Campus
Typical values of 𝑽𝑫𝑺,𝑸, 𝑽𝑮𝑺,𝑸

MOSFET:
𝐼𝐷𝑆,𝑄 = 𝑑𝑒𝑝𝑒𝑛𝑑𝑠 𝑜𝑛 𝑔𝑎𝑖𝑛 𝑜𝑟 𝑝𝑜𝑤𝑒𝑟 𝑐𝑜𝑛𝑠𝑢𝑚𝑝𝑡𝑖𝑜𝑛 𝑠𝑝𝑒𝑐𝑠.
𝑉𝐷𝑆,𝑄 ≈ ℎ𝑎𝑙𝑓 𝑜𝑓 𝑉𝐷𝐷
𝑉𝐺𝑆,𝑄 = 𝑉𝑇 + 𝑉𝑜𝑣 ; (𝑉𝑜𝑣 ≈0.2 V)

BJT:
𝐼𝐶,𝑄 = 𝑑𝑒𝑝𝑒𝑛𝑑𝑠 𝑜𝑛 𝑔𝑎𝑖𝑛 𝑜𝑟 𝑝𝑜𝑤𝑒𝑟 𝑐𝑜𝑛𝑠𝑢𝑚𝑝𝑡𝑖𝑜𝑛 𝑠𝑝𝑒𝑐𝑠.
𝑉𝐶𝐸,𝑄 ≈ ℎ𝑎𝑙𝑓 𝑜𝑓 𝑉𝐶𝐶
𝑉𝐵𝐸,𝑄 = 𝑉𝛾 + ; typically around (0.5- 0.7 )V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

END
Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability,

Tweak parameter

8. Apply ac signal, Analyze ac performance, small

signal model Bits, pilani
BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Task-6 DC Bias circuit—

Types
DC bias circuit

1. Voltage bias (set VGS, VDS)

 Potential divider bias (2 variations)
 Drain to gate feedback bias (MOSFET)/ collector
to base feedback bias (BJT)

2. Current bias (set ID)

 Current mirror circuit

BITS Pilani, Pilani Campus

Potential divider bias circuit
2 variations

𝐼𝐷𝑆,𝑄 = 1𝑚𝐴 𝐼𝐷𝑆,𝑄 = 0.5𝑚𝐴

𝑉𝐷𝑆,𝑄 = 7 𝑉 𝑉𝐷𝑆,𝑄 = 5 𝑉
𝑉𝐺𝑆,𝑄 = 3.5𝑉 𝑉𝐺𝑆,𝑄 = 2𝑉

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Potential divider bias 1
Q point, 𝐼𝐷𝑄 = 1𝑚𝐴
𝑉𝐷𝑆,𝑄 = 7𝑉,
𝑉𝐺𝑆,𝑄 = 3.5 𝑉
10um technology
𝑉𝑇 = 1 𝑉
𝑢𝐴
𝜇𝑛 𝐶𝑜𝑥 = 100 2
𝑉

7𝑀
𝑉𝐺𝑆 = 𝟑. 𝟓 𝑽 = 𝑉𝐷𝐷
7 + 23 𝑀

𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝑉𝐷𝑆 ; 𝑅𝐷 = 𝟖 𝑲𝜴;

1 𝑊 2 𝑾 𝟑𝟐𝒖𝒎
𝐼𝐷 = 𝟏𝒎𝑨 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 → 𝑳
= 𝟑. 𝟐 =
𝟏𝟎𝒖𝒎
2 𝐿
 CSA- Q point on Output charac.
Signal swing on load line

I2

Id=1 mA

I1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Potential divider bias2 -- (IDS, V DS, VGS )
Potential divider bias with Rs

𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆
𝑅1
𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝑆
𝑅1 + 𝑅2
5um technology
𝑉𝑇 = 1 𝑉
𝑢𝐴
𝜇𝑛 𝐶𝑜𝑥 = 50 2
𝑉

𝐼𝐷𝑆,𝑄 = 0.5𝑚𝐴
𝑉𝐷𝑆,𝑄 = 5 𝑉
𝑉𝐺𝑆,𝑄 = 2𝑉
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Potential divider bias,
capacitive coupling

Capacitive coupling
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 In a technology
MOSFET----Drain to Gate feedback bias 𝑉𝑇 = 3 𝑉
D-G shorted (VGS=VDS) 𝑢𝐴
𝜇𝑛 𝐶𝑜𝑥 = 100 2
𝑉
Singe gate current is zero, 𝑉𝐷𝐷 =15 V
hence no DC voltage drop
across Rf 𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆 ;
𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐺𝑆
Since Rf is very large valued, 𝑉𝐷𝑆 =7V
so no coupling between input and 𝐼𝐷 = 𝟎. 𝟓𝒎𝑨
output ac voltage
𝑉𝐷𝐷 − 𝑉𝐷𝑆
𝑅𝐷 = = 8K ohm
𝐼𝐷
1 𝑊 2
𝐼𝐷 = 𝟏𝒎𝑨 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿

Drain-Gate shorted (VGS,Q=VDS,Q)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BJT-Collector to Base
feedback bias
𝑉𝐷𝐷 = 𝐼𝐶 + 𝐼𝐵 𝑅𝐶 + 𝐼𝐵 𝑅𝐹 + 𝑉𝐵𝐸 ; 𝐼𝐶
𝐼𝐵 = ; active region operation, 𝛽=100
𝑉𝐷𝐷 = 𝐼𝐶 + 𝐼𝐵 𝑅𝐶 + 𝑉𝐶𝐸 𝛽
𝛽+1
𝐼𝐶 + 𝐼𝐵 =𝐼𝐶
𝛽

𝛽+1
𝑉𝐷𝐷 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸
𝛽
𝛽+1 𝑅𝐹
𝑉𝐷𝐷 = 𝐼𝐶 𝑅𝐶 + + 𝑉𝐵𝐸 ;
𝛽 𝛽
𝑽𝑩𝑬,𝑸 =0.6 V

𝑽𝑩𝑬
𝑰𝑪 = 𝑰𝑺 𝒆𝒙𝒑
𝑽𝒕

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Capacitively coupled amplifier
Capacitor C1, C2, C3 introduce poles at low frequencies

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Capacitively coupled amplifier
Capacitors C1, C2, C3 introduce poles at low frequencies

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Current Biasing
Direct coupled amplifiers
IC BIASING—Current bias
Fix current first

Why???

BITS Pilani, Pilani Campus

Characteristics- ideal current
source behaviour

𝑅𝑐𝑚 = ∞, 𝑉𝑐𝑚 = 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Characteristics- practical
current source behaviour

Non idealities of current mirror 𝑅𝑐𝑚 ≠ ∞, 𝑉𝑚𝑖𝑛 ≠ 0

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Current bias
Basic current mirror ckt.

𝑽𝑩𝑬𝟏
𝑽𝒕𝒉 𝑽𝑪𝑪 −𝑽𝑩𝑬𝟏
𝑰𝑹𝑬𝑭 = 𝑰𝑺 𝒆𝒙𝒑 =
𝑹𝟏
𝟐
𝑽𝑫𝑫 − 𝑽𝑮𝑺𝟏
𝑰𝑹𝑬𝑭 = 𝜷 𝑽𝑮𝑺 − 𝑽𝑻 =
𝑹𝟏

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Current transfer ratio
MOSFET

𝑰𝑫
= 𝟏; 𝒊𝒅𝒆𝒂𝒍
𝑰𝑹𝑬𝑭

𝐼𝐷 1 + λ𝑉𝐷𝑆
= ≠ 1; 𝑉𝐷𝑆 ≠ 𝑉𝐺𝑆 always
𝐼𝑅𝐸𝐹 1 + λ𝑉𝐺𝑆

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT CM No ideality –
Base current – current transfer ratio

𝐼𝑟𝑒𝑓 = 𝐼𝑐 − 4𝐼𝑏
𝐼𝑜𝑢𝑡 1
=
𝐼𝑟𝑒𝑓 1 + 4
𝛽
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CSA with Current bias
Current mirror ckt.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Which is better, I or II ?

BAD

Good
 Direct Coupled amplifiers
No Cc1, Cc2, poles at low frequencies

No
capacitor

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Bypass capacitor Cs
Why?
--Large Bypass capacitor Cs to provide nearly zero resistance ((1/jwCs)=0) path for ac signal,
-- thus brings node S to ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Pole
due to
Cc, Cs

Wp1 Wp2
Wp1
Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability

,make changes

8. Apply ac signal and Analyze ac performance, small

signal model Bits, pilani
BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Task-7--Q point stability

Which biasing scheme is best ?
Voltage bias
Which technique is best?

1. Voltage bias
 Potential divider bias
 Drain to gate feedback bias (MOSFET)/ collector to base
feedback bias (BJT)

 Which technique is best? (Q point should be insensitive

to Vdd fluctuation)

2 7𝑀
 𝐼𝐷𝑆 ∝ 𝛽 𝑉𝐺𝑆 − 𝑉𝑇 ; 𝑉𝐺𝑆 ∝ 𝑉𝐷𝐷
7+23 𝑀
𝑽𝑮𝑺
Check stability factor 𝑺𝑫𝑫

BITS Pilani, Pilani Campus

Stability factor
𝝏𝑽𝑮𝑺
𝑽𝑮𝑺 𝑽𝑮𝑺 𝑝𝑒𝑟𝑐𝑒𝑛𝑡𝑎𝑔𝑒 𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑉𝐺𝑆
𝑺𝑽𝑫𝑫 = ൙𝝏𝑽 =
𝑫𝑫 𝑝𝑒𝑟𝑐𝑒𝑛𝑡𝑎𝑔𝑒 𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝑉𝐷𝐷
𝑽𝑫𝑫

𝑽 𝑽𝑫𝑫 𝝏𝑽𝑮𝑺
𝑺𝑽𝑫𝑫 = ×
𝑮𝑺 𝑽𝑮𝑺 𝝏𝑽𝑫𝑫

𝑽
𝑺𝑽𝑮𝑺
𝑫𝑫
=1(worst case)

𝑽𝑮𝑺
𝑺𝑽𝑫𝑫 =0 (best value)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

PD bias1

𝑹𝟏
𝑽𝑮𝑺 = 𝑽
𝑹𝟏 + 𝑹𝟐 𝑫𝑫
𝜕𝑉𝐺𝑆 𝑅1
=
𝜕𝑉𝐷𝐷 𝑅1 + 𝑅2

𝑅1
𝑽 𝑽𝑫𝑫 𝝏𝑽𝑮𝑺 𝑅1 + 𝑅2
𝑺𝑽𝑮𝑺 = × = ൙ 𝑅1 = 1 (worst value)
𝑫𝑫 𝑽𝑮𝑺 𝝏𝑽𝑫𝑫
𝑅1 + 𝑅2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 PD bias2 𝑰𝑫 𝑹𝑫 = 𝑽𝑫𝑫 − 𝑽𝑫𝑺 − 𝑰𝑫 𝑹𝑺
𝑅1
𝑉𝐺𝑆 = 𝑉 − 𝐼𝐷 𝑅𝑆
𝑅1 + 𝑅2 𝐷𝐷
𝑅1 2
𝑉𝐺𝑆 = 𝑉 − 𝑅𝑆 𝛽 𝑉𝐺𝑆 − 𝑉𝑇
𝑅1 + 𝑅2 𝐷𝐷

𝜕𝑉𝐺𝑆 𝑅1 𝜕𝑉𝐺𝑆
= − 2𝛽𝑅𝑆 𝑉𝐺𝑆 − 𝑉𝑇
𝜕𝑉𝐷𝐷 𝑅1 + 𝑅2 𝜕𝑉𝐷𝐷

𝜕𝑉𝐺𝑆 𝑅1
1 + 2𝛽𝑅𝑆 𝑉𝐺𝑆 − 𝑉𝑇 =
𝜕𝑉𝐷𝐷 𝑅1 + 𝑅2
𝑅1
𝜕𝑉𝐺𝑆 𝑅1 + 𝑅2
=
𝜕𝑉𝐷𝐷 1 + 2𝛽𝑅𝑆 𝑉𝐺𝑆 − 𝑉𝑇
𝑹𝟏 = 𝟕𝑴, 𝑹𝟐 = 𝟖𝑴, 𝑽𝑫𝑫 = 𝟏𝟓𝑽, 𝑽𝑮𝑺 = 𝟐𝑽,
𝟏 𝑾 𝑾
𝑹𝑺 = 𝟏𝟎𝑲, 𝜷 = 𝝁𝒏 𝑪𝒐𝒙 , = 𝟐𝟎
𝟐 𝑳 𝑳
1 𝑊
𝐼𝐷 = 𝟎. 𝟓𝒎𝑨 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 2
2 𝐿
In a given technology 𝑹𝟏
𝑢𝐴 𝑽𝑫𝑫
𝑉𝑇 = 1 𝑉; 𝜇𝑛 𝐶𝑜𝑥 = 50 2 𝑽 𝑹𝟏 + 𝑹𝟐
𝑉 𝑺𝑽𝑮𝑺 = ×
𝑫𝑫 𝑽𝑮𝑺 𝟏 + 𝟐𝜷𝑹𝑺 𝑽𝑮𝑺 − 𝑽𝑻
 𝑹𝟏 = 𝟕𝑴, 𝑹𝟐 = 𝟖𝑴, 𝑽𝑫𝑫 = 𝟏𝟓𝑽, 𝑽𝑮𝑺 = 𝟐𝑽,
𝟏 𝑾 𝒖𝑨 𝑾
𝑹𝑺 = 𝟏𝟎𝑲, 𝜷 = 𝝁𝒏 𝑪𝒐𝒙 = 𝟓𝟎𝟎 𝟐 , = 𝟐𝟎
𝟐 𝑳 𝑽 𝑳
𝟏 𝑾
𝑰𝑫 = 𝟎. 𝟓𝒎𝑨 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝑻 𝟐
𝟐 𝑳
In a technology
𝑢𝐴
𝑉𝑇 = 1 𝑉; 𝜇𝑛 𝐶𝑜𝑥 = 50 2
𝑉

𝑅1
𝑽 𝑉𝐷𝐷 𝑅1 + 𝑅2
𝑺𝑽𝑮𝑺 = ×
𝑫𝑫 𝑉𝐺𝑆 1 + 2𝛽𝑅𝑆 𝑉𝐺𝑆 − 𝑉𝑇

𝑽 𝟑.𝟓
𝑺𝑽𝑮𝑺 = = 𝟎. 𝟑𝟓 ;
𝑫𝑫 𝟏+ 𝟏𝟎 𝟏

Stability factor<1, why? Intuitive reason?

• Reason? Negative feedback

• Drawback ???? Gain reduces
Drain-gate feedback bias
stability
𝑉𝐺𝑆 =𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝑅𝐷 𝛽 𝑉𝐺𝑆 − 𝑉𝑇 2
1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 2 = 𝛽 𝑉𝐺𝑆 − 𝑉𝑇 2
2 𝐿
2
𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝑅𝐷 𝛽 𝑉𝐺𝑆 − 𝑉𝑇

𝜕𝑉𝐺𝑆 𝜕𝑉𝐺𝑆
= 1 − 2𝑅𝐷 𝛽 𝑉𝐺𝑆 − 𝑉𝑇
𝜕𝑉𝐷𝐷 𝜕𝑉𝐷𝐷
𝜕𝑉𝐺𝑆 𝜕𝑉𝐺𝑆
+ 2𝑅𝐷 𝛽 𝑉𝐺𝑆 − 𝑉𝑇 =1
𝜕𝑉𝐷𝐷 𝜕𝑉𝐷𝐷

𝝏𝑽𝑮𝑺 𝟏
=
𝝏𝑽𝑫𝑫 𝟏 + 𝟐𝑹𝑫 𝜷 𝑽𝑮𝑺 − 𝑽𝑻

𝑽𝑫𝑫 𝝏𝑽𝑮𝑺 In a technology

𝑽
𝑺𝑽𝑮𝑺 = × =? ? ? ? 𝑢𝐴
𝑫𝑫 𝑽𝑮𝑺 𝝏𝑽𝑫𝑫 𝑉𝑇 = 1 𝑉; 𝜇𝑛 𝐶𝑜𝑥 = 50 2
𝑉
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
D-G feedback bias
Why is Sensitivity less than 1 ????

No Rs here
𝑉𝐺𝑆
Why 𝑉𝑑𝑑𝑆 < 1? ?
Intuitive explanation????
𝑵𝒆𝒈𝒂𝒕𝒊𝒗𝒆 𝒇𝒆𝒆𝒅𝒃𝒂𝒄𝒌

𝑉𝐷𝐷 ↑→ 𝑽𝑮𝑺 ↑, → 𝐼𝐷 ↑, → 𝑉𝑅𝑑 ↑, → 𝑽𝑮𝑺 ↓

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Generate V1-----Use resistor
ladder (poor stability of V1)

𝑽𝟏
𝑺𝑽𝑫𝑫 =1

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active resistor ladder—
(Vgs referenced),
Vref = V1 = (1/3) VDD
S= 1

Not much gain

but poor
stability

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Stability of Current mirror bias
Use reference arm
𝟐
𝑽𝑫𝑫 − 𝑽𝑮𝑺
𝑰𝑹𝑬𝑭 ∝ 𝜷 𝑽𝑮𝑺 − 𝑽𝑻 =
𝑹𝟏

𝜕𝑉𝐺𝑆 1 𝜕𝑉𝐺𝑆
2𝛽 𝑉𝐺𝑆 − 𝑉𝑇 = 1−
𝜕𝑉𝐷𝐷 𝑅1 𝜕𝑉𝐷𝐷

𝜕𝑉𝐺𝑆 1
=
𝜕𝑉𝐷𝐷 2𝛽𝑅1 𝑉𝐺𝑆 − 𝑉𝑇 +1

𝑽 𝑉𝐷𝐷 𝜕𝑉𝐺𝑆 𝑉𝐷𝐷 1

𝑺𝑽𝑮𝑺 = × = ×
𝑫𝑫 𝑉𝐺𝑆 𝜕𝑉𝐷𝐷 𝑉𝐺𝑆 2𝛽𝑅1 𝑉𝐺𝑆 − 𝑉𝑇 +1

𝟏 𝑾 𝑊
𝜷= 𝝁 𝑪 ; =20 𝑽𝑮𝑺
𝐿
𝟐 𝒏 𝒐𝒙 𝑳 𝑺𝑽𝑫𝑫 =0.625 <1
1 𝑊 𝑢𝐴
𝐼𝐷 = 0.5𝑚𝐴 = 2 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 2 ; 𝛽=500𝑉 2
𝐿
𝑢𝐴
In a technology 𝑉𝐷𝐷 = 5𝑉, 𝑉𝐺𝑆 =2V, 𝑉𝑇 = 1 𝑉, 𝜇𝑛 𝐶𝑜𝑥 = 50 𝑉 2 , 𝑅1 =6K
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Modified current mirror
For better stability

𝑽 𝑽𝑫𝑫 𝝏𝑽𝑮𝑺 𝑽𝑫𝑫 𝟏

𝑺𝑽𝑮𝑺 = × = ×
𝑫𝑫 𝑽𝑮𝑺 𝝏𝑽𝑫𝑫 𝑽𝑮𝑺 𝟐𝜷𝑹𝟏 𝑽𝑮𝑺 − 𝑽𝑻 +𝟏

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability

,make changes

8. Apply ac signal, Analyze ac performance, small

signal model
Anu Gupta Bits, pilani BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Task- 8 AC operation
Small signal analysis
 BITS Pilani
Pilani Campus

END
Amplifier designed

Voltage amplifier
Class A amplifier
MOSFET device amplifier
Common source amplifier
Direct coupled amplifier

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

MOSFET
Small signal parameters
Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability

,make changes

8. Apply ac signal, Analyze ac performance, small

signal model Bits, pilani
BITS Pilani, Pilani Campus
AC analysis of CSA

1. Small signal parameters expression

2. Small signal model of CSA

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

1.---Small signal parameters of MOSFET/ BJT

in active region
𝒈𝒎, 𝒓𝒐, 𝒈𝒎𝒃 / 𝒈𝒎, 𝒓𝒐, 𝒓𝝅, 𝒓𝒆
MOSFET
Small signal parameters

1. 𝒈𝒎

2. 𝒓𝒐

3. 𝒈𝒎𝒃

BITS Pilani, Pilani Campus

Total signal (DC+ac)

1 𝑊 2
𝐷𝐶 → 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿

1 𝑊 2
𝑎𝑐 → 𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝑔𝑠 − 𝑉𝑇
2 𝐿

1 𝑊 2
𝑡𝑜𝑡𝑎𝑙 → 𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝐺𝑆 − 𝑉𝑇
2 𝐿

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

MOSFET
structure

• Trans-conductance device
• 𝒈𝒎 ----defines gain
Bits, pilani
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Small Signal Parameters in
active region

iD= f (vGS, vDS, vSB)

𝒈𝒎 − trans-conductance

𝒓𝒐 − drain resistance or go/ gd= drain

conductance

𝒈𝒎𝒃 − body trans-conductance

Anu Gupta BITS Pilani, Pilani Campus

iD= f (VGS, VDS, VSB)—Taylor
approx.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 𝒅𝒊𝑫 𝒊𝒅 1 𝑊 2
𝒈𝒎 = = 𝐷𝐶; 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥
2 𝐿
𝑉𝐺𝑆 − 𝑉𝑇
𝒅𝒗𝑮𝑺 𝒗𝒈𝒔 1 𝑊 2
Total; 𝑖𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑣𝐺𝑆 − 𝑉𝑇
2 𝐿

𝒅𝒊𝑫 𝒊𝒅
𝒈𝒎 = 𝒂𝒕 𝑸 𝒑𝒐𝒊𝒏𝒕 = 𝒗𝒈𝒔 = 𝒗𝒔𝒃 = 𝟎
𝒅𝒗𝑮𝑺 𝒗𝒈𝒔

𝑾
𝒈𝒎 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝑻
𝑳

𝟐𝑰𝑫
𝒈𝒎 =
𝑽𝑮𝑺 − 𝑽𝑻

𝑾
𝒈𝒎 = 𝟐𝝁𝒏 𝑪𝒐𝒙 𝑰
𝑳 𝑫

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Large signal (total signal)
MODEL (for flat current profile)

1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
gm  f(Vov, Id, w/L)

• gm vs. w/L for Id constant

• gm vs. w/L for Vov. Constant

• gm vs. Id for Vov. Constant

Bits, pilani
Anu Gupta BITS Pilani, Pilani Campus
𝒈𝒎 parameter
𝟏 𝑾 𝟐
𝒊𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝒗𝑮𝑺 − 𝑽𝑻
𝟐 𝑳

Id also increases
• gm increases linearly
• Id also increases more
power consumption
• Vov. increases

BITS Pilani, Pilani Campus

How to keep ID constant?

• gm increases linearly
• Id constant
• Vov. Decreases/ or / (W/L ) reduces(good)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 𝟏 𝑾 𝟐
𝒊𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝒗𝑮𝑺 − 𝑽𝑻
𝟐 𝑳

• gm increases slowly
• Id increases more more
power consumption
• Vov. increases

good method

• gm increases linearly as Vov.

Reduces (PVT sensitivity more)
• No extra power consumption
• (W/L) increases
 1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿
ID increases with VDS

𝟏 𝑾 𝟐
𝑰𝑫 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝑻 𝟏 + 𝝀𝑽𝑫𝑺
𝟐 𝑳

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Secondary Effects
(ro, gmb)
iD= f (VDS)—Taylor series approx.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 𝒅𝒊𝑫
𝒓𝒐 =
𝒅𝒗𝑫𝑺
Channel Length Modulation effect

1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿 − ∆𝐿)
Bits, pilani
Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 1 𝑊 1 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
2 𝐿 ∆𝑳
1−
𝑳
Using binomial expansion---
1 𝑊 ∆𝑳
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 1+ 𝑉𝐺𝑆 − 𝑉𝑇 2
2 𝐿 𝑳
∆𝐿 ∝ 𝑉𝐷𝑆 → ∆𝐿 = 𝑘𝑉𝐷𝑆

1 𝑊 𝒌
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 1 + 𝑉𝐷𝑆 𝑉𝐺𝑆 − 𝑉𝑇 2 ;
2 𝐿 𝑳

𝒌
= 𝝀; 𝒄𝒉𝒂𝒏𝒏𝒆𝒍 𝒍𝒆𝒏𝒈𝒕𝒉 𝒎𝒐𝒅𝒖𝒍𝒂𝒕𝒊𝒐𝒏 𝒑𝒂𝒓𝒂𝒎𝒆𝒕𝒆𝒓
𝑳

1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 1 + λ𝑉𝐷𝑆
2 𝐿
 1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 1 + λ𝑉𝐷𝑆
2 𝐿

𝑑𝑣𝐷𝑆 1 𝑖𝑑
𝑟𝑜 = 𝑉𝐺𝑆, 𝑉𝑆𝐵 𝑐𝑜𝑛𝑠𝑡𝑡. = =
𝑑𝑖𝐷 𝑑𝑖𝐷 𝑣𝑑𝑠
𝑑𝑣𝐷𝑆
2
𝑟𝑜 =
𝑊 2
𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 λ
𝐿
𝟏
𝒓𝒐 ≈
𝒓𝒐 =
λ+1 𝟏
λ 𝑰𝑫
≈
𝟏
λ𝑰𝑫
≈
𝑽𝑨
𝑰𝑫
; λ𝑰𝑫
𝑽𝑨 = 𝐞𝐚𝐫𝐥𝐲 𝐯𝐨𝐥𝐭𝐚𝐠𝐞,
(𝐭𝐲𝐩𝐢𝐜𝐚𝐥𝐥𝐲 𝐥𝐚𝐫𝐠𝐞, 𝐡𝐲𝐩𝐨𝐭𝐡𝐞𝐭𝐢𝐜𝐚𝐥 𝐯𝐨𝐥𝐭𝐚𝐠𝐞)
Graphical explanation
Relation---λ, and Early voltage VA

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Impact of decreasing λ on current

decreasing λ = increasing |VA|

1 1
λ= ∝
𝑉𝐴 𝐿

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Modified large signal model & equ.

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Body (substrate) Bias Effect
VSB

VT = VTO +γ [(2ΦF + VSB) ½ – (2ΦF)½ ]

2qN A s

Cox
ID reduces

I D  K ' VGS  VT  1  VDS 

W 2

L
Anu Gupta BITS Pilani, Pilani Campus
iD= f (VBS)—Taylor series approx.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

iD= f (VBS)—Taylor series approx.

ID reduces
Effect of Body Bias Vsb
Id Vsb1 Vsb2 Vsb3

Vt1 Vt2 Vt3

Vgs

Vsb1 < Vsb2 < Vsb3

Anu Gupta BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 1 𝑊 2
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 1 + λ𝑉𝐷𝑆
2 𝐿

𝒅𝒊𝑫 𝒅𝒊𝑫
𝒈𝒎𝒃 =+ | 𝒂𝒕 𝑸 𝒑𝒐𝒊𝒏𝒕 = − | 𝒂𝒕 𝑸 𝒑𝒐𝒊𝒏𝒕
𝒅𝒗𝑩𝒔 𝒅𝒗𝑺𝑩
 𝜸
𝒈𝒎𝒃 = 𝒈𝒎
𝟐 𝟐∅𝑭 + 𝑽𝑺𝑩
𝒈𝒎𝒃 ≈ χ𝒈𝒎

𝜸= body bias coeff. parameter

Summary

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

SPICE Model parameters– λ, ϒ
Temperature effects

Vt, K’ , µ are temperature sensitive

Vt reduces at a rate of 2mv per degree rise in

temp.

Breakdown---

Oxide breakdown, punch through

Anu Gupta BITS Pilani, Pilani Campus

AC analysis of CSA

1. Small signal parameters expression

2. Small signal model of CSA

BITS Pilani, Pilani Campus

Model--Separating, ac and DC
operations -- (Active region )
Idsat

I D  K ' VGS  VT 0  1  VDS 

W 2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Small signal model
Resistive load CSA

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Small signal model
Active load CSA

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

AC Model of CSA x
-- (Active region )
𝑾
𝒈𝒎 = 𝝁𝒏 𝑪𝒐𝒙 𝑽𝑮𝑺 − 𝑽𝑻
𝑳
𝟐
𝒓𝒐 =
𝑾 𝟐
𝝁𝒏 𝑪𝒐𝒙 𝑳 𝑽𝑮𝑺 − 𝑽𝑻 𝝀

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

End
 BITS Pilani
Pilani Campus

Bipolar Junction Transistor—

BJT NPN / PNP operation
Circuit Symbols and
Conventions

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Bipolar Junction Transistor

operation