EEE / INSTR F244

Microelectronic
Circuits
BITS Pilani
Anu Gupta
Pilani Campus
Previous class

• Types of amplifiers, 2 port networks models, ideal

conditions of input/ output impedances

• Specification ----Amplifier characterization parameters–

gain, bandwidth, distortion, power efficiency etc.

Next step

• Devices, operation, characteristics, region of operation,

operating point, small signal parameters, DC bias

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 Learning outcomes----
Questions you can answer

• Why devices BJT/ MOSFET needed in amplifier?

• How to configure an amplifier?

• How does device equations/ I-V characteristics help in

designing amplifiers? What are small signal parameters,
AC/ DC load line? How to get them from I-V characteristics?

• How to sketch VTC, CTC etc.?

• What are device capacitances of BJT/MOSFET ? How to find

their value?

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Learning outcomes-

• What is need of DC analysis? How to do it (techniques-

current/ voltage biasing, & circuits?)

• What is operating point stability? Why is it required? How

to achieve it?

• What is need of AC analysis ? How to do it (model)?

• What is the difference in AC equivalent circuit at low/

high frequency ranges?

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Class A, AB, B amplifier

Effect of Q point location on
output

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Angle of conduction

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Class A-- Q point location

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Class AB–
clipping of output waveform

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Class AB-----
Cross-over distortion
Because BJT/ MOSFET turns off below
cutin/ threshold voltage

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Class AB problem

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Class B

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Class C amplifier

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Summary- Types of amplifier

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 BITS Pilani
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Amplifier Design
Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device ,characteristics, VTC

4. Locate Q point on VTC, device characteristics, DC

load line

5. Set DC bias, Choose a DC bias circuit Design,

calculate component values

6. Analyze, check DC performance, Q point stability

7. Tweak parameter

8. Apply ac signal, Analyze ac performance, small

signal model Bits, pilani BITS Pilani, Pilani Campus
Task1---Device to act as
amplifier
• Device should have 3 terminals to get 2 port network (inpit
port/ output port)

• Device should have amplification ability ie any output

current or voltage parameter should amplify when small
input (current or voltage) is applied

• Which device fulfills both conditions???

BJT and MOSFET
Condition--- BJT ( active mode)
MOSFET (active mode)
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Active mode of BJT/ MOSFET
Amplification property

BJT------ emitter base junction--- forward bias

collector base junction--- reverse bias

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Forward Active mode of
MOSFET
MOSFET------ (saturation region of operation)

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 BITS Pilani
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Task-2—
MOSFET/ BJT amplifiers design
Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics, DC

load line

5. Set DC bias, Choose a DC bias circuit Design,

calculate component values

6. Analyze, check DC performance

7. Tweak parameter

8. Apply ac signal, Analyze ac performance, small

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signal model BITS Pilani, Pilani Campus
Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability,

Tweak parameter

8. Apply ac signal, Analyze ac performance, small

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signal model BITS Pilani, Pilani Campus
Choice of Input and Output
terminal
• 3 parameters---VGS, VDS, ID, (Vsb= for advanced
course)

ID α (VGS, VDS)
• ID---captures variation----output
• either VGS / VDS can be input
• but if VDS is input, no other terminal is available
for output
• so only VGS can be the input
• Now what should be Vds?

Anu Gupta BITS Pilani, Pilani Campus

 Types of amplifier

Amplifier classification----

• Based on signal type-----(Voltage amplifier, current

transconductance, trans resistance/impedance)

• Based on location of Q point--- (Clas A, B, AB,)

• Based on INPUT/ OUTPUT terminals of device—

MOSFET (CSA, CGA, CDA),

BJT (CEA, CBA, CCA)

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MOSFET—
Choice of Input and Output terminal

• 3 parameters---VGS, VDS, ID, (Vsb= for advanced course)

• ID α (VGS, VDS) ID---captures variation----output

• Either VGS / VDS can be input

• but if VDS can not be input, because Id is at drain
terminal
• so only Vgs can be the input (either gate or source)
• Now what should be Vds? output

Anu Gupta BITS Pilani, Pilani Campus

MOSFET Voltage amplifier topologies
Choice of Input and Output terminal

• Vg input, Vd output , source common terminal---- common

source amplifier

• Vs input, Vd output , gate common terminal (mean ?)---

common gate amplifier

• Vg input, Vs output , drain common terminal (?)----

common source amplifier

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 MOSFET Amplifier
Configuration1– input/ output port
Common source amplifier circuit

Anu Gupta
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 MOSFET Amplifier
Configuration2– input/ output port
Common gate amplifier circuit

Anu Gupta
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 MOSFET Amplifier
Configuration3– input/ output port
(Common Drain) Source follower amplifier circuit

Anu Gupta
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BJT amplifiers- CEA,CBA, Emitter follower

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability,

Tweak parameter

8. Apply ac signal, Analyze ac performance, small

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signal model BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Task3-- MOSFET Device

Operation / characteristics
MOSFET
structure

• Trans-conductance device
• gm ----defines gain
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Symbols–
NMOS/ PMOS

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
MOSFET
operation

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  ox A
Oxide capacitance Cox 
t ox

ε0 = Relative Permittivity of a Vacuum = 8.854 × 10-12 F/m;

εr = Relative Permittivity of Dielectric (SiO2)=4;

Permittivity is the measure of a material's ability to store an electric field in

the polarization of the medium.

In standard CMOS technologies of the last twenty years , tox

is about fifty times lower than the minimum channel length
Lmin:

Lmin=180 nm, tox=3.6 nm ~ 4nm 

for Cox= 1 µF, A = 11.29 x 1013 nm2

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MOSFET current equations

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ID vs. VGS- (transfer characteristic)

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Effect of changing aspect ratio
(W/L)

(W/L)2 > (W/L)1

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BITS, Pilani, Anu Gupta
ID vs. VDS

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PMOS/ NMOS

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Correct PMOS current
equations

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Active Region

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MOSFET
Device capacitances
CGS
CGD
CDB
CSB

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BJT – current, Capacitances,
Cπ, Cμ

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance

8. Tweak parameter

9. Apply ac signal, Analyze ac performance, small Bits, pilani

signal model BITS Pilani, Pilani Campus

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Task4- locate Q point of Amplifier (CSA)

DC operation--Operating/ Quiescent (Q) point
How to define Q point?

Set of 3 parameters:

MOSFET—𝐼𝐷 , 𝑉𝐷𝑆 , 𝑉𝐺𝑆 typically Vds= half of Vdd

BJT---- (𝐼𝐶 , 𝑉𝐶𝐸 , 𝑉𝐵𝐸 )

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Why to set DC bias?

Reason1---- signal is of few millivolt (5 mV sinusoid). This

will not be sufficient to turn on MOSFET/ BJT

Reason2-- Device should be made to operate in a region

(linear/ active) where maximum gain can be obtained

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Region of operation
(Q) point choice
Max gain-------MAX IDRD------------MAX ID
Min distortion (linear operation),Q-point stability
Easy Controllability of Id
ID= f (VGS, VDS)
1. LINEAR REGION- small signal approx. Less current,

ID varies with (VGS , VDS )---(extra variation)-Qpoint stability

less

2. SATURATION REGION

ID= f (VGS)------Max current, ID captures variations of VGS

faithfully, high resistance, ID varies with VGS only
Anu Gupta BITS Pilani, Pilani Campus
Where to set DC bias?
Class A operation
1. Which is maximum gain region (linear/ active)? ---Active
region
2. Where to locate Q point in chosen region ?--- middle
of active region range
3. Which Vgs graph should be selected???? Use DC load
line

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Intrinsic (max.) gain of
MOSFET
𝒗𝒅𝒔 = 𝒈𝒎 𝒓𝒐 𝒗𝒈𝒔 ;
𝑣𝑑𝑠
𝐢𝐧𝐭𝐫𝐢𝐧𝐬𝐢𝐜 𝐠𝐚𝐢𝐧 = 𝑔𝑚 𝑟𝑜
𝑣𝑔𝑠
𝒖𝑨
𝒊𝒇 𝒈𝒎 = 𝟏𝟎𝟎 , 𝒓𝒐 = 𝟏𝟎𝟎 𝐌 𝐨𝐡𝐦, 𝒕𝒉𝒆𝒏 𝒈𝒎 𝒓𝒐 =100
𝑽

𝒈𝒎- max. in active region, 𝒓𝒐 − 𝐦𝐚𝐱 𝒊𝒏 𝒂𝒄𝒕𝒊𝒗𝒆 𝒓𝒆𝒈𝒊𝒐𝒏

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Intrinsic (max.) gain of BJT

𝑣𝑏𝑒 = 𝑔𝑚 𝑟𝑜 𝑣𝑐𝑒 ;
𝑣𝑏𝑒
𝐢𝐧𝐭𝐫𝐢𝐧𝐬𝐢𝐜 𝐠𝐚𝐢𝐧 = 𝒈𝒎 𝒓𝒐
𝑣𝑐𝑒
𝒈𝒎 , 𝒓𝒐 𝒆𝒔𝒕𝒊𝒎𝒂𝒕𝒆 ? ? ?

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Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance

8. Tweak parameter

9. Apply ac signal, Analyze ac performance, small

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signal model BITS Pilani, Pilani Campus
 BITS Pilani
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Task 5---DC Load Line

Q point location on VTC

Q point location on MOSFET

characteristics????????

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 Actual operating region
of amplifier on voltage
Transfer Curve as Vin>=
Vin- VTN

𝑽𝑮𝑺 − 𝑽𝑻
linear
DC Load line for resistive load

The load line, superimposed on the transistor

characteristics, can be used to visualize the
bias condition and operating mode of the
transistor
Impact of changing Rd
Load line shifts

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Why Vds
half???
• Class A

• Class AB
Vov.=0.2 V

• Class B

Class A- Q point--- 𝑰𝑫 , 𝑽𝑮𝑺 , 𝑽𝑫𝑺 = 𝟏𝟐 𝑽𝑫𝑫 nearly

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Q point on Output charac.—
load line
Corresponds to nearly center of VTC
Vdd/ Rd

Vdd

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 Q point on Output charac
Signal swing on load line

I2

I1

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Q point on Transfer charac.

I2
Id=1 mA

I1

-2mV
2mV Anu Gupta BITS Pilani, Pilani Campus
Typical values of 𝑽𝑫𝑺,𝑸, 𝑽𝑮𝑺,𝑸

MOSFET:
𝐼𝐷𝑆,𝑄 = 𝑑𝑒𝑝𝑒𝑛𝑑𝑠 𝑜𝑛 𝑔𝑎𝑖𝑛 𝑜𝑟 𝑝𝑜𝑤𝑒𝑟 𝑐𝑜𝑛𝑠𝑢𝑚𝑝𝑡𝑖𝑜𝑛 𝑠𝑝𝑒𝑐𝑠.
𝑉𝐷𝑆,𝑄 ≈ ℎ𝑎𝑙𝑓 𝑜𝑓 𝑉𝐷𝐷
𝑉𝐺𝑆,𝑄 = 𝑉𝑇 + 𝑉𝑜𝑣 ; (𝑉𝑜𝑣 ≈0.2 V)

BJT:
𝐼𝐶,𝑄 = 𝑑𝑒𝑝𝑒𝑛𝑑𝑠 𝑜𝑛 𝑔𝑎𝑖𝑛 𝑜𝑟 𝑝𝑜𝑤𝑒𝑟 𝑐𝑜𝑛𝑠𝑢𝑚𝑝𝑡𝑖𝑜𝑛 𝑠𝑝𝑒𝑐𝑠.
𝑉𝐶𝐸,𝑄 ≈ ℎ𝑎𝑙𝑓 𝑜𝑓 𝑉𝐶𝐶
𝑉𝐵𝐸,𝑄 = 𝑉𝛾 + ; typically around (0.5- 0.7 )V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Aim
Problem statement---Design an amplifier of gain 30 v/v

Sub tasks--

1. Choose the device (MOS , BJT)

2. Type of amplifier using (MOS , BJT)

3. Understand device characteristics

4. Locate Q point on VTC, device characteristics,

5. DC load line

6. Set DC bias, Choose a DC bias circuit Design,

calculate component values

7. Analyze, check DC performance, Q-point stability,

Tweak parameter

8. Apply ac signal, Analyze ac performance, small

signal model Bits, pilani
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 BITS Pilani
Pilani Campus

DC Bias circuit—
Types
DC bias circuit

1. Voltage bias (set VGS, VDS)

 Potential divider bias (2 variations)
 Drain to gate feedback bias (MOSFET)/ collector
to base feedback bias (BJT)

2. Current bias (set ID)

 Current mirror circuit

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Potential divider bias circuit
2 variations

𝐼𝐷𝑆,𝑄 = 1𝑚𝐴 𝐼𝐷𝑆,𝑄 = 0.5𝑚𝐴

𝑉𝐷𝑆,𝑄 = 7 𝑉 𝑉𝐷𝑆,𝑄 = 5 𝑉
𝑉𝐺𝑆,𝑄 = 3.5𝑉 𝑉𝐺𝑆,𝑄 = 2𝑉

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 Potential divider bias 1
Q point, 𝐼𝐷𝑄 = 1𝑚𝐴
𝑉𝐷𝑆,𝑄 = 7𝑉,
𝑉𝐺𝑆,𝑄 = 3.5 𝑉
10um technology
𝑉𝑇 = 1 𝑉
𝑢𝐴
𝜇𝑛 𝐶𝑜𝑥 = 100 2
𝑉

7𝑀
𝑉𝐺𝑆 = 𝟑. 𝟓 𝑽 = 𝑉𝐷𝐷
7 + 23 𝑀

𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝑉𝐷𝑆 ; 𝑅𝐷 = 𝟖 𝑲𝜴;

1 𝑊 2 𝑾 𝟑𝟐𝒖𝒎
𝐼𝐷 = 𝟏𝒎𝑨 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 → 𝑳
= 𝟑. 𝟐 =
𝟏𝟎𝒖𝒎
2 𝐿
 CSA- Q point on Output charac.
Signal swing on load line

I2

Id=1 mA

I1

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Potential divider bias2 -- (IDS, V DS, VGS )
Potential divider bias with Rs

𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆
𝑅1
𝑉𝐺𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝑆
𝑅1 + 𝑅2
10um technology
𝑉𝑇 = 1 𝑉
𝑢𝐴
𝜇𝑛 𝐶𝑜𝑥 = 50 2
𝑉

𝐼𝐷𝑆,𝑄 = 0.5𝑚𝐴
𝑉𝐷𝑆,𝑄 = 5 𝑉
𝑉𝐺𝑆,𝑄 = 2𝑉
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Potential divider bias,
capacitive coupling

Capacitive coupling
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