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Problem 36

The document is a final report submitted for the course EEE F313 - Analog & Digital VLSI Design at Birla Institute of Technology and Science, Pilani. It includes the design of a CMOS circuit to realize a specific logic function and a synchronous mod-10 counter using D flip-flops, detailing schematic diagrams, Verilog code, and simulation results. The report is authored by Aarohi Uniyal, Kara Bhatia, and Kavya Goel under the supervision of Dr. Anu Gupta.

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6 views

Problem 36

The document is a final report submitted for the course EEE F313 - Analog & Digital VLSI Design at Birla Institute of Technology and Science, Pilani. It includes the design of a CMOS circuit to realize a specific logic function and a synchronous mod-10 counter using D flip-flops, detailing schematic diagrams, Verilog code, and simulation results. The report is authored by Aarohi Uniyal, Kara Bhatia, and Kavya Goel under the supervision of Dr. Anu Gupta.

Uploaded by

AAROHI UNIYAL
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DIGITAL ASSIGNMENT

BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI

FINAL REPORT
SUBMITTED IN PARTIAL FULFILLMENT OF COURSE
EEE F313- ANALOG & DIGITAL VLSI DESIGN
FIRST SEMESTER 2024-25

BY
Aarohi Uniyal 2021B1A31316P
Kara Bhatia 2021B5A31207P
Kavya Goel 2021B4A32499P

SUBMITTED TO
Dr. Anu Gupta
Professor, Department of Electrical and Electronics engineering
Table of Contents

A] Design of CMOS to realize given logic function


​ A.1] Schematic of CMOS circuit
​ A.2] Hand Drawn Layout
​ A.3] Simulation of Hand Drawn Layout
​ A.4] DSCH Drawn Layout
​ A.5] Simulation of DSCH Drawn Layout
B] Design of synchronous mod-10 counter using D flip-flops
​ B.1] State Diagram and Truth Table
​ B.2] Verilog Code
B.3] Testbench
B.4] Command Prompt Output
B.5] Waveform Output using GTKWave
A] Design a CMOS logic to realize the logic function

A.1]

Schematic of CMOS circuit

​
A.2]

Manual Layout
Euler minimization has been used in the secondary circuit. (Represented by the top N-Well and
its PMOS and the NMOS above Vss ground.
The W/L ratio for:
N-MOS in primary circuit: 1
P-MOS in primary circuit: 2
N-MOS in secondary circuit: 2
P-MOS in secondary circuit: 6

μ ratio for both primary and secondary circuits maintained at 2.


A.3]

Simulation of Manually drawn Layout


The output (mentioned as Y here) gives values exactly according to the following truth table:
A B C D Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 1
A.4]

Layout Made by DSCH Tools


(Converted directly from DSCH circuit file to Microwind Layout using the netlist)

A.5]

Simulation of DSCH generated Layout


B] Design a synchronous mod-10 counter using D flip flops whose counting
sequence is 0000,1001,0111,0010,1011,0100,1101,1000,0110,1111

B.1] Truth Table and State Diagram


B.2] Verilog Code-
module D_ff(input wire D, input wire clk, input wire rst, output reg Q);
​ always @(posedge clk) begin
​ ​ if(rst) begin
​ ​ ​ Q<=1'b0;
​ ​ end
​ ​ else begin
​ ​ ​ Q<=D;
​ ​ end
​ end
endmodule

module xnor_gate(output wire c,input wire a, input wire b);


​ assign c = ~(a^b);
endmodule

module or_gate(output wire c,input wire a, input wire b);


​ assign c = a|b;
endmodule

module xor_gate(output wire c,input wire a, input wire b);


​ assign c = a^b;
endmodule

module and_gate(output wire c,input wire a, input wire b);


​ assign c = a&b;
endmodule

module not_gate(output wire b, input wire a);


​ assign b = ~a;
endmodule

module and3_gate(output wire d, input wire a, input wire b, input wire c);
​ assign d = a&b&c;
endmodule

module mycircuit(input wire clk, input wire rst, output Qa, output Qb, output Qc, output Qd);
​ wire e, f, g, h, i, j, k, l, m, n, o, p, q, r, s;
​ and_gate AND1(e, Qc, ~Qd);
​ and_gate AND2(f, ~Qa, ~Qb);
​ and_gate AND3(g, Qb, ~Qc);
​ or_gate OR1(h, e, f);
​ or_gate OR2(i, g, h);
​ D_ff A(i, clk, rst, Qa);
​ and_gate AND4(j, Qa, ~Qd);
​ xor_gate XOR1(k, Qb, Qd);
​ or_gate OR3(l, j, k);
​ D_ff B(l, clk, rst, Qb);
​ and_gate AND5(m, ~Qa, Qc);
​ and3_gate AND3_1(n, Qa, ~Qb, ~Qc);
​ or_gate OR4(o, m, n);
​ D_ff C(o, clk, rst, Qc);
​ and_gate AND6(p, ~Qa, ~Qc);
​ and3_gate AND3_2(q, ~Qb, ~Qc, Qd);
​ or_gate OR5(r, p, q);
​ or_gate OR6(s, e, r);
​ D_ff D(s, clk, rst, Qd);​
Endmodule

B.3] Verilog Code (testbench):


`timescale 1ns/1ps // Define time scale for simulation

module tb_mycircuit; // Testbench module

// Declare test bench variables


reg clk; // Clock signal
reg rst; // Reset signal
wire Qa, Qb, Qc, Qd; // Outputs of the counter

// Instantiate the design (DUT: Device Under Test)


mycircuit DUT (.clk(clk), .rst(rst), .Qa(Qa), .Qb(Qb), .Qc(Qc), .Qd(Qd));

// Generate clock signal: toggles every 5 ns


always begin
#5 clk = ~clk; // Toggle clock every 5ns, clock period = 10ns
end

// Initial block to provide stimulus


initial begin
​ $dumpfile("dump.vcd"); // Specifies the name of the VCD file
​ $dumpvars(0, tb_mycircuit); // Dumps all variables in the testbench to the VCD
file
// Initialize signals
clk = 0; // Initial clock value
rst = 1; // Start with reset active
​ #10
​ rst = 0;​

// Monitor changes in the counter's output


$monitor("At time %t: Qa = %b, Qb = %b, Qc = %b, Qd = %b", $time, Qa, Qb, Qc,
Qd);

// Run the simulation for 200ns


#300 $finish;
end
Endmodule

B.4] Command Prompt Output:


B.5] Waveform Output using GTKWave:

​ ​

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