SN 65 HVD 1040
SN 65 HVD 1040
SN65HVD1040
SLLS631E – APRIL 2007 – REVISED AUGUST 2015
TXD 1 Overtemperature
VCC (3)
8 STB
Sensor
10 A
Vcc (3) VCC/2 SPLIT (5)
Dominant
Time-Out
30 A
GND 2 Input
7 CANH
Logic
Driver
Sleep Mode
VCC 3 6 CANL
Output Wake Up
RXD 4 Logic
MUX
Filter 5 SPLIT
Bus Monitor
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD1040
SLLS631E – APRIL 2007 – REVISED AUGUST 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.14 Typical Characteristics ........................................... 8
2 Applications ........................................................... 1 8 Parameter Measurement Information ................ 10
3 Description ............................................................. 1 9 Detailed Description ............................................ 14
4 Revision History..................................................... 2 9.1 Overview ................................................................. 14
5 Description (continued)......................................... 3 9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 14
6 Pin Configuration and Functions ......................... 3
9.4 Device Functional Modes........................................ 15
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4 10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
7.2 ESD Ratings.............................................................. 4
10.2 Typical Application ............................................... 19
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 5 11 Power Supply Recommendations ..................... 25
7.5 Driver Electrical Characteristics ................................ 5 12 Layout................................................................... 25
7.6 Receiver Electrical Characteristics ........................... 6 12.1 Layout Guidelines ................................................. 25
7.7 Device Switching Characteristics.............................. 6 12.2 Layout Example .................................................... 26
7.8 Driver Switching Characteristics ............................... 6 13 Device and Documentation Support ................. 27
7.9 Receiver Switching Characteristics........................... 7 13.1 Community Resources.......................................... 27
7.10 Dissipation Ratings ................................................. 7 13.2 Trademarks ........................................................... 27
7.11 Supply Current ........................................................ 7 13.3 Electrostatic Discharge Caution ............................ 27
7.12 Split-Pin Characteristics......................................... 7 13.4 Glossary ................................................................ 27
7.13 STB-Pin Characteristics......................................... 7 14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
Changes from Revision D (December 2008) to Revision E Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
5 Description (continued)
The STB input (pin 8) selects between two different modes of operation; high-speed or low-power mode. The
high-speed mode of operation is selected by connecting STB to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor
standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater
than 5 μs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may
then reactivate the device when it needs to transmit to the bus.
A dominant time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication
during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no
rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then
reset by the next rising edge on TXD.
The SPLIT output (pin 5) is available on the SN65HVD1040 as a VCC/2 common-mode bus voltage bias for a
split-termination network.
The SN65HVD1040 is characterized for operation from –40°C to 125°C.
D Package
8-Pin SOIC
(Top View)
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
TXD 1 I CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
GND 2 GND Device ground
VCC 3 Supply Transceiver 5-V supply
RXD 4 O CAN receive data output (LOW for dominant and HIGH for recessive bus states)
SPLIT 5 O Reference output voltage (VCC/2)
CANL 6 I/O Low level CAN bus line
CANH 7 I/O High level CAN bus line
Mode select: Strong pulldown to GND for high speed mode, strong pullup to VCC for low
STB 8 I
power mode.
7 Specifications
7.1 Absolute Maximum Ratings
See Note (1)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6 & 7.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.
(1) The device under test shall not signal a wake-up condition with dominant pulses shorter than tBUS (min) and shall signal a wake-up
condition with dominant pulses longer than tBUS (max). Dominant pulses with a length between tBUS (min) and tBUS (max) may lead to a
wakeup.
(1) Extended operation in thermal shutdown may affect device reliability, see the Thermal Shutdown.
130 150
VCC = 5 V
120 140
−40 0 25 70 125 −40 0 25 70 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air Figure 2. Dominant-to-Recessive Loop Time vs Free-Air
Temperature (Across Vcc) Temperature (Across Vcc)
Figure 3. Supply Current (RMS) vs Signaling Rate Figure 4. Driver Low-Level Output Voltage vs Low-Level
Output Current
-80
TA = 25 C,
VCC = 5 V,
I OH − High-Level Output Current − mA
-70 S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
-60
-50
-40
-30
-20
-10
-0
0 1 2 3 4 5
VOCANH − High-Level Output Voltage − V
Figure 5. Driver High-Level Output Voltage vs High-Level Figure 6. Driver Differential Output Voltage vs Free-Air
Output Current Temperature (Across Vcc)
Figure 7. Driver Output Current vs Supply Voltage Figure 8. Receiver Output Voltage vs Differential Input
Voltage
DB mV
Figure 9. Frequency Spectrum of Common-Mode Emissions Figure 10. Direct Power Injection (DPI) Response vs
Frequency
TXD
II VOD RL VO(CANH) VO(CANH) + VO(CANL)
VI 2
Dominant
3.5 V VO(CANH)
Recessive
2.5 V
1.5 V VO(CANL)
330 +1%
CANH
TXD 60 +1%
0V VOD
+
_ −2 V 3 VTEST 3 7 V
STB
CANL 330 +1%
CANH
VCC
VCC VCC
VI 2 2
TXD RL = 60 W
+1‘% VO CL = 100 pF +20% 0V
(see Note B)
VI tPLH tPHL
V O(D)
90%
STB 0.9 V
(see Note A) CANH VO 0.5 V
10%
VO(R)
tr tf
CANH
V I (CANH) RXD
IO
VI(CANH) + VI(CANL) V ID
VIC =
2
VO
V I (CANL) CANL
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6 ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
DUT
CANH
TXD VCC
0V C 60W ±1% VI
L 50%
0V
STB CANL
VI VOH
NOTE: CL = 100 pF
Includes Instrumentation VO 50%
RXD
and Fixture Capacitance ten VOL
+ Within ±20%
VO
− 15 pF ±20%
CANH
27 W +1% VOC(PP)
TXD
V
I
CANL 47 nF VOC
VO (CANH) + VO (CANL)
STB
+20% VOC =
27 W +1% 2
All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
Figure 18. Peak-To-Peak Common Mode Output Voltage Test and Waveform
DUT
CANH
TXD VCC
C 60 W 1%
L TXD 50%
Input
STB 0V
CANL
tloop2 tloop1
NOTE: CL = 100 pF
VOH
RXD Includes Instrumentation
and Fixture Capacitance 50% 50%
RXD Output
+ Within ±20%
VOL
VO
− 15 pF 20%
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.
CANH VCC
VI
TXD
RL = 60 W +1% VO 0V
CL VOD(D)
VI (see Note B)
VO 900 mV
CANL 500 mV
(see Note A) STB
0V
tdom
All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
VCC
CANH
STB 3.5 V
RXD IO VI 2.65 V
VI 1.5 V
CANL 0.7 s tBUS
(see Note A) 1.5 V (see Note B) CL VO
VOH
VO
400 mV
V OL
A. For VI bit width ≤ 0.7 μs, VO = VOH. For VII bit width ≥ 5 μs, VO = VOL. VI input pulses are supplied from a generator
with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B. CL = 15 pF includes instrumentation and fixture capacitance within ±20%.
IOS IOS(SS)
IOS(P)
TXD CANH
0 V or VCC 200 ms
0V
STB 12 V
CANL VIN −12 V or 12 V
Vin
0V
or 10 ms
0V
Vin
−12 V
CANH
TXD 60 W ± 1%
VI
60 W ± 1% 4.7 nF VSYM = +VO
VO(CANH) (CANL)
± 20%
STB CANL
V O (CANL) VO (CANH)
9 Detailed Description
9.1 Overview
The SN65HVD1040 CAN bus transceiver meets or exceeds the ISO 11898 standard as a high-speed controller
area network (CAN) bus physical layer device. The device is designed to interface between the differential bus
lines in controller area network and the CAN protocol controller at data rates up to 1 Mbps.
VCC (3)
8
Over Temperature
VCC (3) STB
Sensor
10 A
Vcc (3) VCC/2 SPLIT (5)
Dominant
Time-Out
30 A
7
1 Input
CANH
TXD Logic
Driver
Sleep Mode
6
CANL
RXD 4 Output
Logic
MUX
Wake Up
Filter
Bus Monitor
NOTE
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate on the device. The CAN protocol allows a maximum of
eleven successive dominant bits (on TXD) for the worst case, where five successive
dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO
minimum, limits the minimum data rate. Calculate the minimum transmitted data rate
using: Minimum Data Rate = 11 / tTXD_DTO.
9.3.4 SPLIT
A reference voltage (VCC/2) is available through the SPLIT outpit pin. The SPLIT voltage should be tied to the
common mode point in a split termination network, hence the pin name, to help stabilize the output common
mode voltage. See Figure 29 for more application specific information on properly terminating the CAN bus.
4. 3 k W 15 W
Input Output
6V 6V
10 k W 10 k W
20 k W 20 k W
Input Input
40 V 10 kW 40 V 10 k W
4. 3 k W Output
Input
40 V
6V
SPLIT Output
Vcc
2kW
Output
2k W
40 V
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time, t
Recessive Dominant Recessive
Logic H Logic L Logic H
Figure 25. Bus States
CANH
VCC/2
RXD
CANL
CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the link
layer portion of the CAN protocol. The different nodes on the network are typically connected through the use of
a 120-Ω characteristic impedance twisted-pair cable with termination on both ends of the bus.
VCC
3
Node n
Node 1 Node 2 Node 3 (With Termination)
MCU or DSP
MCU or DSP MCU or DSP MCU or DSP
CAN
CAN CAN CAN Controller
Controller Controller Controller
SN65HVD257 CAN
SN65HVD1040 CAN SN65HVD1050 CAN SN65HVD233 CAN Transceiver
Transceiver Transceiver Transceiver
RTERM
RTERM
CANH CANH
RTERM/2
CAN CAN
Transceiver RTERM
Transceiver
RTERM/2
CANL CANL
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120 Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the standard’s –2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The SN65HVD1040 enhances the standard’s insurance of
data integrity with an extended –12 V to 12 V range of common-mode operation.
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 30, the differential
signal changes logic states in two places on the display, producing an “eye.” Instead of viewing only one logic
crossing on the scope, an entire “bit” of data is brought into view. The resulting eye pattern includes all of the
effects of systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces and cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the SN65HVD1040 mitigate most all sources of signal corruption, and when
used with a quality shielded twisted-pair cable, help insure data integrity.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW 75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
Transient
Clamp
Voltage
SN65HVD1040
Transient
Current
12 Layout
NOTE
High frequency current follows the path of least inductance and not the path of least
resistance.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device. An example placement of the Transient Voltage
Suppression (TVS) device indicated as D1 (either bidirectional diode or varistor solution) and bus filter capacitors
C5 and C7 are shown in Figure 34.
The bus transient protection and filtering components should be placed as close to the bus connector, J1, as
possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.
Bus termination: Figure 34 shows split termination. This is where the termination is split into two resistors, R5
and R6, with the center or split tap of the termination connected to ground through capacitor C6. Split termination
provides common mode filtering for the bus. When termination is placed on the board instead of directly on the
bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal
integrity issues of the bus is not properly terminated on both ends.
Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples
C2, C3 (VCC). Use at least two vias for VCC and ground connections of bypass capacitors and protection devices
to minimize trace and via inductance.
To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3, and R4.
To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1
and C4.
Because the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10-
kΩ pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during
transient events.
Pin 1: If an open-drain host processor is used to drive the TXD pin of the device an external pullup resistor
between 1 kΩ and 10 kΩ should be used to drive the recessive input state of the device.
Pin 5: SPLIT should be connected to the center point of a split termination scheme to help stabilize the common
mode voltage to VCC/2. If SPLIT is unused it should be left floating.
Pin 8: This pin is shown assuming the mode pin, STB, will be used. If the device will only be used in normal
mode, R3 is not needed and the pads of C4 could be used for the pulldown resistor to GND.
C5
GND 2 7 R5
U1
D1
J1
SN65HVD1040 SPLIT C6
C2
C3
VCC R6
C7
3 6
RXD R2 4 5 R4
Figure 34. Layout Recommendation
13.2 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 28-Aug-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN65HVD1040DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP1040 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2024
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive : SN65HVD1040-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Feb-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Feb-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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