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SN 65 HVD 1040

The SN65HVD1040 is a low-power CAN bus transceiver designed for applications requiring robust communication in harsh environments, featuring ±12 kV ESD protection and a low-current standby mode. It supports signaling rates up to 1 Mbps and includes various protective functions such as bus-fault protection and a dominant time-out feature. The device is suitable for a wide range of applications including medical imaging, HVAC, and industrial automation.

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0% found this document useful (0 votes)
5 views35 pages

SN 65 HVD 1040

The SN65HVD1040 is a low-power CAN bus transceiver designed for applications requiring robust communication in harsh environments, featuring ±12 kV ESD protection and a low-current standby mode. It supports signaling rates up to 1 Mbps and includes various protective functions such as bus-fault protection and a dominant time-out feature. The device is suitable for a wide range of applications including medical imaging, HVAC, and industrial automation.

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Product Sample & Technical Tools & Support &

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SN65HVD1040
SLLS631E – APRIL 2007 – REVISED AUGUST 2015

SN65HVD1040 Low-Power CAN Bus Transceiver With Bus Wakeup


1 Features 3 Description

1 Improved Drop-in Replacement for the TJA1040 The SN65HVD1040 meets or exceeds the
specifications of the ISO 11898 standard for use in
• ±12 kV ESD Protection applications employing a Controller Area Network
• Low-Current Standby Mode With Bus Wakeup: (CAN). As a CAN bus transceiver, the SN65HVD1040
5 μA Typical device provides differential transmit and receive
• Bus-Fault Protection of –27 V to 40 V capability for a CAN controller at signaling rates of up
to 1 Mbps (1).
• Rugged Split-Pin Bus Stability
• Dominant Time-Out Function Designed for operation in especially harsh
environments, the device features ±12 kV ESD
• Power-Up/Down Glitch-Free Bus Inputs and protection on the bus and split pins, cross-wire,
Outputs overvoltage and loss of ground protection from –27 V
– High Input Impedance With Low VCC to 40 V, overtemperature shutdown, a –12 V to 12 V
– Monotonic Outputs During Power Cycling common-mode range, and will withstanding voltage
transients from –200 V to 200 V according to ISO
• DeviceNet™ Vendor ID Number 806 7637.
2 Applications Device Information(1)
• CAN Bus Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• Battery-Operated Applications SN65HVD1040 SOIC (8) 4.90 mm × 3.91 mm
• Hand-Held Diagnostics (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Medical Scanning and Imaging
• HVAC
• Security Systems
• Telecom Base Station Status and Control
• SAE J1939 Standard Data Bus Interface
• NMEA 2000 Standard Data Bus Interface
• ISO 11783 Standard Data Bus Interface
• Industrial Automation (1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
– DeviceNet Data Buses bps (bits per second).

SN65HVD1040 Block Diagram


VCC (3)

TXD 1 Overtemperature
VCC (3)
8 STB
Sensor
10 A
Vcc (3) VCC/2 SPLIT (5)
Dominant
Time-Out

30 A
GND 2 Input
7 CANH
Logic
Driver

Sleep Mode

VCC 3 6 CANL

Output Wake Up
RXD 4 Logic
MUX
Filter 5 SPLIT
Bus Monitor

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65HVD1040
SLLS631E – APRIL 2007 – REVISED AUGUST 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.14 Typical Characteristics ........................................... 8
2 Applications ........................................................... 1 8 Parameter Measurement Information ................ 10
3 Description ............................................................. 1 9 Detailed Description ............................................ 14
4 Revision History..................................................... 2 9.1 Overview ................................................................. 14
5 Description (continued)......................................... 3 9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 14
6 Pin Configuration and Functions ......................... 3
9.4 Device Functional Modes........................................ 15
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4 10 Application and Implementation........................ 18
10.1 Application Information.......................................... 18
7.2 ESD Ratings.............................................................. 4
10.2 Typical Application ............................................... 19
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 5 11 Power Supply Recommendations ..................... 25
7.5 Driver Electrical Characteristics ................................ 5 12 Layout................................................................... 25
7.6 Receiver Electrical Characteristics ........................... 6 12.1 Layout Guidelines ................................................. 25
7.7 Device Switching Characteristics.............................. 6 12.2 Layout Example .................................................... 26
7.8 Driver Switching Characteristics ............................... 6 13 Device and Documentation Support ................. 27
7.9 Receiver Switching Characteristics........................... 7 13.1 Community Resources.......................................... 27
7.10 Dissipation Ratings ................................................. 7 13.2 Trademarks ........................................................... 27
7.11 Supply Current ........................................................ 7 13.3 Electrostatic Discharge Caution ............................ 27
7.12 Split-Pin Characteristics......................................... 7 13.4 Glossary ................................................................ 27
7.13 STB-Pin Characteristics......................................... 7 14 Mechanical, Packaging, and Orderable
Information ........................................................... 27

4 Revision History
Changes from Revision D (December 2008) to Revision E Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

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5 Description (continued)
The STB input (pin 8) selects between two different modes of operation; high-speed or low-power mode. The
high-speed mode of operation is selected by connecting STB to ground.
If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor
standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater
than 5 μs on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may
then reactivate the device when it needs to transmit to the bus.
A dominant time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication
during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no
rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then
reset by the next rising edge on TXD.
The SPLIT output (pin 5) is available on the SN65HVD1040 as a VCC/2 common-mode bus voltage bias for a
split-termination network.
The SN65HVD1040 is characterized for operation from –40°C to 125°C.

6 Pin Configuration and Functions

D Package
8-Pin SOIC
(Top View)

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
TXD 1 I CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
GND 2 GND Device ground
VCC 3 Supply Transceiver 5-V supply
RXD 4 O CAN receive data output (LOW for dominant and HIGH for recessive bus states)
SPLIT 5 O Reference output voltage (VCC/2)
CANL 6 I/O Low level CAN bus line
CANH 7 I/O High level CAN bus line
Mode select: Strong pulldown to GND for high speed mode, strong pullup to VCC for low
STB 8 I
power mode.

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7 Specifications
7.1 Absolute Maximum Ratings
See Note (1)

MIN MAX UNIT


VCC Supply voltage (2) –0.3 7 V
VI(bus) Voltage at any bus terminal (CANH, CANL, SPLIT) –27 40 V
IO(OUT) Receiver output current –20 20 mA
Voltage input, transient pulse (3), (CANH, CANL, SPLIT) –200 200 V
VI Voltage input (TXD, STB) –0.5 6 V
TJ Junction temperature –55 170 °C
Tstg Storage temperature –40 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with ISO 7637, test pulses 1, 2, 3a, 3b, 5, 6 & 7.

7.2 ESD Ratings


VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS- Bus terminals vs GND ±12000
001 (1)
All pins ±4000
Electrostatic
V(ESD) Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
discharge
Machine model (MM) ANSI/ESDS5.2-1996 ±200
IEC Contact Discharge (IEC 61000-4-2) Bus terminals vs GND ±6000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions


MIN NOM MAX UNIT
VCC Supply voltage 4.75 5.25 V
VI or VIC Voltage at any bus terminal (separately or common mode) –12 (1) 12 V
VIH High-level input voltage 2 5.25 V
TXD, STB
VIL Low-level input voltage 0 0.8 V
VID Differential input voltage –6 6 V
Driver –70
IOH High-level output current mA
Receiver –2
Driver 70
IOL Low-level output current mA
Receiver 2
tSS Maximum pulse width to remain in standby 0.7 μs
TJ Junction temperature –40 150 °C

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

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7.4 Thermal Information


SN65HVD1040
THERMAL METRIC (1) D (SOIC) UNIT
8 PINS
Low-K Thermal Resistance (2) 211 °C/W
RθJA Junction-to-ambient thermal resistance
High-K Thermal Resistance 131 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 79 °C/W
RθJB Junction-to-board thermal resistance 53.9 °C/W
ψJT Junction-to-top characterization parameter 15.4 °C/W
ψJB Junction-to-board characterization parameter 53.2 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages.

7.5 Driver Electrical Characteristics


over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Bus output voltage CANH VI = 0 V, STB at 0 V, RL = 60 Ω, See Figure 11 and 2.9 3.4 4.5
VO(D) V
(Dominant) CANL Figure 12 0.8 1.75
VO®) Bus output voltage (Recessive) VI = 3 V, STB at 0 V, See Figure 11 and Figure 12 2 2.5 3 V
RL = 60 Ω, STB at VCC, See Figure 11 and
VO Bus output voltage (Standby) –0.1 0.1 V
Figure 12
VI = 0 V, RL = 60 Ω, STB at 0 V, See Figure 11 and
1.5 3
Figure 12, and Figure 13
VOD(D) Differential output voltage (Dominant) V
VI = 0 V, RL = 45 Ω, STB at 0 V, See Figure 11 and
1.4 3
Figure 12
Output symmetry (Dominant or 0.9 ×
VSYM STB at 0 V, See Figure 12 and Figure 23 VCC 1.1×VCC V
Recessive) [ VO(CANH) + VO(CANL) ] VCC
VI = 3 V, RL = 60 Ω, STB at 0 V, See Figure 11 and
–0.012 0.012
VOD®) Differential output voltage (Recessive) Figure 12 V
VI = 3 V, STB at 0 V, No Load –0.5 0.05
Common-mode output voltage
VOC(D) 2 2.3 3
(Dominant)
STB at 0 V, See Figure 18 V
Peak-to-peak common-mode output
VOC(pp) 0.3
voltage
IIH High-level input current, TXD input VI at VCC –2 2 μA
IIL Low-level input current, TXD input VI at 0 V –50 –10 μA
IO(off) Power-off TXD Leakage current VCC at 0 V, TXD at 5 V 1 μA
VCANH = –12 V, CANL Open, See Figure 22 –120 –72
Short-circuit steady-state output VCANH = 12 V, CANL Open, See Figure 22 0.36 1
IOS(ss) mA
current VCANL = –12 V, CANH Open, See Figure 22 –1 –0.5
VCANL = 12 V, CANH Open, See Figure 22 71 120
See Input capacitance to ground in Receiver
CO Output capacitance
Electrical Characteristics.

(1) All typical values are at 25°C with a 5-V supply.

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7.6 Receiver Electrical Characteristics


over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Positive-going input threshold
VIT+ 800 900
voltage
High-speed STB at 0 V, see Table 1
Negative-going input threshold
VIT– mode 500 650 mV
voltage
Vhys Hysteresis voltage (VIT+ – VIT–) STB at VCC 100 125
VIT Input threshold voltage Standby mode STB at VCC 500 1150
VOH High-level output voltage IO = –2 mA, see Figure 16 4 4.6 V
VOL Low-level output voltage IO = 2 mA, see Figure 16 0.2 0.4 V
CANH or CANL = 5 V, VCC at 0 V,
II(off) Power-off bus input current 5 μA
TXD at 0 V
IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 μA
CI Input capacitance to ground, (CANH or CANL) TXD at 3 V, VI = 0.4 sin (4E6πt) + 2.5 V 20 pF
CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 10 pF
RID Differential input resistance TXD at 3 V, STD at 0 V 30 80
kΩ
RIN Input resistance, (CANH or CANL) TXD at 3 V, STD at 0 V 15 30 40
Input resistance matching
RI(m) VCANH = VCANL –3% 0% 3%
[1 – RIN (CANH) / RIN (CANL))] x 100%

(1) All typical values are at 25°C with a 5-V supply.

7.7 Device Switching Characteristics


over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
tloop1 Total loop delay, driver input to receiver output, Recessive to Dominant STB at 0 V, 90 230
ns
tloop2 Total loop delay, driver input to receiver output, Dominant to Recessive see Figure 19 90 230

7.8 Driver Switching Characteristics


over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 25 65 120
tPHL Propagation delay time, high-to-low-level output 25 45 120
tsk(p) Pulse skew (|tPHL – tPLH|) STB at 0 V, see Figure 14 25 ns
tr Differential output signal rise time 25
tf Differential output signal fall time 50
ten Enable time from silent mode to dominant See Figure 17 10 μs
tdom Dominant time-out See Figure 20 300 450 700 μs

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7.9 Receiver Switching Characteristics


over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tpLH Propagation delay time, low-to-high-level output 60 100 130
tpHL Propagation delay time, high-to-low-level output STB at 0 V, TXD at 3 V, See 45 70 130
ns
tr Output signal rise time Figure 16 8
tf Output signal fall time 8
Dominant time required on bus for wakeup from
tBUS STB at VCC Figure 21 0.7 5 μs
standby (1)

(1) The device under test shall not signal a wake-up condition with dominant pulses shorter than tBUS (min) and shall signal a wake-up
condition with dominant pulses longer than tBUS (max). Dominant pulses with a length between tBUS (min) and tBUS (max) may lead to a
wakeup.

7.10 Dissipation Ratings


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 60 Ω, S at 0 V,
PD Device Power Dissipation Input to TXD a 500kHz 50% duty-cycle 112 170 mW
square wave
(1)
TJS Junction Temperature, Thermal Shutdown 190 °C

(1) Extended operation in thermal shutdown may affect device reliability, see the Thermal Shutdown.

7.11 Supply Current


over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Dominant VI = 0 V, 60 Ω Load, STB at 0 V 50 70
Supply current, mA
ICC Recessive VI = VCC, STB at 0 V 6 10
VCC
Standby STB at VCC, VI = VCC 5 12 μA

7.12 Split-Pin Characteristics


over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Output voltage –500 μA < IO < 500 μA 0.3 × VCC 0.5 × VCC 0.7 × VCC V
IO(stb) Standby mode leakage current STB at 2 V, –12 V ≤ VO ≤ 12 V –5 5 μA

7.13 STB-Pin Characteristics


over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH High level input current STB at 2 V –10 0 μA
IIL Low level input current STB at 0 V –10 0 μA

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7.14 Typical Characteristics

t LOOP1− Recessive-to-Dominant Loop Time − ns 150 170

t LOOP2 − Dominant-to-Recessive Loop Time − ns


S at 0 V, S at 0 V,
RL = 60 W, RL = 60 W,
CL = 100 pF, CL = 100 pF,
145 165
Air Flow at 7 cf/m, Air Flow at 7 cf/m,
TXD Input is a 125 kHz, TXD Input is a 125 kHz,
50% Duty Cycle Pulse 50% Duty Cycle Pulse
140 160
VCC = 4.75 V
VCC = 5.25 V

135 155 VCC = 5 V

130 150
VCC = 5 V

125 145 VCC = 4.75 V


VCC = 5.25 V

120 140
−40 0 25 70 125 −40 0 25 70 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C
Figure 1. Recessive-to-Dominant Loop Time vs Free-Air Figure 2. Dominant-to-Recessive Loop Time vs Free-Air
Temperature (Across Vcc) Temperature (Across Vcc)

Figure 3. Supply Current (RMS) vs Signaling Rate Figure 4. Driver Low-Level Output Voltage vs Low-Level
Output Current
-80
TA = 25 C,
VCC = 5 V,
I OH − High-Level Output Current − mA

-70 S at 0 V,
TXD Input is a 125 kHz
1% Duty Cycle Pulse
-60

-50

-40

-30

-20

-10

-0
0 1 2 3 4 5
VOCANH − High-Level Output Voltage − V

Figure 5. Driver High-Level Output Voltage vs High-Level Figure 6. Driver Differential Output Voltage vs Free-Air
Output Current Temperature (Across Vcc)

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Typical Characteristics (continued)

Figure 7. Driver Output Current vs Supply Voltage Figure 8. Receiver Output Voltage vs Differential Input
Voltage
DB mV

Figure 9. Frequency Spectrum of Common-Mode Emissions Figure 10. Direct Power Injection (DPI) Response vs
Frequency

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8 Parameter Measurement Information


IO(CANH)

TXD
II VOD RL VO(CANH) VO(CANH) + VO(CANL)
VI 2

STB IO(CANL) VOC


VO(CANL)

Figure 11. Driver Voltage, Current, and Test Definition

Dominant
3.5 V VO(CANH)

Recessive
2.5 V

1.5 V VO(CANL)

Figure 12. Bus Logic State Voltage Definitions

330  +1%
CANH

TXD 60  +1%
0V VOD
+
_ −2 V 3 VTEST 3 7 V
STB
CANL 330  +1%

Figure 13. Driver VOD Test Circuit

CANH
VCC
VCC VCC
VI 2 2
TXD RL = 60 W
+1‘% VO CL = 100 pF +20% 0V
(see Note B)
VI tPLH tPHL
V O(D)
90%
STB 0.9 V
(see Note A) CANH VO 0.5 V
10%
VO(R)
tr tf

Figure 14. Driver Test Circuit and Voltage Waveforms

CANH
V I (CANH) RXD
IO
VI(CANH) + VI(CANL) V ID
VIC =
2
VO
V I (CANL) CANL

Figure 15. Receiver Voltage and Current Definitions

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Parameter Measurement Information (continued)


3.5 V
CANH 2V 2.4 V
VI
RXD IO 1.5 V
VI
tPLH tPLH
CANL CL = 15 pF ±20% V OH
1.5 V VO 90%
(see NoteA) (see Note B) 0.7 VCC
STB 0.3 VCC
VO
10%
VOL
tr tf

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6 ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.

Figure 16. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test


INPUT OUTPUT
VCANH VCANL |VID| R
–11.1 V –12 V 900 mV L
12 V 11.1 V 900 mV L
VOL
–6 V –12 V 6V L
12 V 6V 6V L
–11.5 V –12 V 500 mV H
12 V 11.5 V 500 mV H
–12 V –6 V 6V H VOH
6V 12 V 6V H
Open Open X H

DUT

CANH

TXD VCC
0V C 60W ±1% VI
L 50%
0V
STB CANL
VI VOH
NOTE: CL = 100 pF
Includes Instrumentation VO 50%
RXD
and Fixture Capacitance ten VOL
+ Within ±20%
VO
− 15 pF ±20%

Figure 17. Ten Test Circuit and Voltage Waveforms

CANH
27 W +1% VOC(PP)
TXD
V
I
CANL 47 nF VOC
VO (CANH) + VO (CANL)
STB
+20% VOC =
27 W +1% 2

All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.

Figure 18. Peak-To-Peak Common Mode Output Voltage Test and Waveform

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DUT

CANH

TXD VCC
C 60 W 1%
L TXD 50%
Input
STB 0V
CANL
tloop2 tloop1
NOTE: CL = 100 pF
VOH
RXD Includes Instrumentation
and Fixture Capacitance 50% 50%
RXD Output
+ Within ±20%
VOL
VO
− 15 pF 20%

All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 125 kHz, 50% duty cycle.

Figure 19. Tloop Test Circuit and Voltage Waveforms

CANH VCC
VI
TXD
RL = 60 W +1% VO 0V
CL VOD(D)
VI (see Note B)
VO 900 mV
CANL 500 mV
(see Note A) STB
0V
tdom

All VI input pulses are from 0 V to VCC and supplied by a generator with the following characteristics: tr or tf ≤ 6 ns.
Pulse Repetition Rate (PRR) = 500 Hz, 50% duty cycle.
A. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.

Figure 20. Dominant Time-Out Test Circuit and Waveform

VCC
CANH
STB 3.5 V
RXD IO VI 2.65 V
VI 1.5 V
CANL 0.7 s tBUS
(see Note A) 1.5 V (see Note B) CL VO
VOH
VO
400 mV
V OL

A. For VI bit width ≤ 0.7 μs, VO = VOH. For VII bit width ≥ 5 μs, VO = VOL. VI input pulses are supplied from a generator
with the following characteristics; tr or tf ≤ 6 ns. Pulse Repetition Rate (PRR) = 50 Hz, 30% duty cycle.
B. CL = 15 pF includes instrumentation and fixture capacitance within ±20%.

Figure 21. TBUS Test Circuit and Waveform

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IOS IOS(SS)
IOS(P)
TXD CANH
0 V or VCC 200 ms
0V
STB 12 V
CANL VIN −12 V or 12 V
Vin
0V
or 10 ms
0V
Vin

−12 V

Figure 22. Driver Short-Circuit Current Test and Waveform

CANH

TXD 60 W ± 1%
VI
60 W ± 1% 4.7 nF VSYM = +VO
VO(CANH) (CANL)

± 20%
STB CANL
V O (CANL) VO (CANH)

Figure 23. Driver Output Symmetry Test Circuit

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9 Detailed Description

9.1 Overview
The SN65HVD1040 CAN bus transceiver meets or exceeds the ISO 11898 standard as a high-speed controller
area network (CAN) bus physical layer device. The device is designed to interface between the differential bus
lines in controller area network and the CAN protocol controller at data rates up to 1 Mbps.

9.2 Functional Block Diagram

VCC (3)

8
Over Temperature
VCC (3) STB
Sensor
10 A
Vcc (3) VCC/2 SPLIT (5)
Dominant
Time-Out

30 A
7
1 Input
CANH
TXD Logic
Driver

Sleep Mode
6
CANL

RXD 4 Output
Logic
MUX
Wake Up
Filter

Bus Monitor

9.3 Feature Description


9.3.1 Mode Control

9.3.1.1 High-Speed Mode


Select the high-speed mode of the device operation by setting the STB pin low. The CAN bus driver and receiver
are fully operational and the CAN communication is bidirectional. The driver is translating a digital input on TXD
to a differential output on CANH and CANL. The receiver is translating the differential signal from CANH and
CANL to a digital output on RXD.

9.3.1.2 Low-Power Mode


If a high logic level is applied to the STB pin, the device enters a low-power bus-monitor standby mode. While
the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater than 5 μs on the bus is
passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the
device when it needs to transmit to the bus.

9.3.2 Dominant State Time-Out


During normal mode, the mode where the CAN driver is active, the TXD DTO circuit prevents the transceiver
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the time-out period tTXD_DTO. The DTO circuit is triggered on a falling edge on the driver input, TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen on TXD before the time-out period expires.
This frees the CAN bus for communication between other nodes on the network. The CAN driver is re-enabled
when a rising edge is seen on the drvier input, TXD, thus clearing the TXD DTO condition. The receiver and
RXD pin still reflect the CAN bus, and the bus pins are biased to recessive level during a TXD DTO.

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Feature Description (continued)

NOTE
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum
possible transmitted data rate on the device. The CAN protocol allows a maximum of
eleven successive dominant bits (on TXD) for the worst case, where five successive
dominant bits are followed immediately by an error frame. This, along with the tTXD_DTO
minimum, limits the minimum data rate. Calculate the minimum transmitted data rate
using: Minimum Data Rate = 11 / tTXD_DTO.

9.3.3 Thermal Shutdown


The SN65HVD1040 has a thermal shutdown that turns off the driver outputs when the junction temperature
nears 190°C. This shutdown prevents catastrophic failure from bus shorts, but does not protect the circuit from
possible damage. The user should strive to maintain recommended operating conditions, and not exceed
absolute maximum ratings at all times. If the SN65HVD1040 is subjected to many or long durations faults that
can put the device into thermal shutdown, it should be replaced.

9.3.4 SPLIT
A reference voltage (VCC/2) is available through the SPLIT outpit pin. The SPLIT voltage should be tied to the
common mode point in a split termination network, hence the pin name, to help stabilize the output common
mode voltage. See Figure 29 for more application specific information on properly terminating the CAN bus.

9.3.5 Operating Temperature Range


The SN65HVD1040 is characterized for operation from –40°C to 125°C.

9.4 Device Functional Modes

Table 2. Driver Function Table (1)


INPUTS OUTPUTS
BUS STATE
TXD STB CANH CANL
L L H L DOMINANT
H L Z Z RECESSIVE
Open X Z Z RECESSIVE
X H or Open Z Z RECESSIVE

(1) H = high level; L = low level; X = irrelevant; Z = high impedance

Table 3. Receiver Function Table (1)


DIFFERENTIAL INPUTS STB OUTPUT BUS STATE
VID = CANH - CANL RXD
VID ≥ 0.9 V L L DOMINANT
VID ≥ 1.15 V H or Open L DOMINANT
0.5 V < VID < 0.9 V X ? ?
VID ≤ 0.5 V X H RECESSIVE
Open X H RECESSIVE

(1) H = high level; L = low level; X = irrelevant; ? = indeterminate; Z =


high impedance

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Table 4. Parametric Cross Reference With the TJA1040


(1)
TJA1040 PARAMETER HVD10xx
TJA1040 DRIVER SECTION
VIH High-level input voltage Recommended VIH
VIL Low-level input voltage Recommended VIL
IIH High-level input current Driver IIH
IIL Low-level input current Driver IIL
TJA1040 BUS SECTION
Vth(dif) Differential input voltage Receiver VIT and recommended VID
Vhys(dif) Differential input hysteresis Receiver Vhys
VO(dom) Dominant output voltage Driver VO(D)
VO(reces) Recessive output voltage Driver VO(R)
VI(dif)(th) Differential input voltage Receiver VIT and recommended VID
VO(dif0(bus) Differential bus voltage Driver VOD(D) and VOD(R)
ILI Power-off bus input current Receiver II(off)
IO(SC) Short-circuit output current Driver IOS(SS)
RI(cm) CANH, CANL input resistance Receiver RIN
RI(def) Differential input resistance Receiver RID
RI(cm) (m) Input resistance matching Receiver RI (m)
CI(cm) Input capacitance to ground Receiver CI
CI(dif) Differential input capacitance Receiver CID
TJA1040 RECEIVER SECTION
IOH High-level output current Recommended IOH
IOL Low-level output current Recommended IOL
TJA1040 SPLIT PIN SECTION
VO Reference output voltage VO
TJA1040 TIMING SECTION
td(TXD-BUSon) Delay TXD to bus active Driver tPLH
td(TXD-BUSoff) Delay TXD to bus inactive Driver tPHL
td(BUSon-RXD) Delay bus active to RXD Receiver tPHL
td(BUSoff-RXD) Delay bus inactive to RXD Receiver tPLH
tPD(TXD–RXD) Prop delay TXD to RXD Device tLOOP1 and tLOOP2
td(stb-norm) Enable time from standby to dominant Driver ten
TJA1040 STB PIN SECTION
VIH High-level input voltage Recommended VIH
VIL Low-level input voltage Recommended VIL
IIH High-level input current IIH
IIL Low-level input current IIL

(1) From TJA1040 Product Specification, NXP, February 19, 2003.

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TXD Input RXD Output


Vcc
Vcc

4. 3 k W 15 W
Input Output

6V 6V

CANH Input CANL Input


Vcc Vcc

10 k W 10 k W
20 k W 20 k W
Input Input

40 V 10 kW 40 V 10 k W

STB Input CANH and CANL Outputs


Vcc Vcc

4. 3 k W Output
Input
40 V
6V

SPLIT Output
Vcc

2kW

Output
2k W
40 V

Figure 24. Equivalent Input and Output Schematic Diagrams

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10 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

10.1 Application Information


The CAN bus has two states during powered operation of the device; dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD pin. A recessive
bus state is when the bus is biased to VCC/2 via the high-resistance internal resistors RIN and RID of the receiver,
corresponding to a logic high on the TXD and RXD pins. See Figure 25 and Figure 26.
4
Typical Bus Voltage (V)

CANH
3

Vdiff(D)
2

Vdiff(R)
CANL
1

Time, t
Recessive Dominant Recessive
Logic H Logic L Logic H
Figure 25. Bus States

CANH

VCC/2
RXD

CANL

Figure 26. Simplified Recessive Common Mode Bias and Receiver

CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the link
layer portion of the CAN protocol. The different nodes on the network are typically connected through the use of
a 120-Ω characteristic impedance twisted-pair cable with termination on both ends of the bus.

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10.2 Typical Application


VIN

VCC
3

VIN VOUT S S (8)


CANH (7)
5-V Voltage
Regulator 5-V MCU
(such as TPS76350) VREF (5)

RXD RXD (4)


TXD TXD (1)
CANL (6)
Optional:
Terminating
GND (2)
Node

Figure 27. Typical Application Schematic

10.2.1 Design Requirements

10.2.1.1 Bus Loading, Length, and Number of Nodes


The ISO 11898 Standard specifies up to 1 Mbps data rate, maximum bus length of 40 meters, maximum drop
line (stub) length of 0.3 meters and a maximum of 30 nodes. However, with careful network design, the system
may have longer cables, longer stub lengths, and many more nodes to a bus. Many CAN organizations and
standards have scaled the use of CAN for applications outside the original ISO 11898 standard. They have made
system level trade-offs for data rate, cable length, and parasitic loading of the bus. Examples of some of these
specifications are SAE J1939, CANopen, DeviceNet and NMEA2000.

Node n
Node 1 Node 2 Node 3 (With Termination)

MCU or DSP
MCU or DSP MCU or DSP MCU or DSP
CAN
CAN CAN CAN Controller
Controller Controller Controller

SN65HVD257 CAN
SN65HVD1040 CAN SN65HVD1050 CAN SN65HVD233 CAN Transceiver
Transceiver Transceiver Transceiver
RTERM

RTERM

Figure 28. Typical CAN Bus

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Typical Application (continued)


A high number of nodes requires a transceiver with high input impedance and wide common mode range such
as the SN65HVD1040 CAN transceiver. ISO 11898-2 specifies the driver differential output with a 60-Ω load (two
120-Ω termination resistors in parallel) and the differential output must be greater than 1.5 V. The SN65HVD1040
device is specified to meet the 1.5-V requirement with a 60-Ω load, and additionally specified with a differential
output voltage minimum of 1.2 V across a common mode range of –2 V to 7 V through a 330-Ω coupling
network. This network represents the bus loading of 90 SN65HVD1040 transceivers based on their minimum
differential input resistance of 30 kΩ. Therefore, the SN65HVD1040 supports up to 90 transceivers on a single
bus segment with margin to the 1.2-V minimum differential input voltage requirement at each node.
For CAN network design, margin must be given for signal loss across the system and cabling, parasitic loadings,
network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes may be
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 meters by careful system
design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to
1-km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898 CAN standard.

10.2.1.2 CAN Termination


The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (ZO ). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed from the bus the termination must be carefully placed so that it
is not removed from the bus.
Termination is typically a 120-Ω resistor at each end of the bus. If filtering and stabilization of the common mode
voltage of the bus is desired, then split termination may be used (see Figure 29). Split termination uses two 60-Ω
resistors with a capacitor in the middle of these resistors to ground. Split termination improves the
electromagnetic emissions behavior of the network by eliminating fluctuations in the bus common mode voltages
at the start and end of message transmissions.
Care should be taken when determining the power ratings of the termination resistors. A typical worst case fault
condition is if the system power supply and ground were shorted across the termination resistance which would
result in much higher current through the termination resistance than the current limit of the CAN transceiver.
Standard Termination Split Termination

CANH CANH

RTERM/2
CAN CAN
Transceiver RTERM
Transceiver

RTERM/2

CANL CANL

Figure 29. CAN Termination

10.2.1.3 Loop Propagation Delay


Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input (TXD pin) to the differential outputs (CANH and CANL pins), plus the delay from the receiver inputs
(CANH and CANL) to its output (RXD pin). A typical loop delay for the SN65HVD1050 transceiver is displayed in
Figure 33.
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Typical Application (continued)


10.2.2 Detailed Design Procedure

10.2.2.1 CAN Basics


The basics of arbitration require that the receiver at the sending node designate the first bit as dominant or
recessive after the initial wave of the first bit of a message travels to the most remote node on a network and
back again. Typically, this “sample” is made at 75% of the bit width, and within this limitation, the maximum
allowable signal distortion in a CAN network is determined by network electrical parameters.
Factors to be considered in network design include the approximately 5 ns/m propagation delay of typical
twisted-pair bus cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in
a system also must be accounted for with adjustments in signaling rate and stub and bus length. Table 5 lists the
maximum signaling rates achieved with the SN65HVD1040 with several bus lengths of category 5, shielded
twisted pair (CAT 5 STP) cable.

Table 5. Maximum Signaling Rates for Various Cable


Lengths
BUS LENGTH (m) SIGNALING RATE (kbps)
30 1000
100 500
250 250
500 125
1000 62.5

The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120 Ω
characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the standard should have as little effect as possible on standard operating
parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the standard’s –2-V to 7-V common-mode range of
tolerable ground noise, helps to ensure data integrity. The SN65HVD1040 enhances the standard’s insurance of
data integrity with an extended –12 V to 12 V range of common-mode operation.
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 30, the differential
signal changes logic states in two places on the display, producing an “eye.” Instead of viewing only one logic
crossing on the scope, an entire “bit” of data is brought into view. The resulting eye pattern includes all of the
effects of systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces and cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the SN65HVD1040 mitigate most all sources of signal corruption, and when
used with a quality shielded twisted-pair cable, help insure data integrity.

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NOISE MARGIN

900 mV Threshold
RECEIVER DETECTION WINDOW 75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN

ALLOWABLE JITTER

Figure 30. Typical CAN Differential Signal Eye-Pattern

10.2.2.1.1 Differential Signal


CAN is a differential bus where complementary signals are sent over two wires and the voltage difference
between the two wires defines the logical state of the bus. The differential CAN receiver monitors this voltage
difference and outputs the bus state with a single ended logic level output signal.
The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant
differential output of the SN65HVD1040 is greater than 1.5 V and less than 3 V across a 60-Ω load as defined by
the ISO 11898 standard. Figure 31 shows CANH, CANL, and the differential dominant state level for the
SN65HVD1040.
A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the
bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver
must do this with common-mode input voltages from –2 V to 7 V.

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Figure 31. Differential Output Waveform

10.2.2.1.2 Common-Mode Signal


A common-mode or recessive signal is an average voltage of the two signal wires that the differential receiver
rejects. The common-mode signal comes from the CAN driver, ground noise, and coupled bus noise. Because
the bias voltage of the recessive state of the device is dependent on VCC , any noise present or variation of VCC
will have an effect on this bias voltage seen by the bus. The SN65HVD1040 CAN transceiver has the recessive
bias voltage set to 0.5 × VCC to comply with the ISO 11898-2 CAN standard.

10.2.2.1.3 ESD Protection


A typical application that employees a CAN bus network may require some form of ESD, burst, and surge
protection to shield the CAN transceiver against unwanted transients that can potential damage the transceiver.
To help shield the SN65HVD1040 transceiver against these high energy transients, transient voltage
suppressors can be implemented on the CAN differential bus terminals. These devices will help absorb the
impact of a ESD, burst, and/or surge strike.

10.2.2.1.4 Transient Voltage Suppresser (TVS) Diodes


Transient voltage suppressors are the preferred protection components for a CAN bus due to their low
capacitance, which allows them to be designed into every node of a multi-node network without requiring a
reduction in data rate. With response times of a few picoseconds and power ratings of up to several kilowatts,
TVS diodes present the most effective protection against ESD, burst, and surge transients.

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Transient

Clamp
Voltage

SN65HVD1040
Transient
Current

Figure 32. Transient

10.2.3 Application Curve

Figure 33. tloop Delay Waveform

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11 Power Supply Recommendations


To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100-
nF ceramic capacitor located as close as possible to the VCC supply pins as possible. The TPS76350 is a linear
voltage regulator suitable for the 5-V supply rail.

12 Layout

12.1 Layout Guidelines


In order for the printed-circuit-board design to be successful, start with design of the protection and filtering
circuitry. Because ESD and EFT transients have a wide frequency bandwidth from approximately 3-MHz to 3-
GHz, high-frequency layout techniques must be applied during PCB design. On chip IEC ESD protection is good
for laboratory and portable equipment but is usually not sufficient for EFT and surge transients occurring in
industrial environments. Therefore robust and reliable bus node design requires the use of external transient
protection devices at the bus connectors. Placement at the connector also prevents these harsh transient events
from propagating further into the PCB and system.
Use VCC and ground planes to provide low inductance.

NOTE
High frequency current follows the path of least inductance and not the path of least
resistance.

Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device. An example placement of the Transient Voltage
Suppression (TVS) device indicated as D1 (either bidirectional diode or varistor solution) and bus filter capacitors
C5 and C7 are shown in Figure 34.
The bus transient protection and filtering components should be placed as close to the bus connector, J1, as
possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.
Bus termination: Figure 34 shows split termination. This is where the termination is split into two resistors, R5
and R6, with the center or split tap of the termination connected to ground through capacitor C6. Split termination
provides common mode filtering for the bus. When termination is placed on the board instead of directly on the
bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal
integrity issues of the bus is not properly terminated on both ends.
Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples
C2, C3 (VCC). Use at least two vias for VCC and ground connections of bypass capacitors and protection devices
to minimize trace and via inductance.
To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3, and R4.
To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1
and C4.
Because the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10-
kΩ pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during
transient events.
Pin 1: If an open-drain host processor is used to drive the TXD pin of the device an external pullup resistor
between 1 kΩ and 10 kΩ should be used to drive the recessive input state of the device.
Pin 5: SPLIT should be connected to the center point of a split termination scheme to help stabilize the common
mode voltage to VCC/2. If SPLIT is unused it should be left floating.
Pin 8: This pin is shown assuming the mode pin, STB, will be used. If the device will only be used in normal
mode, R3 is not needed and the pads of C4 could be used for the pulldown resistor to GND.

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12.2 Layout Example

TXD R1 1 8 R3 VCC /GND


C1 C4

C5
GND 2 7 R5
U1

D1
J1
SN65HVD1040 SPLIT C6
C2
C3

VCC R6

C7
3 6

RXD R2 4 5 R4
Figure 34. Layout Recommendation

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13 Device and Documentation Support

13.1 Community Resources


The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.2 Trademarks
DeviceNet, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN65HVD1040D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 VP1040


SN65HVD1040DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP1040 Samples

SN65HVD1040DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP1040 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 28-Aug-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN65HVD1040 :

• Automotive : SN65HVD1040-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 24-Feb-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD1040DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 24-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD1040DR SOIC D 8 2500 350.0 350.0 43.0

Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK


METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE


BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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