Chapter 5: Memory Management

Operating System Concepts Essentials – 2nd Edition Silberschatz, Galvin and Gagne ©2013
 Chapter 5: Memory
Management
● Logical VS Physical Address Space
● Swapping
● Contiguous Memory Allocation
● Segmentation
● Paging

Operating System Concepts Essentials – 2nd Edition 7.2 Silberschatz, Galvin and Gagne ©2013
 Objectives

● To provide a detailed description of various ways of organizing

memory hardware
● To discuss various memory-management techniques, including
paging and segmentation
● To provide a detailed description of the Intel Pentium, which
supports both pure segmentation and segmentation with paging

Operating System Concepts Essentials – 2nd Edition 7.3 Silberschatz, Galvin and Gagne ©2013
 Background

● Program must be brought (from disk) into memory and placed within a
process for it to be run
● Main memory and registers are only storage ,CPU can access directly
● Memory unit only sees a stream of addresses + read requests, or
address + data and write requests
● Register access in one CPU clock (or less)
● Main memory can take many cycles, causing a stall
● Cache sits between main memory and CPU registers
● Protection of memory required to ensure correct operation

Operating System Concepts Essentials – 2nd Edition 7.4 Silberschatz, Galvin and Gagne ©2013
 Address Binding

● Programs on disk, ready to be brought into memory to execute from an input queue
Without support, It must be loaded into address 0000
●
● Inconvenient to have first user process physical address always at 0000
● How can it not be?
● Further, addresses represented in different ways at different stages of a program’s life
● Source code addresses usually symbolic
● Compiled code addresses bind to relocatable addresses
4 i.e. “14 bytes from beginning of this module”
● Linker or loader will bind relocatable addresses to absolute addresses
4 i.e. 74014
● Each binding maps one address space to another

Operating System Concepts Essentials – 2nd Edition 7.5 Silberschatz, Galvin and Gagne ©2013
 Binding of Instructions and Data to Memory

● Address binding of instructions and data to memory addresses can happen

at three different stages
● Compile time: If memory location known a priori, absolute code
can be generated and if starting location changes must recompile
code
● Load time: Must generate relocatable code if memory location is not
known at compile time
● Execution time: Binding delayed until run time if the process can be
moved during its execution from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers)

Operating System Concepts Essentials – 2nd Edition 7.6 Silberschatz, Galvin and Gagne ©2013
 Multistep Processing of a User
Program

Operating System Concepts Essentials – 2nd Edition 7.7 Silberschatz, Galvin and Gagne ©2013
 Logical vs. Physical Address
Space
● The concept of a logical address space that is bound to a separate physical
address space is central to proper memory management
● Logical address – generated by the CPU; also referred to as virtual
address
● Physical address – address seen by the memory unit
● Logical and physical addresses are the same in compile-time and
load-time address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding scheme.
● Logical address space is the set of all logical addresses generated by a
program
● Physical address space is the set of all physical addresses generated by a
program

Operating System Concepts Essentials – 2nd Edition 7.8 Silberschatz, Galvin and Gagne ©2013
 Memory-Management Unit (MMU)
● Hardware device that at run time maps virtual to physical address
● Many methods possible, covered in the rest of this chapter
● To start, consider simple scheme where the value in the relocation register is added
to every address generated by a user process at the time it is sent to memory
● Base register now called relocation register
● MS-DOS on Intel 80x86 used 4 relocation registers
● The user program deals with logical addresses; it never sees the real physical
addresses
● Execution-time binding occurs when reference is made to location in memory
● Logical address bound to physical addresses

● CPU --------- [MMU]------- Main Memory

[Logical [ Physical Adrress]
Address]
nd
Operating System Concepts Essentials – 2 Edition 7.9 Silberschatz, Galvin and Gagne ©2013
 Dynamic relocation using a relocation register

Operating System Concepts Essentials – 2nd Edition 7.10 Silberschatz, Galvin and Gagne ©2013
 Static and Dynamic (Run-Time) Linking

● Static linking – system libraries and program code combined by the loader
into the binary program image
● Dynamic linking –linking postponed until execution time
● Small piece of code, stub, used to locate the appropriate memory-resident
library routine
● Stub replaces itself with the address of the routine, and executes the routine
● Operating system checks if routine is in processes’ memory address
● If not in address space, add to address space
● Dynamic linking is particularly useful for libraries
● System also known as shared libraries

Operating System Concepts Essentials – 2nd Edition 7.11 Silberschatz, Galvin and Gagne ©2013
 Swapping

● A process can be swapped temporarily out of memory to a backing store, and then
brought back into memory for continued execution
● Total physical memory space of processes can exceed physical memory
● Backing store – fast disk large enough to accommodate copies of all memory images
for all users; must provide direct access to these memory images
● Roll out, roll in – swapping variant used for priority-based scheduling algorithms;
lower-priority process is swapped out so higher-priority process can be loaded and executed
WhatsApp Image 2023-11-01 at 3.06.16 PM
● Major part of swap time is transfer time; total transfer time is directly proportional to
the amount of memory swapped
● System maintains a ready queue of ready-to-run processes which have memory images on
disk

Memory
Processes in memory Roll Out
p1,p4,p3 Swap Out / Swap Device
New P2 high priority
Backing Store
Higher Threshold : 10
P2 Swap In/ Roll
In
Operating System Concepts Essentials – 2nd Edition 7.15 Silberschatz, Galvin and Gagne ©2013
 Swapping (Cont.)
● Does the swapped out process need to swap back in to same physical addresses?
● Depends on address binding method
Plus consider pending I/O to / from process memory space
●
● Modified versions of swapping are found on many systems (i.e., UNIX, Linux,
and Windows)
● Swapping normally disabled
● Started if more than threshold amount of memory allocated
● Disabled again once memory demand reduced below threshold

Operating System Concepts Essentials – 2nd Edition 7.16 Silberschatz, Galvin and Gagne ©2013
 Schematic View of
Swapping

Operating System Concepts Essentials – 2nd Edition 7.17 Silberschatz, Galvin and Gagne ©2013
 Context Switch Time including
Swapping
● If next processes to be put on CPU is not in memory, need to swap out a process
and swap in target process
● Context switch time can then be very high
● 100MB process swapping to hard disk with transfer rate of 50MB/sec
● Swap out time of 2000 ms
● Plus swap in of same sized process
● Total context switch swapping component time of 4000ms (4 seconds)
● Can reduce if reduce size of memory swapped – by knowing how much
memory really being used
● System calls to inform OS of memory use via request_memory() and
release_memory()

Operating System Concepts Essentials – 2nd Edition 7.18 Silberschatz, Galvin and Gagne ©2013
 Context Switch Time and Swapping
(Cont.)
● Other constraints as well on swapping
● Pending I/O – can’t swap out as I/O would occur to wrong process
● Or always transfer I/O to kernel space, then to I/O device
4 Known as double buffering, adds overhead 20 k
● Standard swapping not used in modern operating systems
30k
● But modified version common
10k
4 Swap only when free memory extremely low

Pass2
[80k]

Pass 1
[70k]

Operating System Concepts Essentials – 2nd Edition 7.19 Silberschatz, Galvin and Gagne ©2013
 Swapping on Mobile Systems
● Not typically supported
● Flash memory based
4 Small amount of space
4 Limited number of write cycles
4 Poor throughput between flash memory and CPU on mobile platform
● Instead use other methods to free memory if low
● iOS asks apps to voluntarily relinquish allocated memory
4 Read-only data thrown out and reloaded from flash if needed
4 Failure to free can result in termination
● Android terminates apps if low free memory, but first writes application state to flash for fast restart
● Both OSes support paging as discussed below

Operating System Concepts Essentials – 2nd Edition 7.20 Silberschatz, Galvin and Gagne ©2013
 Hardware Support for Relocation and Limit Registers

74600 100040

62300 100040
+
62300
82300 < 74600 false = 162340
Trap : addr error

Operating System Concepts Essentials – 2nd Edition 7.21 Silberschatz, Galvin and Gagne ©2013
 Contiguous Allocation
● Main memory must support both OS and user processes
Operating
● Limited resource, must allocate efficiently System
● Contiguous allocation is one early method
● Main memory usually into two partitions:
● Resident operating system, usually held in low memory with interrupt vector
● User processes then held in high memory User Processes
● Each process contained in single contiguous section of memory

Operating System Concepts Essentials – 2nd Edition 7.22 Silberschatz, Galvin and Gagne ©2013
 Contiguous Allocation (Cont.)
● Relocation registers used to protect user processes from each other, and
from changing operating-system code and data
● Base register contains value of smallest physical address
● Limit register contains range of logical addresses – each logical address must
be less than the limit register
● MMU maps logical address dynamically
● Can then allow actions such as kernel code being transient and kernel changing
size

Operating System Concepts Essentials – 2nd Edition 7.23 Silberschatz, Galvin and Gagne ©2013
 H1 100 allo free free
free c
Multiple-partition allocation H6 H3
60 100

● Multiple-partition allocation
H2 H5
● Degree of multiprogramming limited by number of partitions 80 70
● Variable-partition sizes for efficiency (sized to a given process’ needs) H4
150
● Hole – block of available memory; holes of various size are scattered throughout
● memory
When a process arrives, it is allocated memory from a hole large enough to
accommodate it
● Process exiting frees its partition, adjacent free partitions combined
● Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

Operating System Concepts Essentials – 2nd Edition 7.25 Silberschatz, Galvin and Gagne ©2013
 Dynamic Storage-Allocation
Problem
How to satisfy a request of size n from a list of free holes?
● First-fit: Allocate the first hole that is big enough
● Best-fit: Allocate the smallest hole that is big enough; must search

entire list, unless ordered by size

● Produces the smallest leftover hole

● Worst-fit: Allocate the largest hole; must also search entire list
● Produces the largest leftover hole

Operating System Concepts Essentials – 2nd Edition 7.27 Silberschatz, Galvin and Gagne ©2013
2
 Fragmentation
● External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous
● Internal Fragmentation – allocated memory may be slightly larger than requested memory;
this size difference is memory internal to a partition, but not being used
● First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
● 1/3 may be unusable -> 50-percent rule

Problem with Internal fragment

Waste=10-5=5k

Operating System Concepts Essentials – 2nd Edition 7.33 Silberschatz, Galvin and Gagne ©2013
 Fragmentation (Cont.)

● Reduce external fragmentation by compaction

● Shuffle memory contents to place all free memory together in one large block
● Compaction is possible only if relocation is dynamic, and is done at execution time
● I/O problem
H1 100 Free Free Free Free
4 Latch job in memory while it is involved in I/O free 200 120 60
70
4 Do I/O only into OS buffers
● Now consider that backing store has same fragmentation problems Free 40 Free Free 45 Free 80 H5
100 70

Free Free 30 alloc alloc alloc

1000

alloc allco alloc alloc alloc

alloc alloc allco alloc alloc

Operating System Concepts Essentials – 2nd Edition 7.34 Silberschatz, Galvin and Gagne ©2013
 Segmentation

● Memory-management scheme that supports user view of memory

● A program is a collection of segments
A segment is a logical unit such as: main program
Procedure
function
method
object
local variables,
global variables
common block
stack
symbol table
arrays Silberschatz, Galvin and Gagne ©2013
Operating System Concepts Essentials – 2nd Edition 7.41
 User’s View of a Program

Operating System Concepts Essentials – 2nd Edition 7.42 Silberschatz, Galvin and Gagne ©2013
 Logical View of
Segmentation
1

4
1

3 2
4

user space physical memory space

Operating System Concepts Essentials – 2nd Edition 7.43 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture

● Logical address consists of a two tuple:

<segment-number, offset>,

● Segment table – maps two-dimensional physical addresses; each table

entry has:
● base – contains the starting physical address where the segments reside
in memory
● limit – specifies the length of the segment

● Segment-table base register (STBR) points to the segment table’s

location in memory
● Segment-table length register (STLR) indicates number of segments
used by a program; segment number s is legal if s < STLR
Operating System Concepts Essentials – 2nd Edition 7.44 Silberschatz, Galvin and Gagne ©2013
 Segmentation Architecture (Cont.)
● Protection
With each entry in segment table associate:
●
4 validation bit = 0 ⇒ illegal segment
4 read/write/execute privileges
● Protection bits associated with segments; code sharing occurs at
segment level
● Since segments vary in length, memory allocation is a dynamic
storage-allocation problem
● A segmentation example is shown in the following diagram

Operating System Concepts Essentials – 2nd Edition 7.45 Silberschatz, Galvin and Gagne ©2013
 Segmentation Hardware

Operating System Concepts Essentials – 2nd Edition 7.46 Silberschatz, Galvin and Gagne ©2013
Example Of Segmentation
For example,
segment 2,limit=400 ,Base=4300
Thus, a reference(displacement) to byte 53 of segment 2 is
mapped onto location 4300 +53= 4353 (53<400).

A reference to segment 3, byte 852, is mapped to 3200 (the

base of segment 3) 3200+ 852 = 4052(852<1100).

A reference to byte 1222 of segment 0 would result in a trap to

the operating system, as this segment is only tO bytes
long.(1222<1000) False
 Paging

● Physical address space of a process can be noncontiguous; process is

allocated physical memory whenever the latter is available
● Avoids external fragmentation
● Avoids problem of varying sized memory chunks
● Divide physical memory into fixed-sized blocks called frames
● Size is power of 2, between 512 bytes and 16 Mbytes
● Divide logical memory into blocks of same size called pages
● Keep track of all free frames
● To run a program of size N pages, need to find N free frames and load
program
● Set up a page table to translate logical to physical addresses
● Backing store likewise split into pages
7.49 Silberschatz, Galvin and Gagne ©2013
 Address Translation Scheme
● Address generated by CPU is divided into:
● Page number (p) – used as an index into a page table which contains base address of each page in
physical memory
● Page offset (d) – combined with base address to define the physical memory address that is sent to the
memory unit
For given logical address space 2m and page size 2n

Operating System Concepts Essentials – 2nd Edition 7.50 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware

Operating System Concepts Essentials – 2nd Edition 7.51 Silberschatz, Galvin and Gagne ©2013
 Paging Model of Logical and Physical
Memory

Operating System Concepts Essentials – 2nd Edition 7.52 Silberschatz, Galvin and Gagne ©2013
 Paging Example

n=2 and m=4 32-byte memory and 4-byte

pages

Operating System Concepts Essentials – 2nd Edition 7.53 Silberschatz, Galvin and Gagne ©2013
Here, in the logical address, n= 2 and m = 4.
Using a page size of 4 bytes and a physical memory of 32 bytes (8 pages),
we show how the user's view of memory can be mapped into physical memory.
Logical address 0 is page 0, offset 0.
Indexing into the page table, we find that page 0 is in frame 5.
Thus, logical address 0 maps to physical address 20 [= (5 x 4) + 0].

Logical address 3 (page 0, offset 3) maps to physical address 23 [ = (5 x 4) + 3].

Logical address 4 is page 1, offset 0; according to the page table,

page 1 is mapped to frame 6.
Thus, logical address 4 maps to physical address 24 [ = ( 6 x 4) + 0].
Logical address 13 maps to physical address 9[=2*4+1]
 Implementation of Page
Table
● Page table is kept in main memory
● Page-table base register (PTBR) points to the page table
● Page-table length register (PTLR) indicates size of the page
table
● In this scheme every data/instruction access requires two
memory accesses
● One for the page table and one for the data / instruction
● The two memory access problem can be solved by the use of a
special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)

Operating System Concepts Essentials – 2nd Edition 7.55 Silberschatz, Galvin and Gagne ©2013
 Implementation of Page Table
(Cont.)
● Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
● Otherwise need to flush at every context switch
● TLBs typically small (64 to 1,024 entries)
● On a TLB miss, value is loaded into the TLB for faster access
next time
● Replacement policies must be considered
● Some entries can be wired down for permanent fast access

Operating System Concepts Essentials – 2nd Edition 7.56 Silberschatz, Galvin and Gagne ©2013
 Associative Memory

● Associative memory – parallel search

● Address translation (p, d)

● If p is in associative register, get frame # out
● Otherwise get frame # from page table in memory

Operating System Concepts Essentials – 2nd Edition 7.57 Silberschatz, Galvin and Gagne ©2013
 Paging Hardware With TLB

Operating System Concepts Essentials – 2nd Edition 7.58 Silberschatz, Galvin and Gagne ©2013
 Memory Protection

● Memory protection implemented by associating protection bit with

each frame to indicate if read-only or read-write access is allowed
● Can also add more bits to indicate page execute-only, and so on
● Valid-invalid bit attached to each entry in the page table:
● “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
● “invalid” indicates that the page is not in the process’ logical address
space
● Or use page-table length register (PTLR)
● Any violations result in a trap to the kernel

Operating System Concepts Essentials – 2nd Edition 7.59 Silberschatz, Galvin and Gagne ©2013
 Valid (v) or Invalid (i) Bit In A Page
Table

Operating System Concepts Essentials – 2nd Edition 7.60 Silberschatz, Galvin and Gagne ©2013
 End of Chapter 7

Operating System Concepts Essentials – 2nd Edition Silberschatz, Galvin and Gagne ©2013