Fetch Decode Execute Cycle

and Interrupts
 Learning objectives

✔ Explain the difference between RISC and CISC chips

✔ Explain processing pipelining
✔ Explain processing on GPUs
✔ Explain how the processor works
✔ Explain the fetch, decode, execute cycle
✔ Explain what an interrupt is
 RISC (Reduced instruction set chips)

✔ RISC chips have a set of instructions that take fewer CPU cycles to execute.
✔ RISC chips contain simple instructions.
✔ These chips have simpler logic circuits, have fewer transistors
✔ Each instruction that can be executed in a single CPU cycle.
✔ It takes more operations to perform more complex instructions.
✔ On a RISC chip complex instructions can be achieved by combining a sequence of these simpler operations.
✔ Although RISC chips may process each operation quicker, more complex tasks will require more operations.
✔ RISC chips can now be found in most devices including mobile phones and computers.
✔ Complex translation required from high level programming language to the low level assembler instructions.
 CISC (Complex Instruction Set Chips)

✔ The hardware architecture of the chip is more complex than for RISC
chips.
✔ More logic circuitry is needed to perform the operations.
✔ Instructions can consist of several operations.
✔ Instructions will take multiple clock cycles to execute.
✔ It does mean that programs are shorter reducing requirements on
memory.
✔ More straightforward translation between high level language the
assembly language.
 Processor pipelining
✔ Processor pipelining allows instructions to be carried out in parallel on a single processor, thereby
improving processor throughput.
✔ The processor steps are broken down into stages, in this case fetch decode and execute stages. In
reality there are more stages, but we only include these three here for simplicity
✔ Without pipelining the stages will occur in series. The complete fetch-decode-execute cycle of the
preceding operation needs to be completed before the next instruction is fetched.
✔ Once the fetch part of the cycle has been completed in pipeline 1, it moves onto the decode part.
At the same time the next instruction is fetched. When these second steps have been completed,
pipeline moves onto the execute step, pipeline moves onto the decode and Pipeline 3 fetches the
instruction. This process repeats itself.

Time 1 2 3 4 5 6 7 8 9
No Pipelining Fetch Decode Execute Fetch Decode Execute Fetch Decode Execute

Pipeline 1 Fetch Decode Execute

Pipeline 2 Fetch Decode Execute
Pipeline 3 Fetch Decode Execute
 Multicore and parallel processing

✔ Parallel and multicore processing systems allow instructions and data

to be processed at the same.
✔ All processors have threads which allows processing to be performed
at the same time.
✔ Muticore processing refers to threading instructions on multiple cores
on a single CPU chip.
✔ Parallel processing refers to multiple processors as in the case of a
supercomputer, processing data and instructions at the same time
cross multiple CPUs.
 Discrete Graphics Card

✔ You can add these graphic cards to the motherboard’s expansion slots
✔ Graphics cards control the output to the monitor
✔ They allow the quality of the graphics to be improved
✔ Graphics cards have their own processing capability called a GPU (graphics
processing unit), taking some of the burden away from the CPU.
✔ These are specialised CPUs designed for graphics rendering
✔ Graphics cards also have their own RAM
✔ Graphics cards are connected to the monitor via ports (eg HDMI or VGA)
 Uses of GPUs

✔ GPUs process data in parallel giving them a high processing throughput.

✔ GPUs are good for tasks that are processing intensive but at the same time
are highly parallelizable.
✔ GPUs are that makes them good for:
✔ Machine learning – Processing huge volumes of data for creating models
✔ Video rendering
✔ Gaming
✔ Blockchain and cryptocurrency mining – solving complex mathematical
problems to validate new transactions that are added to the blockchain.
 Components of a CPU

✔ Arithmetic logic unit – The arithmetic and logic operations take place here.
✔ Control unit – Decodes the instruction, splits it into the opcode and operand and
identifies the specific operation.
✔ Clock – The purpose is to keep all the processor components synchronised. The
clock controls the processor so that it can process the instructions one-by-one and
in the correct order.
✔ Registers – Memory locations on the CPU. Much faster than cache and RAM
however also much smaller. Used to store frequently accessed data and
instructions. There are two types of registers general purpose and registers
dedicated to a specific purpose.
Processor schematic
Processor Main memory

Registers Address Content

Address bus
PC MAR
Data bus
CIR MBR

ACC

Control Unit ALU

Clock
 Dedicated registers

✔ Memory Address Register (MAR) – The address in main memory that we wish to fetch the
instruction from
✔ Memory Buffer Register (MBR) – Holds the instruction that has been fetched from memory
✔ Current instruction register (CIR) – Holds the contents of MBR, which is the instruction to be
processed
✔ Program Counter (PC) – This holds the memory address of the location to fetch the next instruction
from.
✔ Status Register (SR) – Gives information on such things as overflow/underflow, interrupts, parity.
The status register allows an instruction to depend the outcome of the previous instruction.
✔ Accumulator – Holds the results of arithmetic and logic computations
 Fetch-decode-execute cycle
✔ The instructions are loaded into memory
✔ The processor fetches the instruction from the
main memory
✔ The instruction is decoded so the CPU knows
what to do with the instruction
✔ The processor then executes the instruction
✔ The result of the instruction can be stored in
memory
✔ The next instruction is then fetched from main
memory and the cycle repeats itself
Fetch-decode-execute

Transfer the contents of the PC to the MAR

1. MAR ← [PC]

The contents at that address is transferred back to the MBR along the data bus
2. MBR ← [Memory]MAR_address At the same time the PC is incremented by one to get ready for the next cycle.
PC ← [PC] +1

Transfer the contents of the MBR to the CIR ready to be decoded.

3. CIR ← [MBR]

4. Decode [CIR] Control unit decodes instruction held in CIR into operand and opcode

Instruction executed by ALU for instance and result stored in Accumulator.

Status register updated
5. Execute [CIR]
 Fetch

Processor Main memory

Register Content Address Content
PC 0 0 00101001
MAR 1 11101010
MBR 2 11100101
CIR 3 10101110
 Fetch: MAR ← [PC]

Processor Main memory

Register Content Address Content
PC 0 Address bus 0 00101001
MAR 0 1 11101010
MBR 2 11100101
CIR 3 10101110

✔ Transfer the contents of the PC to the MAR

✔ The address in MAR is transferred to main memory along the address bus
 Fetch: MBR ← [Memory]MAR_address ; PC ← [PC] +1
Processor Main memory
Register Content Address Content
PC 1 Address bus 0 00101001
MAR 0 1 11101010
MBR 00101001 Data bus 2 11100101
CIR 3 10101110

✔ The contents at that address is transferred back to the MBR along the data bus
✔ At the same time the PC is incremented by one to get ready for the next cycle. This can be
done because the two steps do not rely on one another.
 Fetch: CIR ← [MBR]
Processor Main memory
Register Content Address Content
PC 1 Address bus 0 00101001
MAR 0 1 11101010
MBR 00101001 Data bus 2 11100101
CIR 00101001 3 10101110

✔ Transfer the contents of the MBR to the CIR ready to be decoded.

✔ This allows the MBR to be used to store the next instruction during the decode and
execution stages.
 Decode: [CIR]

Processor
✔ The control unit decodes the Registers
instruction held by the current PC MAR
instruction register.
CIR MBR
✔ The instruction is divided into the
opcode and the operand ACC

Control Unit ALU

Clock
 Execute: [CIR]
Processor

✔ The instruction is executed in the Registers

PC MAR
arithmetic logic unit.
✔ The result is stored in the CIR MBR

accumulator register ACC

✔ The status register is updated
Control Unit ALU

Clock
Fetch Decode Execute Animation
FDE images Slide-by-Slide
 Multitasking

✔ Multitasking allows concurrent processing of multiple programs.

✔ Instructions can only be processed one at a time on a single
processing core.
✔ Multitasking works by interleaving operations between multiple
programs.
✔ Multitasking interrupts a program so that another program can use
the processor.
 What is an interrupt?
✔ Interrupts are messages from software applications or hardware that request processing
resources from the processor.
✔ If the processor is performing operations already then those processes can be interrupted
and suspended, and the CPU processes the interrupt request
✔ An interrupt service routine will be executed depending on the type of interrupts.
✔ When an interrupt occurs, the data and instruction in the registers from the interrupted
job are stored in the stack so that the job can be restored after the interrupt has been
dealt with.
✔ Once the interrupt has been completed the processor resumes the job it was currently
processing from where it left off. It is able to do this because the instructions and data are
loaded back into registers and memory from the stack.
Examples of interrupts

✔ Hardware commands
✔ Computer reset
✔ Software
✔ Error detection
✔ Overflow error
✔ Timer
✔ Input/output
✔ Pressing a key on a keyboard
✔ Moving the mouse
 Interrupt Service Routine

Step 1 Stack Step 2 Stack When an interrupt is encountered the

contents of the program counter are
Program Counter: Program Counter:
copied to the stack and address of the
0100 0111
instruction of the interrupt service
routine is copied to the program
Interrupt service 0100 counter.
Routine address:
0111 Once all the instructions of the
interrupt service routine have been
Stack executed the address in the stack is
Step 3 copied back into the program counter
and the original processing task
Program Counter: resumes.
0100
Interrupt in the fetch execute cycle Start

Fetch next instruction

Decode instruction

Execute instruction

No

Yes
Interrupt? Process interrupt