ANALOG

1111111111 LC 2MOS High Speed µ,P-Compatible

WDEVICES 8-Bit ADC with Track/Hold Function
AD7820 I
FEATURES FUNCTIONAL BLOCK DIAGRAM
Fast Conversion Time: 1.36p.s max Voo

Built-In Track-and-Hold Function

No Missed Codes 4-BIT
FLASH
No User Trims Required ADC
(4MSB)
Single + 5V Supply
Ratiometric Operation
No External Clock 4-BIT
DB0-087
DATADUT
DAC
Extended Temperature Range Operation PINS 2-5, 14-17

Skinny 20-Pin DIP, SOIC and 20-Terminal

Surface Mount Packages
4-BIT
FLASH
ADC
l4LSBI

GND MODE WR/ROY CS RD INT

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD7820 is a high speed, microprocessor-compatible 8-bit 1. Fast Conversion Time
analog-to-digital converter which uses a half-flash conversion The half-flash conversion technique, coupled with fabrication
technique to achieve a conversion time of 1.36µ,s. The converter on Analog Devices' LC2MOS process, enables very fast con-
has a OV to + SV analog input voltage range with a single + SV version times. The maximum conversion time for the WR-RD
supply. mode is 1.36µ,s, with l.6µs the maximum for the RD mode.
The half-flash technique consists of 31 comparators, a most 2. Total Unadjusted Error
significant 4-bit ADC and a least significant 4-bit ADC. The The AD7820 features an excellent total unadjusted error
input to the AD7820 is tracked and held by the input sampling figure of less than l/2LSB over the full operating temperature
circuitry, eliminating the need for an external sample-and-hold range. The part is also guaranteed to have no missing codes
for signals with slew rates less than lOOmV/µs. over the entire temperature range.
The part is designed for ease of microprocessor interface with 3. Built-In Track-and-Hold
the AD7820 appearing as a memory location or 1/0 port without The analog input circuitry uses sampled-data comparators,
the need for external interfacing logic. All digital outputs use which by nature have a built-in track-and-hold function. As
latched, three-state output buffer circuitry to allow direct con- a result, input signals with slew rates up to lOOmV/µs can be
nection to a microprocessor data bus or system input port. A converted to 8-bits without external sample-and-hold. This
non-three state overflow output is also provided to allow cascading corresponds to a SV peak-to-peak, 7kHz sine-wave signal.
of devices to give higher resolution. 4. Single Supply
The AD7820 is fabricated in an advanced, all ion-implanted, Operation from a single + SV supply with a positive voltage
high speed, Linear Compatible CMOS (LC 2MOS) process and reference allows operation of the AD7820 in microprocessor
features a low maximum power dissipation of 75mW. It is available systems without any additional power supplies.
in 20-pin DIPs, SOICs and in 20-terminal surface mount
packages.

REV.A
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
parties which may result from its use. No license is granted by implica- Tel: 617/329-4700 Fax: 617/326-8703 Twx: 710/394-6577
tion or otherwise under any patent or patent rights of Analog Devices. Telex: 924491 Cable: ANALOG NORWOODMASS
 (V00 = + SV; VREF ( +) = + SV; VREF ( - ) = GND = DV unless otherwise stated).
All specifications lmin to lmax unless otherwise specified. Specifications apply for
AD7820-SPECIFICATIONS RD Mode (Pin 7= OV)
...,._.. KVe..- 1 LVenioa B,TVenioaa C,UVeniou Ullita eo.diliou/Commem
ACCUJlACY
Raohnion 8 8 8 8 Bits
Tow U....tjusted Error2 :!:) :!: 1/2 :!:I :!: 112 LSBmu
Mllllmum Raolution forwllicll
NoMillins Codes are pruueed 8 8 Bits
REFERENCE INPUT
Input Rcsimnc:c 1.0/4.0 1.0/4.0 1.0/4.0 1.0/4.0 ldl min/ldl mu
Yau(+ )Input Voltage Range VREF(- )IVDD VaEF(- )[Von VaEF(- )[Von VllEF( - ){Von Vmin/Vmu
VaEF(-)InputVoltagollange GNDNaEF(+) GNDNaEF(+) GNDNaEF(+) GNDNREF( +) Vmin/Vmu
ANALOG INPUT
Input Voltqe ilmF V REF( - )IV REF( + ) VREF< - )IVREF< +) V REp( - )IVREF( + ) V11EF( - )N11EF< +) Vmin/Vmax
Input Leakage Currcn1 :!:3 :!:3 :!: 3 :!:3 tLAmu
Input c.p.citance 3 45 45 45 45 pF1yp
LOGIC INPUTS
CS,WR,RD
VINH 2.4 2.4 2.4 2.4 Vmin
VINL 0.8 0.8 0.8 0.8 Vmu
IINH (CS, RD) I tLAmu
l1N11(\1VR) 3 tLAmu
IINL -I -1 -I -I tLAmu
Input C.pmcitmce3 8 8 8 8 pFmu Typically 5pF
MODE
VINH 3.5 3.5 3.5 3.5 Vmin
VINL 1.5 1.5 1.5 1.5 Vmax
IINH 200 200 200 200 tLAmu 50tLAtyp
I1N1. -I -1 -I -I tLAmu
Input C.pmcitllllCC3 8 8 8 8 pFmu Typically5pF
LOGIC OUTPUTS
DBO-DB7, OFL, INT
Vo11 4.0 4.0 4.0 4.0 Vmin Isou11cE = 360tLA
VoL 0.4 0.4 0.4 0.4 Vmu IsiNK = l.6mA
louT (DBO-DB7) :!: 3 :!:3 :!:3 :!:3 tLAmu Floating Staie Leakage
Output c.p.ciw,a,3 8 8 8 pFmu Typically 5pF
ROY
VoL 0.4 0.4 0.4 0.4 Vmu IslNk = 2.6mA
louT :!:3 :!:3 :!:3 :!:3 tLAmu Floating Stale Leakage
Output c.p.ciw,a,3 8 8 8 pFmax Typically 5pF
SLEW RATE, TRACKING' 0.2 0.2 0.2 0.2 VlfLS!yp
0.1 0.1 0.1 0.1 Vi..,smax
POWER SUPPLY
Von Volis :!: 5% for Specified
Performance
Inn• 15 15 20 20 mAmu CS=RD=OV
Power Diaipatian 40 40 40 40 mWtyp
Power Supply Sensitivity :!: 1/4 :!: 114 :!: 1/4 :!: 1/4 LSBmu :!: l/16LSB typ
Vnn=5V :t5%

NOTES
'Tcmpcnture Ruips are II follows:
K, L Vcniolll: - 40'C to + 85'C
B, C Versions: - 40'C to + 85'C
T, U Veniom: - 55'C to + 12S'C
'T-i Ulllldjllllcd Error includesoffoct, full-scale and linearitycm,n.
'S.mptc lalal at 2S'C by Product Aaunnce tocmurccompliance.
"Sec Typical Pafarmuce Cll8nctaistics.
Specifications subject to cba111C without notice.

-2- REV.A
 AD7820

TIMING CHARACTERISTICSl (V 111 = + 5Y; Vm( + )= +5Y; Ym (-)= GND =DY unless otherwise stated.)

Limit at Limit at
Limit at 25°C Tmia,T....,. Tmia,T....,.
Parameter (All Versions) (K, L, B, C Versions) (T, UVersions) Units Conditions/Comments
less 0 0 0 nsmin CS TO RD/WR Setup Time
fcsH 0 0 0 nsmin CS TO RD/WR Hold Time
tRDy2 70 90 100 nsmax CS to Delay. Pull-Up
Resistor 5k0.
tcRD 1.6 2.0 2.5 µsmax Conversion Time (RD Mode)
tAcci tcRD +20 tcRD +35 tcRD +50 nsmax Data Access Time (RD Mode)
t!NTH2 125 nstyp RD to INT Delay (RD Mode)
175 225 225 nsmax
toH4 60 80 100 nsmax Data Hold Time
tp 500 600 600 nsmin Delay Time between Conversions
t'IVR 600 600 600 nsmin Write Pulse Width
50 50 50 µsmax
tRD 600 700 700 nsmin Delay Time between WR and RD Pulses
tAcc1 3 160 225 250 nsmax Data Access Time (WR-RD Mode,
see Fig. Sb)
tRl 140 200 225 nsmax RD to INT Delay
t!NTL2 700 nstyp WR to INT Delay
1000 1400 1700 nsmax
tACC23 70 90 110 nsmax Data Access Time (WR-RD Mode,
see Fig. Sa)
tIHWR2 100 130 150 nsmax WR to INT Delay (Stand-Alone Operation)
tm 50 65 75 nsmax Data Access Time after INT
(Stand-Alone Operation)

NOTES
1
Sample tested at 2S"C to ensure compliance. All input control signals are specified with tr=tf=20ns (10% to 90"A, of +SV) and timed from a voltage level of l.6V.
2cL=SOpF.
3
Measured with load circuits of Figure I and defined as the time required for an output to cross 0.8V or 2.4V.
4
Defined as the time required for the data lines to change O.SV when loaded with the circuits of Figure 2.
Specifications subject to change without notice.

Test Circuits

3kfi•
,•
'
..••
3kfi '

DGND DGND

a. High-Zto VOH a. VoH to High-Z

b. High-Zto Vol b. Vol to High-Z

Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test

REV.A -3-
 AD7820
ABSOLUTE MAXIMUM RATINGS*
VootoGND . . . . . . . . . . . . . . . . OV, +7V Storage Temperature Range . . . . . . . . . - 6S°C to + 1S0°C
Digital Input Voltage to GND Lead Temperature (Soldering, IOsecs) +300°C
-----~..,._,,ins~~8~--ill •- L . ~ ~- -• - ~ -• - ~ • -0.3V,._ Voo +0.3V Power Dissipation (Any Package) to + 7S°C 4SOmW
Digital Output Voltage to GND Derates above + 7S°C by . . . . . . . . . . 6mWf'C
(Pins 2-S, 9, 14-18) -0.3V, V00 +0.3V
VREF ( +) to GND VREF (-), Von +0.3V
VREF ( - ) to GND . . . . ov, VREF ( +) *Stresses above those listed under "Absolute Maximum Ratings" may
VIN to GND . . . . -0.3V, Von +0.3V cause permanent damage to the device. This is a stress rating only and
Operating Temperature Range functional operation of the device at these or any other conditions above
Commercial (K, L Versions) - 40°C to + 8S°C those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
Industrial (B, C Versions) -40°C to +8S°C periods may affect device reliability.
Extended (T, U Versions) - SS°C to + 12S°C

CAUTION:
ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected;
however, permanent damage may occur on unconnected devices subject to high energy electro-
static fields. Unused devices must be stored in conductive foam or shunts. The protective foam
should be discharged to the destination socket before devices are inserted.

ORDERING GUIDE

Total
Temperature Unadjusted Package
Model1 Range Error(Max) Option2
AD7820KN - 40°C to + 8S°C ±lLSB N-20
AD7820LN - 40°C to + 8S°C ± l/2LSB N-20
AD7820KP - 40°C to + 8S°C ±lLSB P-20A
AD7820LP - 40°C to + 8S°C ±l/2LSB P-20A
AD7820KR - 40°C to + 8S°C ±lLSB R-20
AD7820LR - 40°C to + 8S°C ± l/2LSB R-20
AD7820BQ - 40°C to + 8S°C ±lLSB Q-20
AD7820CQ - 40°C to + 8S°C ± l/2LSB Q-20
AD7820TQ - SS°C to + 12S°C ±lLSB Q-20
AD7820UQ - SS°C to + 12S°C ± l/2LSB Q-20
AD7820TE - SS°C to + 12S°C ±lLSB E-20A
AD7820UE - SS°C to + 12s0 c ± l/2LSB E-20A

NOTES
1
Toorder MIL-STD-883, ClassB processed parts, add/883B to part number.
Contact your local sales office for military data sheet. For U.S. Standard
Military Drawing (SMD), see DESC drawing #5962-88650.
2
E = LeadlessCcramicChipCarricr;N = PlasticDIP;P = Plastic Leaded
ChipCarricr;Q = Ccrdip;R =SOIC.

PIN CONFIGURATIONS
DIP,SOIC LCCC PLCC

! ! >' >g uz
3 2 1 20 19
~

DB2 4 )
''
o I ~
11 18 OFL
""
DB3 5 17 DB7 IMSBI
WR/RDV 6 )
AD7820
TOP VIEW
,, 16 DB&
AD7820
TOP VIEW
(Not to SAie) (Not to Scale)
MODE 7 I 15 DBS

RO a I ,, 084

9
--
10 11
- - ""
12 13

l!i ~ I I I~ c
z I +
NC= NO CONNECT JJ "' -::
NC= NO CONNECT NC= NO CONNECT J
-4- REV.A
 Typical Performance Characteristics-AD7820
12
2.0

I
~
I ..
11

1.5
\ Voo=SV
VREF=SY
TA=25°C
tp=500ns -

\
w E 10 tR 0 =600ns
:E ,...I
~ z
z w
a:
0 a:
iii :,
ffi 1.5

.
<.) 1.0
z> ~
0
<.)
I
ll
:,
"' I
8
\ '-
---
0
.,; .!!
0.5

0
-100 -100 -so so 100 150 200 300 400 500 600 700
-50 0 50 100 150
TA -AMBIENT TEMPERATURE- "C T• -AMBIENT TEMPERATURE- 'C

Conversion Time (RD Model) Power Supply Current vs. Temperature Accuracy vs. twR
vs. Temperature (not including reference ladder)

2 . 0 - - - - - - , - - - - - ~ - - ~ - - - -..... 2.0 2.0

I
1.5
V 00 =5V
VREF:::SV
T•=25"C 1.5
\ Voo=SV
I
VREF:::SV
T•=2S"C 1.5
\ Voo=SV
T.=25"C

\\
m

\
tp=SOOns tWR=600ns

=
....
I
tWR=600ns
"'....a:
I
t,. 0 =600ns
~I
Is
~
0
a:
::iw 1.0
a:
w 1.0 ffi 1.0
>-
~ t: ~

\
a:
:iz :iz !z
:J :J
0.5
~ -....._ :J
0.5 0.5
.........

o.__~~-~--.....__ __.__ _.__ _. 0 0

200 300 400 500 600 700 600 300 400 500 600 700 600 900 0 4
tsm- ns tp-ns

Accuracy vs. tRo Accuracy vs. tp Accuracy vs VREF

fVREF = VRE,=(+) - VREF (-)}
-36 10~--~---~---.-------~

V 00 =5V
-38

-40

-42 ,I
J

-48
/
/r
-48

-50
-
...... ,, i,.,,'

-52 o ....._ __.__ _~~--.......__ __,,_ _ _

1 3 4 S 7 10 20 30 40 so 70 100 OL----'-----'---_.__ __.__ ___. ~

INPUT FREQUENCY - kHz -100 -50 so 100 150 -100 -50 50 100 150
T.-AMBIENTTEMPERATURE-"C T• - AMBIENT TEMPERATURE- 'C
ENCODE RA TE = 400kHz
INPUTSIGNAL = SVp-p
MEASUREMENT BANDWIDTH = BOkHz

Signal-Noise Ratio vs. Input Frequency ttNn, Internal Time Delay vs. Output Current vs. Temperature
Temperature

REV.A -5-
AD7820
PIN FUNCTION DESCRIPTION CIRCUIT INFORMATION
BASIC DESCRIPTION
PIN MNEMONIC DESCRIPTION The AD7820 uses a half-flash conversion technique whereby
two 4-bit flash AID converters are used to achieve an 8-bit
I Analog Input. Range: VREF{ - ) to
result. Each 4-bit flash ADC contains 15 comparators which
VREF{ + ).
compare the unknown input to a reference ladder to get a 4-bit
2 DBO Data Output. Three State Output, bit O
result. For a full 8-bit reading to be realized, the upper 4-bit
(LSB)
flash, the most significant (MS) flash, performs a conversion to
3 DBI Data Output. Three State Output, bit I
provide the 4 most significant data bits. An internal DAC,
4 DB2 Data Output. Three State Output, bit 2
driven by the 4 MSBs, then recreates an analog approximation
s DB3 Data Output. Three State Output, bit 3
of the input voltage. This analog result is subtracted from the
6 WR/ROY WRITE control input/READY status
input, and the difference is converted by the lower flash ADC,
output. See Digital Interface section.
the least significant (LS) flash, to provide the 4 least significant
7 Mode Mode Selection Input. It determines
bits of the output data. The MS flash ADC also has one additional
whether the device operates in the WR-RD
comparator to detect input overrange.
or RD mode. It is internally tied to
GND through a SOµA current source.
See Digital Interface section. OPERATING SEQUENCE
8 READ Input. RD must be low to access The operating sequence for the AD7820 in the WR-RD mode is
data from the part. See Digital Interface shown in Figure 3. A set-up time of SOOns is required prior to
section. the falling edge of WR. (This SOOns is required between reading
9 INTERRUPT Output. INT going low data from the AD7820 and starting another conversion). When
indicates that the conversion is complete. WR is low the input comparators track the analog input signal,
INT returns high on the rising edge VIN. On the rising edge of WR, the input signal is sampled and
of RD or CS. See Digital Interface section. the result for the four most significant bits is latched. INT goes
10 GND Ground low approximately 700ns after the rising edge of WR. This
11 VREF{-) Lower limit of reference span. indicates that conversion is complete and the data result is already
Range: GNDsVREp(-)sVREF{ +) in the output latch. RD going low then accesses the output
12 VREF{ +) Upper limit of reference span. data. If a faster conversion time is required, the RD line can be
Range: VREp( - )s VREF{ + )sVoo brought low 600ns after WR goes high. This latches the lower 4
13 cs Chip Select Input. CS, the decoded bits of data and accesses the output data on DBO-DB7.
device address, must be low for
RD or WR to be recognized by the
converter.
14 DB4 Data Output. Three State Output, bit 4 \ I WT GOING LOW INDICATES
15 DBS Data Output. Three State Output, bit S WR
I\ I
THAT CONVERSION ~COMPLETE
ANDTHATTHEDATARESULTIS

16 DB6 Data Output. Three State Output, bit 6 500ns---- t----&00n•- ~~~~~~~J::~~~:~J
I _.....
17

18
DB7 Data Output. Three State Output, bit 7
(MSB)
Overflow Output. If the analog input is
sET-uPTIMEREau1REo
~~~~~~i~~:~IORTO
STARTING CONVERSION V1N
I Xia~\t~~:-:~.8
DECISION IS LATCHED
IS TRACKED
iNT \
\
\
~

BY INTERNAL ......_.....___
higherthan(VREF{ +) - lt2LSB),OFL COMPARATORS RD BROUGHT LOW HERE LATCHES
THE 4 LSBS INTO OUTPUT LATCH
will be low at the end of conversion. It AND ACCESSES DATA ON DB0-087

is a non three state output which

can be used to cascade 2 or more Figure 3. Operating Sequence (WR-RD Mode)
devices to increase resolution.
19 NC No connection.
20 Voo Power supply voltage, + SV

-6- REV.A
 AD7820
DIGITAL INTERFACE In the first of these options the processor waits for the INT
The AD7820 has two basic interface modes which are determined status line to go low before reading the data (see Figure Sa).
by the status of the MODE pin. When this pin is low the converter INT typically goes low 700ns after the rising edge of WR. It
is in the RD mode, with this pin high the AD7820 is set up for indicates that conversion is complete and that the data result is
the WR-RD mode. in the output latch. With CS low, the data outputs (DBO-DB7)
RD Mode are activated when RD goes low. INT is reset by the rising edge
The timing diagram for the RD mode is shown in Figure 4. In of RD or CS.
the RD mode configuration, conversion is initiated by taking The alternative option can be used to shorten the conversion
RD low. The RD line is then kept low until output data appears. time. To achieve this, the status of the INT line is ignored and
It is very useful with microprocessors which can be forced into RD can be brought low 600ns after the rising edge of WR. In
a WAIT state, with the microprocessor starting a conversion, this case RD going low transfers the data result into the output
waiting, and then reading data with a single READ instruction. latch and activates the data outputs (DBO-DB7). INT also goes
In this mode, pin 6 of the AD7820 is configured as a status low on the falling edge of RD and is reset on the rising edge of
output, RDY. This RDY output can be used to drive the processor RD or CS. The timing for this interface is shown in Figure Sb.
READY or WAIT input. It is an open drain output (no internal
pull-up device) which goes low after the falling edge of CS and
goes high impedance at the end of conversion. An INT line is
_----JI______ _
also provided which goes low at the completion of conversion.
INT returns high on the rising edge of CS or RD.

cs~ f \
RD 1-~---tcs..-,--lf- ~~---
tcss · ~ •• ~ - - -
----;~ ....
WIT=r~~:UP
I
DBD·DB7--------

-~1J--- Figure 5b. WR-RD Mode (tRo<t1NnJ

The AD7820 can also be used in stand-alone operation in the

WR-RD mode. CS and RD are tied low and a conversion is
initiated by bringing WR low. Output data is valid typically
Figure 4. RD Mode 700ns after the rising edge of WR. The timing diagram for this
mode is shown in Figure 6.
WR-RD Mode
In the WR-RD mode, pin 6 is configured as the WRITE input

-
for the AD7820. With CS low, conversion is initiated on the
falling edge of WR. Two options exist for reading data from the
converter.

:~------\ ~
~ ~tcs.. ~··~ -
tcss
DBO-DB7 -------.J----C~~¥~ )---
~I~£. Figure 6. WR-RD Mode Stand-Alone Operation,

1r
CS=RD=O

INT---'I --:--11
DB0-087-------------- I
·-=~ ~ 'Off
Figure 5a. WR-RD Mode (tRo>t,NTL)

REV.A -7-
AD7820
APPLYING THE AD7820
VoN(+) VoN
REFERENCE AND INPUT
The two reference inputs on the AD7820 are fully differential VoN(-) GND
and define the zero to full-scale input range of the AID converter. AD7820
As a result, the span of the analog input can easily be varied +sv Voo

since this range is equivalent to the voltage difference between VReFI+)

VIN(+) and VIN(-). By reducing the reference span, VREF( + )- J0.1µF J47µF VREF(-)
VREF\ - ), to less than SV the sensivity of the converter can be
increased (i.e., ifVREF= 2V then lLSB = 7.SmV). The input/refer-
ence arrangement also facilitates ratiometric operation.
Figure la. Power Supply as Reference
This reference flexibility also allows the input span to be offset
from zero. The voltage at VREF\ - ) sets the input level which
produces a digital output of all zeroes. Therefore, although VIN
is not itself differential, it will have nearly differential-input
V,N(+) VoN
capability in most measurement applications because of the
reference design. Figure 7 shows some of the configurations that V,N(-) GND

are possible. AD7820

+sv Voo

INPUT CURRENT 0.1µF 47µF 2.SV

AD580 VREF( +)
Due to the novel conversion techniques employed by the AD7820,
the analog input behaves somewhat differently than in conventional
devices. The ADC's sampled-data comparators take varying
amounts of input current depending on which cycle the conversion
J i VReF(-)

is in.
Figure lb. External Reference 2.5V Fu/I-Scale
The equivalent input circuit of the AD7820 is shown in Figure
Sa. When a conversion starts (WR low, WR-RD mode), all
input switches close, and VIN is connected to the most significant
and least significant comparators. Therefore, VIN is connected
to thirty one lpF input capacitors at the same time.
GND
The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 2k!l to Sk!l). In AD7820
addition, about 12pF of input stray capacitance must be charged.
For large source resistances, the analog input can be modelled
as an RC network as shown in Figure Sb. As Rs increases, it
takes longer for the input capacitance to charge.
In the RD mode, the time for which the input comparators *CURRENT PATH MUST
track the analog input is 600ns at the start of conversion. In the STILL EXIST/FROM
V,N ( - ) TO GROUND.
WR-RD mode the input comparators track VIN for the duration
of the WR pulse. Since other factors cause this time to be at
least 600ns, input time constants of lOOns can be accommodated Figure le. Input Not Referenced to GND
without special consideration. Typical total input capacitance
values of 4SpF allow Rs to be 1.Sk!l without lengthening WR
to give VIN more time to settle.

-8- REV.A
 AD7820
comparators' outputs are not latched while WR is low, so at
least 600ns will be provided to charge the ADC's input capacitance.
fl12pF It is therefore not necessary to filter out these transients with an
external capacitor at the VIN terminal.

INHERENT SAMPLE-HOLD
A major benefit of the AD7820's input structure is its ability to
measure a variety of high speed signals without the help of an
external sample-and-hold. In a conventional SAR type converter,
regardless of its speed, the input must remain stable to at least
'hLSB throughout the conversion process if full accuracy is to
be maintained. Consequently, for many high speed signals, this
signal must be externally sampled and held stationary during
the conversion. The AD7820 input comparators, by nature of
their input switching inherently accomplish this sample-and-hold
function. Although the conversion time for the AD7820 is l.36µs,
the time through which VIN must be V2LSB stable is much
smaller. The AD7820 "samples" VIN only when WR is low.
Figure Ba. AD7820 Equivalent Input Circuit The value of VIN approximately IOOns (internal propogation
delay) after the rising edge of WR is the measured value. This
value is then used in the least significant flash to generate the
lower 4-bits of data.
Input signals with slew rates typically below 200mV/µs can be
32pfi converted without error. However, because of the input time
constants, and charge injection through the opened comparator
input switches, faster signals may cause errors. Still, the AD7820's
Figure Bb. RC Network Model loss in accuracy for a given increase in signal slope is far less
than what would be witnessed in a conventional successive
INPUT FILTERING approximation device. A SAR type converter with a conversion
It should be made clear that transients on the analog input time as fast as lµs would still not be able to measure a SV,
signal, caused by charging current flowing into VIN will not lkHz sine wave without the aid of an external sample-and-hold.
normally degrade the ADC's performance. In effect, the AD7820 The AD7820 with no such help, can typically measure SV,
does not "look" at the input when these transients occur. The lOkHz waveforms. ·

Applications
OUTPUT
CODE FULL SCALE
TRANSITION

)-
INT
Voo 11111111
RDV
VREF VREF( +) cs 11111110
i 0.1µF i47µF
V1N V1N AD7820 RD 11111101

MODE DB7 ,, 1LSB=

FS
VREF(-) / 256
/
GND DBO I "
00000011 ~ /
00000010

00000001
Figure 9a. 8-Bit Resolution
00000000 -- ---- I I I .,
01LSB2LSB'S 3LSB'S \_ FS
1
AIN, INPUT VOLTAGE (IN TERMS OF LSB'S) FS - LSB

Figure 9b. Nominal Transfer Characteristic for 8-Bit

Resolution Circuit

REV.A -9-
AD7820

+5V Voo cs cs
MODE WR WR
~ 0.1µF ~ 47µF
RD
AD7820
RD

VREF VREF( + I
DB7
V1N V1N

DBO
VREF(-1

1kfi GND OFL

Skfi
+5V
Voo cs
MODE WR
1kfi
AD7820
RD

VREF(+I
DB7
V1N

DBO
VREF(-)

GND OFL

Figure 10. 9-Bit Resolution

25kfi

WR i-..--
AD7820"'
RD'---

+5V-~..... -----,i------~ Voo DB7

VREF(-1

~··"" GND
MODE
DBO

*SAMPLE RATE IS 20kHz.

Figure 11. Te/com AID Converter

-10- REV.A
 AD7820
CLKJ-u-

VINA V1NB

WR cs WR VREF
GND +15V

cs AD7820 Voo AD7224

RD RESET

VREF(-1 VouT Vo

087 087
Voo
LDAC
MODE
080 080
AGND
VREF VREF( + I DGND
Vss

V _ VINA• VINB
o- -5V
VREF
IF v,NA.,vREF

Figure 12. 8-Bit Analog Multiplier

SAMPLE-, ,--
PULSE L......1
+10V +15V

+15V

VouT OVTO +10V

AD7820 AD7224

cs
WR
087---- 087 LDAC

AGND
I.47µ.F MODE 0801---- 080
DGND
v +5V VREFl+I

Figu~e 13. Fast Infinite Sample-and-Hold

 AD7820
MECHANICAL INFORMATION
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

20-PIN CERAMIC 1

E]~~~]~]l=
I. . ... ··-··· ·I (25.40 :r 0.25)

...!. ......
.i:-
ffiITWff
(4.45)

..1._ -j f-0.011
J • .0.002
(D.46-r:P0.051 a.so
(2.11 ±0.231

~ 0 . 1 0 0 ......
11.211 TYP 12.54 :i:0.13)

1 4 - - - - ~ ~ !~~
TOL NON ACCUM

0.300 :t:0.010
(7.12 .:t:0.25)

. . . ~0.010~==
(o.2s~g::)
NOTES:
1. LEAD NUlmER 1 IDENTIFIED BY DOT OR NOTCH.
2. LEADS Will BE EITHER GOLD OR TIN Pl.A.TED IN ACCORDANCE
WITH ML-M-31610 REQUIREMENTS.

20-PIN CERDIP (SUFFIX Q) 20-PIN PLASTIC DIP (SUFFIX N)

NOTE
I
Analog Devices reserves the right to ship ceramic packages in lieu of cerdip packages.

-12- REV.A