2023-24_sem8papers_iitkgp
2023-24_sem8papers_iitkgp
Date of Exam: 20th February, 2024 Session: AN Duration: 2hours Full Marks: 60
Sub No: EC 60204 Sub name: Digital VLSI Circuits Number of Students: 61
Department/Center/School: Electronics &Elcctrical Communication Engineering
Specific charts, graph paper, log book etc., required: NO
Special Instructions (if any): This question paper consists of two pages. Questions are self-explanatory
and need no clarification. Answer ALL the questions. Answers to parts of aquestion must be written in
one place. Otherwise, they will NOT be evaluated. Consider velocity-saturated transistors only for
Question 3.
1. Consider an NMOS inverter circuit with saturated enhancement type NMOS load
transistor and following parameters: VDD = S.0 V; Vro-0.8 V; y= 0.4 y0s, a = 0Vl;
HnCox = S0 uAV'; 20F,subl =0.6 V; (W/L)load (2/2); (W/L)river (16/2).
(a) Draw the transistor diagram of the inverter. Calculate the values of the output
voltages VOH and VoL, considering the substrate-bias effect of the load device. Perform
two iterations only to compute both VOH and VoL. [6]
(b) Next, calculate the value of the input voltage V1L (assuming Vout =VoH to
threshold voltage of the load), and thus the noise margin NML. You must write the
compute
relevant current-voltage equation, and show all the intermediate steps. Do not write and
use any formula from memory.
[6]
(c) Finally, calculate the value of the input voltage VIH (assuming Vout = VoL to
threshold voltage of the load), and thus the noise margin NMH. Write only the compute
relevant
current-voltage equation and showall the intermediate steps. Do not write and use any
formula from memory.
[7]
2a) How does one define a symmetric CMOS inverter? For a symmetric CMOS
inverter, derive an appropriate expression for VIL (the lower salient input voltage) in
terms of only VDD and VTO,n. Do not write and use any formula from memory. Hint:
consider the regions of operation of the two transistors at Vin= VIL. Calculate the vahbe e
VL for VDD =3.3 V and VTo,n =0.75 V.
'nique
4(ayfor what type of digital circuits is subthreshold leakage current amatter of concem.,
and why? Write the complete current-voltage expression for an NMOS transistor in
subthreshold region, that is based on modeling it as a bipolar-junction transistor (BJT).
Clearly state all the parameters involved in the expression, and which regions of the
NMOS transistor correspond to which regions of a BJT.
If the measured values of the subthreshold current are 10 nA at VGs = 125 mn÷ and 100
nAat VGs = 205 mV, calculate the values of the subthreshold swing parameter, and the
slope factor in mV/decade. [9]
tH Explain the advantage and the disadvantage of fabricating the resistor RL (for a
resistive-load inverter) bymeans o() isolated ditfusion region with one contact on each
end and (ij) un-doped poly-silicon. Draw suitable diagrams and mention values of typical
sheet resistivity of the two structures. (8]
2
-+ydra
C
D
Date of Exam: 23rd Aprit, 2024 Session: AN Duration: 3 hours Full Marks: 100
Sub No: EC 60204 Sub name: Digital VLSI Circuits Number of Students: 61
Department/Center/School: Electronics &Electrical Communication Engineering
Specific charts, graph paper, log book etc., required: NO
Special Instructions (if any): This question paper consists of three pages. Ouestions are
self-expianatory and need no clarification. ANSwer ALL the guestions. Answers to parts of
aquestion must be written in one place. Otherwise, they will NOT be
evoluated.
Ka) (i) Draw thc transistor diagram of a simple bi-stable scqucntial circuit madc of
two
identical cross-couplcd CMOS invertcrs. Show how thc two stablc states and onc quasi
stable (unstablc) statc of the circuit can bc idcntíficd by drawing
characteristics of this circuit. voltagc-transfcr
3
(ii)Assume that the bi-stablc circuit is initially
operating at thc unstable opcrating point,
Viz. Vol= Vo2 - VM (or Vs) wherc Vs is thc switching
threshold voltagc of a CMOS
inverter. Morcover, assumc that thc input (gatc) capacitancc Cy of cach
greater than its output (drain) capacitancc Co. Devclop (do not invertcr is much
memory) a second-order differential equation describing the simply state from
gate charge of an inverter. time-dormain behavior of
[4)
(iii) Using Laplace transform, solve the above
dependent variation of the output voltages of the twodifferential
inverters.
equation to obtain time
(6]
(iy`how how with small initial perturbation (change) of output voltages, the
Eircuit will settle into onc of the two stable states. Draw the bi-stable
the transient signals at the output of the corresponding waveform of
two ínverters. [2}
Draw the transistor diagram of aSR latch using
CMOS
such that the sum of the delay from S to 0 and that from RNOR gatcs. Design this latch
to 0 is 600 ps. Assume the
total load to be driven by )and 0 is 150
cach, and that for cach transistor, Z !00
nm. Lse the relationship lpH, tPLH
K2i.Find W, and W. that is, the size0.7ReC'. Also, Regn 12.5 KS2/C, and Reqp
(width) of NMOS and PMOS transistors n um
L) Derive the layout of the comnley gate with minimum number of diffusion breaks to
Tcauce the separation betwccn the nolv.silicon gatc columns. Use graph models to find a
Eulcr path common to both the n.channel and the n-channel nctworks. Draw the
Symbolic layout that shows all the source and drain connections. State the number of
contact cuts needed in p-diffusion and n-diffusion blocks. [8]
(e) Draw the transistor diagram of a CMOS 2-input NOR gate. Next, draw its layout
using single-layer metal and single-layer poly-silicon (noting that the (W/L)p= 2(W/L)N).
Clearly indicate the metal, diffusion, n-well and poly-silicon layers as well as the contact
Cuts. [4]
the two
multi-llevel CMOS implementations of an 8-input AND (ANDS)
4. Consider INV-NOR2-NAND4-INV and INV-NOR4-NAND2-INV.
gate, nanely
diagram of both the configurations, and prove that the output of these
Draw the gate product innt..ins of eight Boolean variables in1, ..., ins. [3]
are indeed theAND
Iwo
simply state from memory) the logical effort (LE) values and the
Compute(donotvalues for
both static CMOS NAND4 (4-input NAND) and NOR4 (4- prc
6) (P) symbolic layouts ofa NAND4 gate and a NOR4 gate which
parasiticterm Drawthe 1e
gates.
input NOR) CN
dis
2 . v ea
4-5 7 SPS
hclp in ca<eulating the P terms. [6]
, (©For both the above configurations, consider the input capacitancc to be 2 fF, and the
utput load capacitance to be 200 fF. Compute the path effort, optimal stageeffort SE",
andtotal path delay (both normalized valuc and absolute valucs in picoscconds (ps) for
the above two configurations. In this connection, state/compute tinv (intrinsic time
constant of a minimum-sizcd inverter) in picoscconds (ps). 22- b [91244
( n your opinion, which onc of the above two options is better? Comment on the
statement, "merc knowledgc of LE of gates in a logic path cannot hclp decide which
configuration is better." [2]
5. ýAssumc that astatic CMOS thrcc-input NAND gatc (built with minimum-sizcd
transistors and ensuring symmetrical rise and fall times) having inputs A, B and C drivcs
a CMOS transmission gate (TG) made of minimum-sized transistors. Let sel be the
control input of the TG. Compute LE input ^and LE inputsel where "LE" represents
logical effort. Draw the complete transistor diagram and the equivalent circuit for finding
the logical effort. Re-compute LE input, Aand LE input sel if one increases only the
size of the TG to four times the minimúm'S1ze. (6]
(c) Logical implication, written as "A implies B" or Implies (A, B), is a switching
function of two variables A and B. It produces a false valuc just in case the first operand
for all other cases.
A is true and the second operand B is false. It produces true values
it can be
Write the truth table of the Boolean Function Implies (A, B), and show how
expressed in minimal algebraic form (using AND, NOT and OR operators). Similarly.
be called as
write the algebraic formn of its complement function which may
(A, B) and
Not _Implies (A, B). Now, realize both the 2-variable functions Implies
structure. Draw the
Not Implies (A, B) using a dual-rail (differential) domino logic while obtaining the
complete transistor diagram. Mention the disadvantagcs that result
for this. |10]
Cxtra (complementary) output. Suggest possible remedy
A
3
)nderSEM?
CAD FOR VLSI (EC61202)
ENDSPRING SEMESTER EXAMINATION 2023-24
Total Marks: 50
Time: 3 hours
Answer First Four questions and Any One part from question 5
of part (b) of any one of the first four questions
You may answer rest three parts of question5 n ieu
in Fig. I by applying
1. ()Bipartition the graph shown Assume B
initial A
Kemighan-Lin algorithm.
Showall the
partitioning of {A,B,C.D), (E,EG,H}. obtained.
graph
intermediate steps. Draw the final
[6] Antil artition
Mention the final cut-cost achieved.
heuristics to bipartition
| ) Apply Fiuccia-Mattheyses
1, with a maximum allowed E
G
the graph shown in Fig. partitioning Fig. 1
imbalance of +1 node. Assume an initial
Show all the intermediate
of {A,B,C,D}, {E,F,G,H). J
obtained. Mention the A 0 0, BC D 0EFGH
steps. Draw the final graph [6]
final cut-cost achieved.
problem shown in
Solve the 2-metal channel routing
number of horizontal tracks BFC DA 0GJHE 00
Fig. 2 using minimum connections and
north-south
using Metal 1 for Fig.2
connections. [6]
Metal 2for east-west
to minimize
solution of Question 2(a), allocate two different meial layers
(b) Starting with the
(constrained via minimization) approach. Drav the final
a CVM
the number of vias with contrasting colors).
distinguishing between Metal_1 and Metal_2 (choose
solution clearly the vias in your drawing
the total number of vias used and indicate the position of [6]
Mention
clearly.
shown therein, draw the
shoWn in Fig. 3 and for the input waveforms
3. qeFor the circuit event-driven
point Y (with proper timing information), by applying
waveform at the output
that the propagation delay of
the NAND
time units 0 to 80 given
simulation technique for the event queue and
that of the INVERTER is 2 time units. Sketch
gate is 5 time units and (6]
CMOS static logic implementation)
the gate queue. [Assume full
20 40 60 80
0
B
B
D
S
Fig. 3
Fig.3 on a
notation, draw the portable layout for the circuit shown in
(b)LSing stick diagram
minimizing the nåmber of isolation transistors. Mentionthe colour
fishbone framework while [6]
your drawing. |Assume full CMOS static logic implenentation}
codes usedin
PLEASE TURN OVER
CADEOR VISI(EC6! 202)
using
4. («) or the newok of ombinatorial
blocks shown in Fig. 4, distribute the net delays
(AT) of the
the inpt indicafe the arrival time
ze0 slack algoithm. The nunnbers at delay
the required time (RT ). Propagation
signals and the numbers at the output indicate nswer, redraw
witten msile the blocks. As the final
of the blocks ae shown as nunnbers (6|
the correspondling nets.
written beside
the netuOrk with all the net delays clearly
(RT)
(AT) DCB A
3 24
5
0 0 0 |
26
7
8
lig. 4
A. 8
INDIAN INSTITUTE OF TECHNOLOGY
End Spring Semester Examination
NANOELECTRONICS (EC 60294)
ullMarks: 6o, Time: 3 Hours
Instructions
Allwaveform sketches /diagrams must be neatly drawn and
clearly labeled. Answers must be brief and
to the point.
Answer all the questions (10x6=60).
For every Question No., start your answer from anewW page.
Avoid writing answers of the various parts of a single question at different locations in your
Given parameters which you might require: answer-script.
Mass of electron -9.11X103kg, Mass of a proton 1.67x10-kg, Speed of light - 3x10® m/sec,
Planck's constant-6.63x1o:34Jsec, Boltzmann constant - 1.38x10-23 J/K
For any value related to any particle parameter or quantum parameter, which you may find not given with a problem,
assume suitable value for such parameter.