INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR

Mid-Spring Semester 2023-24

Date of Exam: 20th February, 2024 Session: AN Duration: 2hours Full Marks: 60
Sub No: EC 60204 Sub name: Digital VLSI Circuits Number of Students: 61
Department/Center/School: Electronics &Elcctrical Communication Engineering
Specific charts, graph paper, log book etc., required: NO
Special Instructions (if any): This question paper consists of two pages. Questions are self-explanatory
and need no clarification. Answer ALL the questions. Answers to parts of aquestion must be written in
one place. Otherwise, they will NOT be evaluated. Consider velocity-saturated transistors only for
Question 3.

1. Consider an NMOS inverter circuit with saturated enhancement type NMOS load
transistor and following parameters: VDD = S.0 V; Vro-0.8 V; y= 0.4 y0s, a = 0Vl;
HnCox = S0 uAV'; 20F,subl =0.6 V; (W/L)load (2/2); (W/L)river (16/2).
(a) Draw the transistor diagram of the inverter. Calculate the values of the output
voltages VOH and VoL, considering the substrate-bias effect of the load device. Perform
two iterations only to compute both VOH and VoL. [6]
(b) Next, calculate the value of the input voltage V1L (assuming Vout =VoH to
threshold voltage of the load), and thus the noise margin NML. You must write the
compute
relevant current-voltage equation, and show all the intermediate steps. Do not write and
use any formula from memory.
[6]
(c) Finally, calculate the value of the input voltage VIH (assuming Vout = VoL to
threshold voltage of the load), and thus the noise margin NMH. Write only the compute
relevant
current-voltage equation and showall the intermediate steps. Do not write and use any
formula from memory.
[7]
2a) How does one define a symmetric CMOS inverter? For a symmetric CMOS
inverter, derive an appropriate expression for VIL (the lower salient input voltage) in
terms of only VDD and VTO,n. Do not write and use any formula from memory. Hint:
consider the regions of operation of the two transistors at Vin= VIL. Calculate the vahbe e
VL for VDD =3.3 V and VTo,n =0.75 V.

(byDraw the transistor diagram as well as the corresponding layout of a

built using an n-well and a p-substrate) in which the PMOS transistor CMOS inverter
width is twice
of the NMOS transistor, and the lengths of the two
transistors are equal, Take narethat
to
reduce the area so as to allow not mOre than two collinear contact cuts (that is in a
straight line). Show clearly the different conducting layers in your layout. [4]
Please turn over [P.T.0.]
 W

'nique

(- 3. Draw transistor diagrams of a CMOS and a

pscudo-nMOS invcrter. Size thc two
inverters (i.c. caleulate the widths (in um) of both the pull-up and the pull-down
transistors) in order to satisfy the following spccifications (or spccs), whcn thc output
sper load is a capacitancc of valuc 50 (F (| F 10 F), Assume
the velocity-saturated deviccs
with the following paramctcrs: Vpp- 1.2 V, VIN 0,4 V, Vip--0.4 V, Cox L.6 uFlcm',
leve n 270 cm'/N-s, Hp 70 cm/V-s, critical ficlds En - 6x 10 V/cm and Ecp 24 × 10
V/cm, channcl lcngth L = 100 nm (for both nMOS and pMOS
r re velocity Vsat = 8X 10° cm/scc and 2. =0 V' (for both nMOS and pMOS).transistors); saturation
P= Specs for CMOS inverter: (tpH- tPLH) < 50 ps: VoH = 1.2 V and VoL. = 0 V; low dc
power, minimum arca. 2-l
or
Specs for pseud0-nMOS inverter: tpHL< 50 ps; VoH = 1.2 V and Vo = 0.08 V;
av minimum
dc power; minimum area.
Adopt a simple timing model which states that the propagation delay equals 0.7 times the
product of average on-resistance and load capacitance.
Logically explain how you can arrive at proper values for the widths of the pull-up and
pull-down transistors for both CMOS and pseudo-nMOS inverters so that all the above
specs are satisfied. State the relevant algebraic current-voltage expressions before
using
numerical values of parameters.
Also, compute the value of the propagation delay tpLH in ps (pico-seconds) for the
pseudo-nMOS inverter with the transistor width obtained by you.
Mention the advantage and disadvantage of using pseudo-nMOS gates as compared to
CMOS gates. [13]

4(ayfor what type of digital circuits is subthreshold leakage current amatter of concem.,
and why? Write the complete current-voltage expression for an NMOS transistor in
subthreshold region, that is based on modeling it as a bipolar-junction transistor (BJT).
Clearly state all the parameters involved in the expression, and which regions of the
NMOS transistor correspond to which regions of a BJT.
If the measured values of the subthreshold current are 10 nA at VGs = 125 mn÷ and 100
nAat VGs = 205 mV, calculate the values of the subthreshold swing parameter, and the
slope factor in mV/decade. [9]
tH Explain the advantage and the disadvantage of fabricating the resistor RL (for a
resistive-load inverter) bymeans o() isolated ditfusion region with one contact on each
end and (ij) un-doped poly-silicon. Draw suitable diagrams and mention values of typical
sheet resistivity of the two structures. (8]

*** END OF THE QUES APER***

2
 -+ydra

CAD FOR VLSI

(EC61202)
Mid Spring Semester Examination 2023-24
Time: 2 Hours Total Marks: 3)

Answer ALL the questions

1 By using spectral technique, synthesize a tributary logic network for
realizing the Boolean function as shown in the Truth Table here. Draw DCBA
the gate level circuit. Show the decision making
calculations.
2,(a) For real primary inputs A, B, C, D, E, F, G, H, we
need to Compute
P=y\(AB+CD)+v(EF+GH). Draw an appropriate Schedule
for computing P in minimum possible control steps, where the
available resources are two square-root computing
units,
multipliers and two adders. Assume that the delays of the adder, two
the
multiplier and the square-root computing unit are identical. Show
the Allocation on the Schedule
itself. [4)
(Assuming that the primary inputs are always available, draw the
Binding for the above Schedule while keeping the
usage of the
multiplexers minimum. [4]
3.4á) Bipartition the graph sthown in Fig. 1by
algorithm. Assume an initial partitioningapplying Kernighan-Lin
of
{E,F,G,H}. Show all the intermediate steps. Draw the {A,B,C,D},
1
final graph
obtained. Mention the final cut-cost achieved.
[4J
6) Apply B
Fiduccia-Mattheyses
graph shown in Fig. 1,
heuristics to bipartition the
with maximum allowed imbalance
a
of ±1 node. Assume an initial Initial Partition
partitioning of (A,B,C,D},
{E,F,G,H}. Show all the intermediate steps. Draw the final
graph obtained. Mention the final cut-cost
achieved.
Fig. 1
4. Draw the symbolíc layout of a full
that realizes the Boolean function CMOS static logic circuit using stick diagram
Y=AB + CDE,(note that the representation,
i.e. it does not have a bar over the function is not complementary,
expression) on a fishbone framework without using any
isolation transistor. Mention whích colour is used for which layer.
[4)
S. Draw the full CMOS static logic
circuit (22 transistors) to realize the gate level
below. Optimíze the circuit by using circuit shown
number of transistors without transformation at the transistor level to obtain minimum
compromizing the noise margin. Draw the intermediate steps. (5)
A

C
D

END OF QUESTION PAPER

 INDIAN INSTITUTE OF TECHNOLOGY
Mid Spring Semester Examination
NANOELECTRONICS(EC 60294)
Full Marks: 60, Time: 2 Hours
Instructions
Al waveform sketches / diagrams must be neatly drawn and clearly labeled. Answers must be brief and to the
point.
Answer all the questions (10x6-60).
Ihe final answers (numerical values with unit) should be
For every Question No., start your underlined or enclosed within Dox with unit.
Given parameters which you might answer from a newpage.
Mass of electron -9.11x10'kg, Massrequire:
ofa proton - 1.67x1027'kg, Speed of
Planck's constant -6.63x10-34Jsec, Boltzmann light-3x10° m/sec,
constant -1.38x1023 J/K, Charge
For any value related to any particle parameter or of an electron- 1.6x10C
assume suitable value for such parameter. quantum parameter, which you may find not given with a problem,
248 nm
A. Find out the wavelength
2. The AIGaAs/GaAs has a two associated with 5 eV photon and 5 eV
electron.
the channel width is &nm, thedimensional
pinch off
electron gas concentration of 1x1012/cm², the spacer is5
nm,
AlGaAs is 108/cm3. The Schottky barriervoltage is 1.5 V, AEc/q=0.23 V, and the doping
height is o.8 V. Find the thickness of the dopedconcentration of
threshold voltage. AlGaAs and the
3,Consider particle of mass m held in a one-dimensional potential V(x).
a
is constant, V(x)=V. For this region, find Suppose that
thé stationary states of the particle when in some region V(x)
energy of the particle. Ant E=V, where E is the
B) What is the probability of locating a
height box of length L (i.e. dimension x=o particle of mass n between x=L/4 and x=L/2 in a 1-D
to x=L)? Assume the particle is in the infinite
n=1 energy state.
t4. A) Light of wavelength 4000 Åis incident on a
maximum kineticenergy of emitted photoelectron?metaller plate whose work function is 2 eV. What is the
B) In a photoelectric experiment, the
to400 nm and (hc/e = 1240 nm-V.wavelength
of the light incident on metal is
Find the changed from 300 nm
8. A) Describe the fabrication steps of decrease in the stopping potential. Lo33r
çompared to other techniques? C) WhatReplacement
is shadow
Fins. B) What is the advantage of this
effect in Fin FET fabrication? technique
6. A) A MOSFET has a threshold voltage of
current of MOSFETis o.1 uA at threshold o.,5V and subthreshold slope of 100
voltage. mV/decade. The drain
B)What is LDD in short channel MOSFET and whyWhat is the subthreshold leakage current at Ve=oV. I0
7A)Ina Davisson-Germer experiment, an electron it is required?
plate. The angle between incident and reflected beam of energy 60 eV is incident on a polished metal
electrons. If this beam is used to get diffraction patternbeam is 60°. Find the wavelength associated with
crysta plane of the metal for first order maxima (i.e. n=1)of the same plate, then find the distance between
BYWhy HKMG is required for new generation FET? using the above findings. (-S&A
8/A) Why next generation Fin FET is thinner and taller?
be reduced? B) Draw the variation of What is corner effect in Fin FET, how this efect can
in short channel MOSFET, and explain. threshold voltage with respect to MOSFET channel length and width
9.AWhat is the advantage and disadvantage of pre-CMOS
nano-material? B) Why Ga,In(-)As is usually grown on InPcompared
for
to post-CMOS integration of
x=0.47? C) Advantage of SOI Fin
sompared to bulk Si Fin.
o Explainthe working principle of AlGa(1-»)As/ GaAs
B Slate advantage and disadvantage of increase the based HEMT structure.
Why value of x.
spacer layer is important in above HEMT structure.
 INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR
End-Spring Semester 2023-24

Date of Exam: 23rd Aprit, 2024 Session: AN Duration: 3 hours Full Marks: 100
Sub No: EC 60204 Sub name: Digital VLSI Circuits Number of Students: 61
Department/Center/School: Electronics &Electrical Communication Engineering
Specific charts, graph paper, log book etc., required: NO
Special Instructions (if any): This question paper consists of three pages. Ouestions are
self-expianatory and need no clarification. ANSwer ALL the guestions. Answers to parts of
aquestion must be written in one place. Otherwise, they will NOT be
evoluated.

Ka) (i) Draw thc transistor diagram of a simple bi-stable scqucntial circuit madc of
two
identical cross-couplcd CMOS invertcrs. Show how thc two stablc states and onc quasi
stable (unstablc) statc of the circuit can bc idcntíficd by drawing
characteristics of this circuit. voltagc-transfcr
3
(ii)Assume that the bi-stablc circuit is initially
operating at thc unstable opcrating point,
Viz. Vol= Vo2 - VM (or Vs) wherc Vs is thc switching
threshold voltagc of a CMOS
inverter. Morcover, assumc that thc input (gatc) capacitancc Cy of cach
greater than its output (drain) capacitancc Co. Devclop (do not invertcr is much
memory) a second-order differential equation describing the simply state from
gate charge of an inverter. time-dormain behavior of
[4)
(iii) Using Laplace transform, solve the above
dependent variation of the output voltages of the twodifferential
inverters.
equation to obtain time
(6]
(iy`how how with small initial perturbation (change) of output voltages, the
Eircuit will settle into onc of the two stable states. Draw the bi-stable
the transient signals at the output of the corresponding waveform of
two ínverters. [2}
Draw the transistor diagram of aSR latch using
CMOS
such that the sum of the delay from S to 0 and that from RNOR gatcs. Design this latch
to 0 is 600 ps. Assume the
total load to be driven by )and 0 is 150
cach, and that for cach transistor, Z !00
nm. Lse the relationship lpH, tPLH
K2i.Find W, and W. that is, the size0.7ReC'. Also, Regn 12.5 KS2/C, and Reqp
(width) of NMOS and PMOS transistors n um

2.Consider a single-stage static full CMOS complex gate with

(WIL)p 20 and (W/L)n the transistor siZes as
15 to realize 9-variable function
F-A C D G + P0 R S
+

Please turn over |P. T.0./

 and
Assume that all variables are present both in normal (un-complcmcnted)
diagram of the complex gate.
omplemented forms. Derive the complctc transistortransistors
Calculate the (W/L) sizes of the PMOS and the NMOS of an equivalent static
(MOS inverter circuit for simultanenus switching of all inputs. 2/- 6

L) Derive the layout of the comnley gate with minimum number of diffusion breaks to
Tcauce the separation betwccn the nolv.silicon gatc columns. Use graph models to find a
Eulcr path common to both the n.channel and the n-channel nctworks. Draw the
Symbolic layout that shows all the source and drain connections. State the number of
contact cuts needed in p-diffusion and n-diffusion blocks. [8]

(e) Draw the transistor diagram of a CMOS 2-input NOR gate. Next, draw its layout
using single-layer metal and single-layer poly-silicon (noting that the (W/L)p= 2(W/L)N).
Clearly indicate the metal, diffusion, n-well and poly-silicon layers as well as the contact
Cuts. [4]

Consider complementary pass transistor (CPL) logic implementation of a 1-bit full

3. (97 which involves three inputs A (addend bit), B (augend bit) and Cin (carry input
adder,
S
bit), and two outputs S (sum bit) and Cout (carry output bit). Express the two outputs
variables A, B and Cin, using
and Cout as well as their complements as functions of three contro!
of sum and carry output functions, and taking A and Cin as
variables. property
inverting Based on this, draw the complete transistor diagrams for realizing the sum and
carry output functions (along with their complements) by CPL logic. Compare betvween
total number of transistors required for sum and its complement vs. that required for carry
reason for the difference? [10]
output and itscomplement. What is the
EDP regarded as a
(b Define energy-delay product (EDP) of a digital gate. Why is the designs
compare performing
Vhetter metric than the power-delay product (PDP) in order to designs on a qualitative
+he same operation? Show how one can plot the EDP of several
delay and EDPcan be plotted on the
Granh of energy vs. 1/delay. Also, sh0w how energy,
graph as a function of the supply voltage VDD. Derive (do not simply
same normalized
the optimum valuc of VDp for which EDP is minimizcd for a given
write from memory) [6]
technology.

the two
multi-llevel CMOS implementations of an 8-input AND (ANDS)
4. Consider INV-NOR2-NAND4-INV and INV-NOR4-NAND2-INV.
gate, nanely
diagram of both the configurations, and prove that the output of these
Draw the gate product innt..ins of eight Boolean variables in1, ..., ins. [3]
are indeed theAND
Iwo
simply state from memory) the logical effort (LE) values and the
Compute(donotvalues for
both static CMOS NAND4 (4-input NAND) and NOR4 (4- prc
6) (P) symbolic layouts ofa NAND4 gate and a NOR4 gate which
parasiticterm Drawthe 1e

gates.
input NOR) CN
dis
2 . v ea
 4-5 7 SPS
hclp in ca<eulating the P terms. [6]

, (©For both the above configurations, consider the input capacitancc to be 2 fF, and the
utput load capacitance to be 200 fF. Compute the path effort, optimal stageeffort SE",
andtotal path delay (both normalized valuc and absolute valucs in picoscconds (ps) for
the above two configurations. In this connection, state/compute tinv (intrinsic time
constant of a minimum-sizcd inverter) in picoscconds (ps). 22- b [91244
( n your opinion, which onc of the above two options is better? Comment on the
statement, "merc knowledgc of LE of gates in a logic path cannot hclp decide which
configuration is better." [2]

5. ýAssumc that astatic CMOS thrcc-input NAND gatc (built with minimum-sizcd
transistors and ensuring symmetrical rise and fall times) having inputs A, B and C drivcs
a CMOS transmission gate (TG) made of minimum-sized transistors. Let sel be the
control input of the TG. Compute LE input ^and LE inputsel where "LE" represents
logical effort. Draw the complete transistor diagram and the equivalent circuit for finding
the logical effort. Re-compute LE input, Aand LE input sel if one increases only the
size of the TG to four times the minimúm'S1ze. (6]

transmission design a circuit whose output is

Using gates,
oUT = ABC + ABC+4. Use A and B as the control signals for the transmission
gates (TG). Draw the complete TG diagram for simple (un-optimized) design. Next,
optimize the design by combining signal transmission paths, and removing the redundant
transistors/switches. Draw the optimized gate diagram. Now, to reduce silicon area
occupied by TG circuits, try to place all PMOS transistors in a single n-well. In that case,
show by drawing a nedt transistor diagram how the polysilicon signal lines can be laid in
parallel and connect to the gates of all the transistors. [8]

(c) Logical implication, written as "A implies B" or Implies (A, B), is a switching
function of two variables A and B. It produces a false valuc just in case the first operand
for all other cases.
A is true and the second operand B is false. It produces true values
it can be
Write the truth table of the Boolean Function Implies (A, B), and show how
expressed in minimal algebraic form (using AND, NOT and OR operators). Similarly.
be called as
write the algebraic formn of its complement function which may
(A, B) and
Not _Implies (A, B). Now, realize both the 2-variable functions Implies
structure. Draw the
Not Implies (A, B) using a dual-rail (differential) domino logic while obtaining the
complete transistor diagram. Mention the disadvantagcs that result
for this. |10]
Cxtra (complementary) output. Suggest possible remedy

*** END OF THE (ÌUESTION PAPER***

A
3

)nderSEM?
 CAD FOR VLSI (EC61202)
ENDSPRING SEMESTER EXAMINATION 2023-24
Total Marks: 50
Time: 3 hours

Answer First Four questions and Any One part from question 5
of part (b) of any one of the first four questions
You may answer rest three parts of question5 n ieu

in Fig. I by applying
1. ()Bipartition the graph shown Assume B
initial A
Kemighan-Lin algorithm.
Showall the
partitioning of {A,B,C.D), (E,EG,H}. obtained.
graph
intermediate steps. Draw the final
[6] Antil artition
Mention the final cut-cost achieved.
heuristics to bipartition
| ) Apply Fiuccia-Mattheyses
1, with a maximum allowed E
G
the graph shown in Fig. partitioning Fig. 1
imbalance of +1 node. Assume an initial
Show all the intermediate
of {A,B,C,D}, {E,F,G,H). J
obtained. Mention the A 0 0, BC D 0EFGH
steps. Draw the final graph [6]
final cut-cost achieved.

problem shown in
Solve the 2-metal channel routing
number of horizontal tracks BFC DA 0GJHE 00
Fig. 2 using minimum connections and
north-south
using Metal 1 for Fig.2
connections. [6]
Metal 2for east-west
to minimize
solution of Question 2(a), allocate two different meial layers
(b) Starting with the
(constrained via minimization) approach. Drav the final
a CVM
the number of vias with contrasting colors).
distinguishing between Metal_1 and Metal_2 (choose
solution clearly the vias in your drawing
the total number of vias used and indicate the position of [6]
Mention
clearly.
shown therein, draw the
shoWn in Fig. 3 and for the input waveforms
3. qeFor the circuit event-driven
point Y (with proper timing information), by applying
waveform at the output
that the propagation delay of
the NAND
time units 0 to 80 given
simulation technique for the event queue and
that of the INVERTER is 2 time units. Sketch
gate is 5 time units and (6]
CMOS static logic implementation)
the gate queue. [Assume full
20 40 60 80
0

B
B
D
S

Fig. 3
Fig.3 on a
notation, draw the portable layout for the circuit shown in
(b)LSing stick diagram
minimizing the nåmber of isolation transistors. Mentionthe colour
fishbone framework while [6]
your drawing. |Assume full CMOS static logic implenentation}
codes usedin
PLEASE TURN OVER
 CADEOR VISI(EC6! 202)

using
4. («) or the newok of ombinatorial
blocks shown in Fig. 4, distribute the net delays
(AT) of the
the inpt indicafe the arrival time
ze0 slack algoithm. The nunnbers at delay
the required time (RT ). Propagation
signals and the numbers at the output indicate nswer, redraw
witten msile the blocks. As the final
of the blocks ae shown as nunnbers (6|
the correspondling nets.
written beside
the netuOrk with all the net delays clearly
(RT)
(AT) DCB A
3 24
5
0 0 0 |
26
7
8
lig. 4

For the truthtable provided here, by applying spectral technique,

(b) using only AND/OR gates.
You
svnthesize a tributary network inverter at
complemented input(s), but MUST N0T Use |0 0 0 -0
ay use steps
used. Show lhe intermediate
the output of any of the gates
decisions at every logic level. Draw
andmention the basis of vour [6]
the final gate level diagrann.
|10 0 0.

Answer Any One

lieu of part (b) of any one
(You may answer all the parts in (Please mention]) [2 + (6)]
of the first four questions
the arrangement ABOC of
Mention the conditions for having zero wasted space in (2]
()
their widths and heights.
the blocks A, B andC, in terms of
components, SABe iS having
For aBoolean function f(A, B, C), amongst all the spectral
(ii) table enries
highest magnitude (- 6 ), though with a negative sign, since the truth
the generator-modifier based
are mismatching everywhere excepting for CBA. Draw the
(21
logic realization for the same.
R (which are
We need to find out the fourth root of each of the three variables P, Q and
1 (üY computing resources, we are having only wo
available always as primary inputs). As square root of a nunber. Draw the
)
the
combinatorial units, each of which can compute
minimun number of control steps (showing
Schedule for the same having
Allocation/Binding is not necessary). [2]
using 'even transistor th
(iv) Optimize the adjacent circuit by nunber of transistors
ransformation' 10 obtain minimum
Draw the
without compromizing the noise margin.
intermediate steps as well. (Assun e full CMOS logic AB
implementation).

A. 8
 INDIAN INSTITUTE OF TECHNOLOGY
End Spring Semester Examination
NANOELECTRONICS (EC 60294)
ullMarks: 6o, Time: 3 Hours
Instructions
Allwaveform sketches /diagrams must be neatly drawn and
clearly labeled. Answers must be brief and
to the point.
Answer all the questions (10x6=60).
For every Question No., start your answer from anewW page.
Avoid writing answers of the various parts of a single question at different locations in your
Given parameters which you might require: answer-script.
Mass of electron -9.11X103kg, Mass of a proton 1.67x10-kg, Speed of light - 3x10® m/sec,
Planck's constant-6.63x1o:34Jsec, Boltzmann constant - 1.38x10-23 J/K
For any value related to any particle parameter or quantum parameter, which you may find not given with a problem,
assume suitable value for such parameter.

QA) What is ballistic transportin nanostructure?

B) From random thermal motion model find out the drift current density equation.
C) Discuss the effect of (1) dopant concentration and (ii) temperature on carrier mobility.
Q2What is coulomb diamond in a single electron transistor?
E Findout the capacitor value associated with a Coulomb Blockade at T=4K
C) Ifan electron and photon have the same kinetic energy, show which one has shorter de Broglie wavelength?
Q8.A) Ambipolar nature is usually visible in CNT based FET, why?
B) How bandgap of graphene can be modified.
C)Compare mechanical and liquid exfoliated graphene with respect to yield and quality.
Q4. A) Compare projection lithography and contact lithography.
B) What is the advantage of phase shift mask?
) What is proximity effect in e-beam lithography?
Q5. A) Compare SADP and LELE pattern lithography.
B)HOW multi-patterning is used to increase density 8 times?
C) Draw I-V characteristics of RTD, why there are multiple peaks and valleys?
Q6 AAn HBT has bandgap of emitter 2 eV and base 1.43 eV. Find out the improvement in Bcompared to BJT made of
L43 eV bandgap material.
CBAdvantage and challenges associated with reduction of base width in BJT.
)Pnd lattice constant of the crystal under study in XRD. The first order peak obtained from (220) plane for x-ray
yavelength 25 pm at = 5°.
7A) Consider a particle of mass mheldin a one-dimensional potential V(x). Suppose that in some region V(x) is constant
V)=V, For this region, find the stationary states of the particle when (a) E>V and (b) E<V, where Eis the energy
of the particle.
B) Atiny particle of díameter 1 m and mass m=1015 kg. Calculate the De Broglie wavelength corresponding to this
particle ifits speed is 1 mm/sec.
Q8, AJ Consider a particle of mass1030 kg trapped in an infinite potential well of width o.5 nm. (a) Find the value of
wave number in the ground state. (b) How many states are there having value of k between 1o nm and
100 nm,
B) pwAuger electron ís generated?
09. A) Adyantageof SoI compared to conventional Si wafer.
Compare of bybrid andmonolithic approach for integrating of MEMS/ nanostructures with CMOS.
Howseveralmetal layers on the same wafer helps in progress of Moore's law?
Q10,4)ompare top gate and back gate CNT FET,
B How nano protrusions can be distinguished from flat surface under SEM?
CYn AFM, why there is attractive arnd repulsive regime?