EECE 3051 : VLSI DESIGN

Dr. S.Karthick
Associate Professor - EECE
To be an exceptional
knowledge-driven institution
advancing on a culture of
honesty & compassion to make
a difference to the world.
Build a dynamic Nurture valuable futures with
global perspectives for our
application-oriented students by helping them find
education ecosystem their ikigai.
immersed in holistic
development.

Drive impactful integrated Permeate a culture of kindness

research programmes to generate
new knowledge, guided by within GITAM,
integrity, collaboration, and fostering passionate contributors.
entrepreneurial spirit.
Department of
Electrical ,
Electronics
& Vision &
Mission
Communication
Engineering
GITAM will be an exceptional
knowledge-driven institution
advancing on a culture of
honesty and compassion to

make a difference to the world

Empower the students with knowledge to face real-world challenges for
holistic development.

Conduct multidisciplinary research that makes an impact on society,

addressing key challenges through innovative solutions.

Foster a culture emphasizing empathy, respect, commitment upholding

the ethical standards.
Programme Objectives (POs)
 Programme Specific Outcomes(PSOs):

PSO1: Demonstrate comprehensive knowledge and practical skills in Electronics

and Communication Engineering focusing on subareas of Aerospace and
Defence Electronics, Telecommunications, Sensors and IoT, AI and ML
Applications and Software Defined Vehicles and apply this knowledge to solve
advanced problems.

PSO2: Design and translate abstract concepts in circuits, communications, signal

processing, computing and sensing to real-time circuits & systems and analyze
their performance.

PSO3: Research and formulate suitable technologies for the implementation of

Electronics and Communication Engineering solutions, demonstrating
entrepreneurial and research aspects with a commitment to professional ethics
and a focus on societal well-being.
 Programme Educational Objectives (PEOs)

PEO 1: Demonstrate comprehensive knowledge of analytical foundations to

Electronics and Communication Engineering in terms of founding principles of
circuits, design, computing, signal processing and communication.

PEO 2: Demonstrate critical thinking and problem-solving abilities to handle the

real-world problems by applying theoretical foundations and practical skills in
different fields of Electronics and Communication Engineering.

PEO 3: Exhibit qualities of teamwork, appreciation of collaboration that entails

inter-disciplinary endeavors and the potential impact of technology on society.

PEO 4: Develop creativity, Research related skills, self-learning, entrepreneurial and

leadership skills in order to meet the ever-changing needs and challenges in the
profession.
 Class Timetable
Day / Time 8.00-8.50 09.00-9.50 10.00- 11.00-11.50 12.00-12.50 1.00-1.50 2.00-2.50 3.00-3.50 4.00-4.50
Am Am 10.50Am Am Pm Pm Pm Pm Pm

Monday EECE3051

Tues day EECE3051

Wednesday

Thursday EECE3051

Friday EECE3051P

Meeting Hours: Mon – Fri 4:00 pm – 5:00 pm Room # SB 337

 Syllabus L: 3 T: 0 P:1 S:0 J:0
C: 3

Course Educational Objectives:

• To introduce the design flow of integrated circuits using hardware description languages and
programmable logic devices.
• To explain the architecture and usage of different types of programmable logic devices including
PLAs, PLDs, CPLDs and FPGAs .
• To describe semiconductor technology evolution, the different steps of IC fabrication process and
appreciate the role of mask layout in the design process
• To provide an understanding of the constraints imposed by fabrication engineer and learn to prepare
mask layouts as per design rules
• To comprehend the design of combinational and sequential circuits from MOS schematic to layout.
UNIT 1 Modeling Digital Circuits with HDLs 10 hours

VLSI Design Methodologies: Computer Aided Design: Hardware description languages, Verilog
description of combinational circuits, Verilog modules, Verilog assignments, procedural assignments,
modeling flip-flops using always block, delays in Verilog, compilation, simulation, and synthesis of Verilog
code, Verilog data types and operators, simple synthesis examples, Verilog models for multiplexers,
modeling registers, counters and finite state machines using Verilog always statements, behavioral and
structural Verilog, testing a Verilog model
.
 Syllabus
UNIT 2 Programmable Logic Devices 6 hours
Programmable Logic Devices: Simple programmable logic devices (SPLDs), Complex programmable logic
devices (CPLDs), Field programmable gate arrays (FPGAs), implementing functions in FPGAs

UNIT 3 Full Custom IC Design 7 hours

IC Design Technology: Integrated Circuit (IC) era, Metal Oxide Semiconductor (MOS) and related VLSI
technology, basic MOS transistors, enhancement mode transistor action, NMOS fabrication, CMOS
fabrication, comparison of NMOS, CMOS, BICMOS, GaAs technologies. Basic Electrical Properties of
MOS Circuits: Drain current vs drain-source voltage relationships, MOS transistor threshold voltage, pass
transistor, NMOS inverter, CMOS inverter

UNIT 4 MOS Circuit Design Process 9 Hours

MOS Circuit Design Process: MOS Layers, stick diagrams, design rules and layout, 2µm micron based
design rules, layout diagrams, symbolic diagrams. CMOS Circuit and Layout Design using Static
Complementary CMOS Logic Style. Delay and Power Analysis of CMOS Logic Circuits

UNIT 5 Subsystem Design and Layout 8 hours

Subsystem Design and Layout: Some architectural issues, switch logic, gate (restoring) logic, examples of
structured design, parity generator, multiplexers, general logic function block. Design of Latches and
Flipflops using Static Complementary CMOS
 Syllabus
Course Outcomes:
1. Model combinational/sequential logic circuits and their testbenches at different levels of abstraction in
Verilog (L3)Identify different hybrid drivetrain topologies. (L3)
2. Describe and compare the architectures of different programmable logic devices (L2).
3. Explain the evolution of IC technology and its fabrication process (L1)
4. Derive the stick diagram and mask layout for a given MOS circuit (L5)
5. Build combination and sequential building blocks at the subsystem level using different MOS circuit
styles (L5)

TextBooks:
1. Charles H. Roth, Lizy Kurian John, ByeongKil Lee, Digital Systems Design using Verilog, 1/e, Cengage
Learning, 2016
2. Douglas A, Pucknell, Kamran Eshraghian, Essentials of VLSI Circuits and Systems, 1/e, Prentice Hall,
2012.
3. Weste, Harris, CMOS VLSI Design, 4/e, Pearson Education, 2014
 Syllabus

Reference Books :
1. Kang, Leblibici, CMOS Digital Integrated Circuits, 3/e, Tata McGraw Hill, 2001
2. Jan M. Rabaey, Digital Integrated Circuits, 2/e, Pearson Education, 2002
 Assessments
1. Mid Exams: 30% [ One Mid Exam ]
[Dates: 10 February 2025 to 14 February 2025] [ Unit 1-3]

2. Quizzes: 20% [5 Quizzes]

[5 Surprised Quizzes during the class hour after completion of each
Unit]

3. Assignments: 20% [ 2 Assignments: Course Projects]

[Dates: Assignment 1: 10 March 2025 ; Assignment 2: 1 April 2025]

4. Final Examination:30%
[Dates: 9 April 2025 - 28 April 2025]
 Integrated Circuits
Integrated Circuits(IC):

• An integrated circuit (IC), is a semiconductor wafer on which thousands

or millions of tiny resistor, capacitor, diodes and transistors are fabricated.

Advantages of IC:
• Extremely small in size
• Low power consumption
• Improved Speed
• Increased Reliability
• Lesser weight
 Types of Integration
Level of Number of Devices Examples
Integration
Small-scale less than 10 Logic gates(AND,OR,NAND)
integration (SSI)
Medium-scale 10 to 100 FF, Mux, DeMux etc
integration(MSI)
Large scale 100 to 10,000 PLD
integration(LSI)
Very large scale 10,000 to 100,000 CPLD
integration(VLSI)
Ultra large-scale 100,000 to 1,000,000 8 & 16 bit microprocessor
integration(ULSI)
Giga—Scale > 1,000,000 Pentium IV Processor
Integration(GSI)
 VLSI?
Very Large Scale Integration(VLSI):

• Very Large Scale Integration(VLSI) is the process of making Integrated Circuits

(ICs) by combining a number of components like resistors, transistors, and

capacitors on a single chip.

Application of VLSI:

• Consumer Electronics: Smart Phones, Tablets…

• Automotive Industry : Driver Assistance…..

• Telecommunication: 5G…

• Health Care: Wearable devices

Semiconductor Manufacturing process
 What is HDL?
➢ Hardware Description Language (HDL) is a programming language

that is used to describe the behavior and structure of digital circuits

➢ HDLs serve the purpose of simulating the circuit and verifying its response

before actual implementation

➢ HDL distinguishes itself by representing extensive parallel operations

➢ Designers can use HDLs to express their designs at different levels of

abstraction. This allows for optimization at various stages

HDL Design FLOW
Design entry: The design is converted to a machine
readable format. The design is described in a
formal hardware description language (HDL). The most
common HDLs are VHDL and Verilog.

Functional Simulation: This is an important step that

check HDL correctness by comparing output of the
HDL model and the behavioral

Synthesis: In this step RTL code is converted to

gate level netlist using synthesis tool. Netlist is a
description of the circuit in terms of gates and
connections between them.

Design Implementation: A synthesis tool generate

netlist is mapped onto internal structure

Device Configuration: Generate 0 and 1 logic and

upload in the Kid
 Popular HDL Types
Verilog VHDL

Verilog – Verification logic HDL VHDL-Very High-Speed Integrated

Circuit Hardware Description
Language
C like syntax Ada like syntax

Case sensitive Not case sensitive

Often Preferred for lower level It is relatively weaker in lower

abstraction (gate and register- level designs, but superior in
transfer level) higher system level design
It results in fast simulation It results in slower simulation
 Verilog
➢ Verilog is a Hardware Description Language (HDL).

➢ It is a language used for describing a digital system such as a

network switch, a microprocessor, a memory, or a flip-flop.

➢ It permits the designers to design the designs in either Bottom-up or

Top-down methodology

➢ In 2001, IEEE 1364 – 2001 was approved and this is the latest

Verilog Standard
 Design Methodology
Verilog can be designed based on
1. Based on Design Hierarchy
2. Based on Abstraction
1.Based on Design Hierarchy
a) Top down Methodology
Design from top block to leaf cell
 Design Methodology
Example: To design 4-Bit Ripple carry adder
 Design Methodology
b) Top down Methodology
Design from leaf cell to top block
 Design Methodology
2.Based on Abstraction
 Design Methodology
Based on Abstraction
 Behavioral or Algorithmic level
❑This is the highest level of abstraction provided by Verilog HDL.
❑A module can be implemented in terms of the desired design algorithm
without concern for the hardware details.
❑It specifies the circuit in terms of its expected behavior.

S[1] S[0] O

0 0 i[0]

0 1 i[1]

1 0 i[2]

1 1 i[3]
 Dataflow level
❑ It is the next higher level of abstraction.
❑ The designer should be aware of data flow of the design
❑This style is similar to logical equations
❑The specification is comprised of expressions made up of input
signals and assigned to outputs
0=S[1]’S[2]’i[0] + S[1]’S[2]i[1] + S[1]S[2]’i[2] + S[1]S[2]i[3]
 Gate level or Structural level
❑The module is implemented in terms of logic gates and
interconnections between these gates.
❑It resembles a schematic drawing with components connected with
signals.
❑Verilog has a predefined set of logic gates known as primitives
 Switch level
❑This is the lowest level of abstraction provided by Verilog.
❑A module can be implemented in terms of transistors, storage
nodes, and the interconnections between them
❑In Verilog HDL transistors are known as Switches that can either
conduct or open
Verilog Module

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 Verilog Module
✓A module is a basic building block that declares the input and output

signals and specifies the internal operation of the module

✓All the input and output signals are listed in the module statement

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Module Structure

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 Module declaration:
module module-name (module interface list); • Verilog program
[list-of-interface-ports] begins with a Keyword
– “module”
...
• Used to declare the
[port-declarations]
three ports
... 1. Input port-to entry
[functional-specification-of-module] the inputs
... 2. Output port-to entry
endmodule the outputs
3. Inout port-to entry
both inputs and
outputs
Example

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 Keywords and Identifiers
Keywords
✓Keywords are special identifiers reserved to define the language constructs. Keywords
are in lowercase
✓Keywords signifies an activity to be carried out or terminated
Example:

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Identifiers
✓Identifiers are names given to objects so that they can be referenced in the
design.
✓Identifiers are made up of alphanumeric characters, the underscore ( _ ), or the
dollar sign ( $ ).
✓Identifiers are case sensitive.
✓ Identifiers start with an alphabetic character or an underscore. They cannot
start with a digit or a $ sign
Example:

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Verilog Modelling

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 Gate level or Structural level Modeling
➢The module is implemented in terms of logic gates and interconnections
between these gates.
➢It resembles a schematic drawing with components connected with signals.
➢Verilog has a predefined set of logic gates known as primitives
 Gate level or Structural level Modeling
In gate level, the circuit is described in terms of gates (e.g., AND gate,
NAND gate).
There are two classes of gate primitives:
1. Single input gate primitives
2. Multiple input gate primitives

1. Single input gate primitives:

o Single input gate primitives have a single input and one or more
outputs.
o The gate primitive are not, buf, notif, and bufif also have a control signal
 Gate level or Structural level Modeling
2. Multiple input gate primitives:
Multiple input gate primitives include AND, OR, XOR, NAND, NOR, and XNOR.
They may have multiple inputs and a single output

Syntax:

1. AND Gate
and (output , input, input);
Example:
and (c, a, b);
2.OR Gate
or (output , input, input);
❖Example:
or (c, a, b);
 Do and Don’t do
❖Example:
and (c, a, b);

❖Example:
AND (c, a, b);

❖Example:
and (C, A, B);

❖ Keyword word / Syntax word like and, or, nand, nor, not, xor, xnor – all
should be in sentence case.
❖ No restrictions for I/O declarations.
 Dataflow level Modeling
✓ It is the next higher level of abstraction.
✓ The designer should be aware of data flow of the design
✓This style is similar to logical equations
✓The specification is comprised of expressions made up of input signals and assigned
to outputs
0=S[1]’S[2]’i[0] + S[1]’S[2]i[1] + S[1]S[2]’i[2] + S[1]S[2]i[3]
 Dataflow level Modeling
❑ Here all operation on signal and variables are represented by assignments
(defines the continuous functioning of the concerned block).
❑In dataflow modeling, most of the design is implemented using continuous
assignments, which are used to drive a value onto a net (nodes in a circuit).

Bit-wise operator
❖Syntax : AND Gate
assign output = input & input;
❖Example:
assign c = a & b;

❖Syntax : OR Gate
assign output = input | input;
❖Example:
assign c = a | b;
Programs

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 Gate Level Modeling-AND Gate

module and_gate (c, a, b);

input a, b;
output c;
and(c, a, b);
endmodule
 Gate Level Modeling-OR Gate

module or_gate (c, a, b);

input a, b;
output c;
or(c, a, b);
endmodule

Digital Design with Verilog EEC346 50

 Gate Modeling for E=AB+D

module two_gate (A,B,D,E);

input A,B,D;
output E;
wire C;
and (C, A, B);
or (E, C, D);
endmodule

Digital Design with Verilog EEC346 51

 Data Flow Modeling-AND Gate

module and_gate (c, a, b);

input a, b;
output c;
assign c= a&b;
endmodule

Digital Design with Verilog EEC346 52

 Data Flow Modeling-AND Gate

module or_gate (c, a, b);

input a, b;
output c;
assign c= a|b;
endmodule

Digital Design with Verilog EEC346 53

 Data Flow Modeling-E=AB+C

module two_gate (A,B,D,E);

input A,B,D;
output E;
wire C;
assign C= A&B;
assign E = C|D;
endmodule

Digital Design with Verilog EEC346 54

Thank you!

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