16Gb DDR5 SDRAM Die Rev A

Features

16Gb DDR5 SDRAM Addendum

MT60B4G4, MT60B2G8, MT60B1G16
Die Revision A
Features • Loopback mode
• Command-based non-target (NT) nominal, DQ/DQS
This document describes the product specifications that park, and dynamic WR on-die termination (ODT)
are unique to Micron 16Gb DDR5 Die Revision A device. • sPPR and hPPR capability
For general Micron DDR5 SDRAM specifications, see • Per-DRAM addressability
the Micron DDR5 SDRAM Core Product Data Sheet. • JEDEC JESD-79.5 compliant
Content in this 16Gb Die Revision A DDR5 SDRAM data
sheet addendum supersedes content defined in the core
data sheet.
Options1 Marking
• VDD = VDDQ = 1.1V (NOM)
• VPP= 1.8V (NOM) • Configuration
• On-die, internal, adjustable VREF generation for DQ, – 4 Gig x 4 4G4
CA, CS – 2 Gig x 8 2G8
• 1.1V pseudo open-drain I/O – 1 Gig x 16 1G16
• TC maximum up to 95°C • FBGA SDP Packages (Pb-free)
– 32ms, 8192-cycle refresh up to 85°C – x4, x8 82-ball (9mm x 11mm) HB
– 16ms, 8192-cycle refresh at >85°C to 95°C – x16 102-ball (9mm x 14mm) HC
• 32 internal banks (x4, x8): 8 groups of 4 banks each • Timing – cycle time
• 16 internal banks (x16): 4 groups of 4 banks each – 0.416ns @ CL = 40 -48B
• 16n-bit prefetch architecture • Operating temperature
• 1 cycle/2 cycle command structure – Commercial (0°C < TC < 95°C) None
• 2N mode – Industrial (–40°C < TC < 95°C) IT
• All bank and same bank refresh – Automotive (–40°C < TC < 105°C) AT
• Multi-purpose command (MPC) • Die Revision :A
• CS/CA training mode
• On-die ECC (bounded fault) Notes: 1. Not all options listed can be combined to define
• ECC transparency and error scrub an offered product. Use the part catalog search on
micron.com for available offerings.
• Decision feedback equalization (DFE)

Table 1: Key Timing Parameters

Speed Grade1 Speed Bin Data Rate (MT/s) Target CL-nRCD-nRP tAA (ns) tRCD (ns) tRP (ns)
-48B 4800B 4800 40-39-39 16.000 16.000 16.000

Notes: 1. Refer to the Speed Bin Tables for additional details.

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Products and specifications discussed herein are subject to change by Micron without notice.
 16Gb DDR5 SDRAM Die Rev A
Features

Table 2: 16Gb Addressing

Configuration 4Gb x4 2Gb x8 1Gb x16
Bank Number of bank groups/number of 8 / 4 / 32 8 / 4 / 32 4 / 4 / 16
address banks per bank group/number of banks
Bank group address BG0-BG2 BG0-BG2 BG0-BG1
Bank address in a bank group BA0-BA1 BA0-BA1 BA0-BA1
Row address R0-R15 R0-R15 R0-R15
Column address C0-C10 C0-C9 C0-C9
Page size 1KB 1KB 2KB
Chip IDs/maximum stack height CID0-3 / 16H CID0-3 / 16H CID0-3 / 16H

Figure 1: Order Part Number Example

Example Part Number: MT60B2G8HB-48B:A

- :

MT60B Configuration Package Speed Revision

{
Configuration Mark Revision
4 Gig x 4 4G4 :A
2 Gig x 8 2G8
Case Temperature
1 Gig x 16 1G16
Commercial None
Industrial temperature IT
Package Mark
82-ball 9.0mm x 11.0mm FBGA HB Speed Bin Cycle Time, CAS Latency
102-ball 9.0mm x 14.0mm FBGA HC -48B t CK = 0.416ns, CL = 40

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 16Gb DDR5 SDRAM Die Rev A
Important Notes and Warnings

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document
if you obtain the product described herein from any unauthorized distributor or other source not authorized by
Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of
non-automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and
conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to
indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component
could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical
Applications"). Customer must protect against death, personal injury, and severe property and environmental
damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron
component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron compo-
nent for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsid-
iaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs,
damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product
liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its
subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron
product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT
FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in
customer's applications and products to eliminate the risk that personal injury, death, or severe property or envi-
ronmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach
of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly autho-
rized representative.

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 16Gb DDR5 SDRAM Die Rev A
General Notes and Functional Block Diagrams

General Notes and Functional Block Diagrams

General Notes
• The functionality and the timing specifications discussed in this data sheet are for the DLL enable
mode of operation (normal operation), unless specifically stated otherwise.
• Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms "_t" and "_c" are used to represent the true and complement of a differential signal pair.
These terms replace the previously used notation of "#" and/or over-bar characters. For example,
differential data strobe pair DQS, DQS# is now referred to as DQS_t, DQS_c.
• The term "_n" is used to represent a signal that is active LOW and replaces the previously used "#"
and/or overbar characters. For example: CS# is now referred to as CS_n.
• The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as DQS_t, DQS_c
and CK_t, CK_c respectively, unless specifically stated otherwise.
• Complete functionality may be described throughout the entire document; any page or diagram may
have been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated here within is considered undefined, illegal, and not
supported, and can result in unknown operation.
• Addressing is denoted as BG[n] for bank group, BA[n] for bank address, and A[n] for row/col address.
• A NOP is considered a valid command for very specific states such as power-down exit, self-refresh
exit, and reset. The NOP must satisfy any associated command timings with respect to the preceding
valid command.
• Not all features described within this document may be available on the Rev. A (first) version.
• Not all specifications listed are finalized industry standards; best conservative estimates have been
provided when an industry standard has not been finalized.
• Although it is implied throughout the specification, the DRAM must be used after reaching a stable
power-on level, which is achieved by following the proper voltage ramp and power-up initialization
sequence procedures as outline in this specification.
• Not all features designated in the data sheet may be supported by earlier die revisions due to late
definition by JEDEC.

Definitions of the Device-Pin Signal Level

• HIGH: A device pin is driving the logic 1 state.
• LOW: A device pin is driving the logic 0 state.
• High-Z or (HI-Z/Hi-Z): A device pin is tri-state
• ODT: A device pin terminates with the ODT settings, which could be terminating or tri-state
depending on the mode register settings.

Definitions of the Bus Signal Level

• HIGH: One device on the bus is HIGH, and all other devices on the bus are either ODT or High-Z. The
voltage level on the bus is nominally VDDQ.
• LOW: One device on the bus is LOW, and all other devices on the bus are either ODT or High-Z. The
voltage level on the bus is nominally VOL(DC) if ODT was enabled, or VSSQ if High-Z.
• High-Z or (HI-Z/Hi-Z): All devices on the bus are High-Z. The voltage level on the bus is undefined
as the bus is floating.

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 16Gb DDR5 SDRAM Die Rev A
General Notes and Functional Block Diagrams

• ODT: At least one device on the bus is ODT, and all others are High-Z. The voltage level on the bus is
nominally VDDQ.
• The specification requires 8,192 refresh commands within 32ms between 0oC and 85oC. This allows
for a tREFI of 3.9µs in normal refresh mode. The specification also requires 8,192 refresh commands
within 16ms between 85oC and 95oC. This allows for a tREFI of 1.95µs in normal refresh mode.

Industrial Temperature
An industrial temperature (IT) device option requires that the case temperature not exceed below
–40°C or above 95°C. JEDEC specifications require the refresh rate to double when TC exceeds 85°C;
this also requires use of the high-temperature self-refresh option. Additionally, ODT resistance and the
input/output impedance must be derated when operating outside of the commercial temperature
range, when TC is between –40°C and 0°C.

Automotive Temperature
The automotive temperature (AT) device option requires that the case temperature not exceed below
–40°C or above 105°C. The specifications require the refresh rate to 2X when TC exceeds 85°C; 4X when
TC exceeds 95°C. Additionally, ODT resistance and the input/output impedance must be derated when
operating temperature Tc <0°C.

Figure 2: 4 Gig x4 Functional Block Diagram

CRC
control ALERT_n
VDDQ
Bank 3
CA_ODT
ODT CA/CS/CK ODT Bank 3
Bank 2
Bank 2
Bank 1 Bank 1
ZQ CAL Start Bank 0 Bank 0 ZQ
MPC ZQ CAL To ZQ Control
RESET_n
RESET_n ZQ CAL Latch BG7 Bank Group 7 control
VrefDQ Row-
Control
CK_t,CK_c Logic
BC8 Address 65,536 Memory
Latch Array
OTF ZQ
and (65,536 x 128 x 64)
TEN Decoder 16384 ODT
3 (CA[13:11]) 16384
Control VDDQ
VrefCS Sense amplifiers
RTTp RTTn RTTw

CS_n
CS_n 6
Command Decode
14 (CA[13:0])
Bank 3 Bank 3 1-
s
Bank 2 Bank 2 up 0 CA[3:2]
Bank 1 Bank 1
G
ro
r BG Burst Order (0 . . . 3)
Bank 0 nk fo
VDDQ / VSS Mode Registers Bank 0 d
Bank Group 0 Ba te DQ[3:0]
BG0 tra CK_t,CK_c
16 us
MRA[7:0]

Row- Ill DQ[3:0]

OP[7:0]

Address 65,536 Memory gic DQS_t / DQS_c

Latch Array Lo
16 Row- ue DLL DCA
and (65,536 x 128 x 64) tin Read
Address
Decoder 16384 on 4 Drivers VDDQ
RefSB MUX 16384 C
Refresh 16
RefAB Counter RTTp RTTn RTTw
Sense amplifiers READ
4 BG0 64 FIFO
and
MIR 3 BG 8192 64
Data
BC8
BG BG1-BG6 BC8
2 BA MUX
and
CAI BA I/O Gating (256
OTF CRC
4 BG7 Global Input DQS_t /
3 BG Control DM Mask Logic x64)
I/O Gating Buffers DQS_c
Logic VDDQ
Address ECC Logic CK_t,CK_c and
CA[13:0] Register
2 BA
Logic Phase
5
RTTp RTTn RTTw Control
MR53[4:0]
4 Loopback
32 128
64 DFE Control
x64 2
Output
Control
MR53[6:5]
7 Data
Column Column Interface DQ[3:0]
Address CA[10:4] Decoder DQS_t /
VrefCA 11 Counter/ DQS_c
Latch 4

CA[3:0]
VrefDQ LBDQ

LBDQS

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 16Gb DDR5 SDRAM Die Rev A
General Notes and Functional Block Diagrams

Figure 3: 2 Gig x8 Functional Block Diagram

CRC
control ALERT_n
VDDQ
Bank 3
CA_ODT
ODT CA/CS/CK ODT Bank 3
Bank 2
Bank 2
Bank 1 Bank 1
ZQ CAL Start Bank 0 Bank 0 ZQ
MPC ZQ CAL To ZQ Control Bank Group 7
RESET_n
RESET_n ZQ CAL Latch BG7 control
VrefDQ Row-
Control
CK_t,CK_c Logic
BC8 Address 65,536 Memory
Array
Latch
OTF (65,536 x 64 x 128) ZQ
and
TEN Decoder 16384 ODT
3 (CA[13:11]) 16384
Control VDDQ
VrefCS Sense amplifiers
RTTp RTTn RTTw

CS_n
CS_n 6
Command Decode
14 (CA[13:0])
Bank 3 Bank 3 1-
Bank 2 p s
Bank 2 ou 0 CA[3:2]
Bank 1 Bank 1 r G (0 . . . 7)
G rB Burst Order
VDDQ / VSS Mode Registers Bank 0 Bank 0 nk fo
Bank Group 0 Ba te
d
CK_t,CK_c DQ[7:0]
BG0
16 stra
MRA[7:0]

Row- llu DQ[7:0]

I
OP[7:0]

Address 65,536 Memory DQS_t / DQS_c

gic
Latch Array Lo DLL DCA
16 Row- ue
and (65,536 x 64 x 128) Read
Address tin
RefSB MUX
Decoder 16384
16384 on 8 Drivers VDDQ
C
Refresh 16
RefAB Counter Sense amplifiers RTTp RTTn RTTw
READ
4 BG0 128 FIFO
128 and
MIR 3 BG 8192
Data
BC8
BG BG1-BG6 BC8
2 BA MUX
and
CAI BA I/O Gating (256
OTF CRC
4 BG7 Global Input DQS_t /
3 BG Control DM Mask Logic x64)
I/O Gating Buffers DQS_c
Logic VDDQ
Address ECC Logic CK_t,CK_c and
CA[13:0] Register
2 BA
Logic Phase
5
RTTp RTTn RTTw Control
MR53[4:0]
8 Loopback
32 64
128 DFE Control
x128 2
Output
Control
MR53[6:5]
6 Data
Column Column Interface DQ[7:0]
Address CA[9:4] Decoder
11 DQS_t /
VrefCA Counter/ DQS_c
Latch 4

CA[3:0] VDDQ
VrefDQ LBDQ
RTTp RTTn RTTw

LBDQS

TDQS_c

DM_n /
TDQS_t

Figure 4: 1 Gig x16 Functional Block Diagram

CRC
control ALERT_n
VDDQ
Bank 3
CA_ODT
ODT CA/CS/CK ODT Bank 3
Bank 2
Bank 2
Bank 1 Bank 1
ZQ CAL Start Bank 0 Bank 0 ZQ
MPC ZQ CAL To ZQ Control Bank Group 3
RESET_n
RESET_n ZQ CAL Latch BG3 control
VrefDQ Row-
Control
CK_t,CK_c Logic
BC8 Address 65,536 Memory
Latch Array
OTF and (65,536 x 64 x 256) ZQ
TEN Decoder 16384 ODT
3 (CA[13:11]) 16384
Control VDDQ
VrefCS Sense amplifiers
RTTp RTTn RTTw
CS_n
CS_n 2
Command Decode
14 (CA[13:0])
Bank 3 Bank 3 1-
Bank 2 p s 0
Bank 2
Bank 1 rou BG
CA[3:2]
Bank 1 G r Burst Order (0 . . . 15)
Bank 0 nk fo
VDDQ / VSS Mode Registers Bank 0 d
Bank Group 0 Ba te
BG0 tra CK_t,CK_c DQ[15:0]
16 us
Ill
MRA[7:0]

Row-
OP[7:0]

DQ[15:0]
Address 65,536 Memory gic DQS_t / DQS_c
Latch Array Lo
16 Row- ue DLL DCA
and (65,536 x 64 x 256) tin Read
Address
Decoder on 16
RefSB MUX 16384
16384 C Drivers VDDQ
Refresh 16
RefAB Counter Sense amplifiers RTTp RTTn RTTw
READ
4 BG0 256 FIFO
256
MIR 2 BG 16384 and BC8
Data
BG BG1-BG2 BC8
2 BA MUX
and
CAI BA 4
I/O Gating (256
OTF CRC
Global DQS_t /
2 BG Control BG3 DM Mask Logic x64) Input
I/O Gating DQS_c
Logic Buffers VDDQ
Address ECC Logic
CK_t,CK_c and
CA[13:0] Register
2 BA
Logic Phase
5
RTTp RTTn RTTw Control
MR53[4:0]
64 16 Loopback
16 DFE
x256 256 Control
Output
2
Control
MR53[6:5]
6 Data
Column Column Interface DQ[15:0]
Address CA[9:4] Decoder
11 DQS_t /
VrefCA Counter/ DQS_c
Latch 4

CA[3:0] VDDQ
VrefDQ LBDQ
RTTp RTTn RTTw

LBDQS

DM_n /
DMU_n
DML_n

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 16Gb DDR5 SDRAM Die Rev A
DDR5 Function Matrix

DDR5 Function Matrix

DDR5 SDRAM has several features supported by configuration width, by density, by speed and by
device die Rev. The following table is the summary of the features supported by 16Gb Die Revision A
by configuration width. The functional matrix will be defined in each device-specific data sheet; there-
fore, device, speed and density options will vary by device data sheet.

Table 3: DDR5 Function Matrix - 16Gb Die Rev. A (by configuration width). V: Supported, Blank: Not
Supported
Function x4 x8 x16 MR Default State Notes
BC8 OTF V V V
BL32 (JEDEC optional)
BL32 OTF (JEDEC optional)
TDQS V
Data Mask (DM) V V
Data Output Disable V V V
Connectivity Test Mode (CT) V V V
CA/CS/CK ODT V V V
2N Mode V V V 5
Per DRAM Addressability (Enum) V V V
Mode Register Read (MRR) V V V 3
Mode Register Write (MRW) V V V
Multi-Purpose Command (MPC) V V V
ZQ calibration V V V
CA Vref Training V V V 1
CS Vref Training V V V 2
DQ Vref Training V V V
CS Training Mode (CSTM) V V V
CA Training Mode (CATM) V V V
Write Leveling Training V V V
WICA 1/2 step, a feature add for Internal WL V V V
(JEDEC Optional)
Read Training Pattern Mode (LFSR) V V V
Write Pattern Command V V V
DQS Interval Oscillator V V V
Duty Cycle Adjuster (DCA) V V V MR42:OP[1:0] = 01 10
Loopback Mode V V V
Decision Feedback Equalization (DFE) V V V
Maximum Power Saving Mode (MPSM) V V V 6
Package Output Driver Test mode (PODTM) V V V
PASR (JEDEC Optional) MR19:OP[7] = 0 11
WRITE CRC V V V

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 16Gb DDR5 SDRAM Die Rev A
DDR5 Function Matrix

Table 3: DDR5 Function Matrix - 16Gb Die Rev. A (by configuration width). V: Supported, Blank: Not
Supported (Continued)
Function x4 x8 x16 MR Default State Notes
READ CRC V V V 4
Programmable Preamble V V V
Programmable Postamble V V V
sPPR V V V
hPPR V V V
MBIST/mPPR (JEDEC optional) MR23:OP[4:3] = 00 12
PPR using DQ[3:0] only V V V
sPPR undo/lock (JEDEC optional) V V V MR23:OP[2] = 1 13
On-Die-ECC V V V
ECC Transparency and Error Scrub V V V
H-Matrix Revision supporting bounded fault V V V
self-aliasing
Same Bank Refresh V V V 7
Same Bank Precharge V V V
MR58:OP[0] = 0 9
MR58:OP[7:5] = 110
Refresh Management (RFM) V V V
MR58:OP[4:1] = 1010 14
MR59:OP[7:6] = 00
Adaptive RFM (JEDEC Optional)
Directed RFM (JEDEC Optional)
Fine Granularity Refresh (FGR) V V V
Refresh Interval Rate (RIR) (JEDEC Optional) MR4:OP[3] = 0 15
Wide Temperature Range (JEDEC Optional) MR4:OP[5] = 0 16
Test Mode MR (MR9) 8
ECS Writeback Suppression (JEDEC Optional) V V V
x4 RMW Suppression (JEDEC Optional) V

Notes: 1. CA Vref Training was added to support internally generated CA Vref.

2. CS Vref Training was added to support internally generated CS Vref.
3. Mode Register Read (MRR) is similar to DDR4’s MPR.
4. Read CRC as well as Write CRC are supported on DDR5.
5. 2N Mode replaced what was called Gear Down Mode on DDR4.
6. MPSM has three states defined: idle, power down and deep power down.
7. Same Bank Refresh requires FGR be enabled.
8. Test Mode (TM) is a vendor-specific mode register; not used by Micron.
9. RFM not required.
10. Device supports DCA for single/two-phase internal clock(s).
11. PASR not supported.
12. MBIST/mPPR not supported.
13. sPPR lock/undo supported.
14. RAAMMT, RAAIMT, and RAA counter decrement are only applicable if the RFM requirement bit is set to 1
(MR58:OP[0]=1).

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 16Gb DDR5 SDRAM Die Rev A
DDR5 Function Matrix

15. RIR indicator not implemented.

16. Wide temperature range not supported.

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 16Gb DDR5 SDRAM Die Rev A
DDR5 Package Pinout and Assignments

DDR5 Package Pinout and Assignments

Rows
The x4/x8 device has 13 electrical rows of balls. The x16 device has 17 electrical rows of balls. Electrical
is defined as rows that contain signal ball or power/ground balls. Additional rows of inactive balls may
be available for mechanical support.

Ball Pitch
The device uses a ball pitch of 0.8mm x 0.8mm.

Columns
The number of depopulated columns is 3.
The device has six electrical columns of balls in two sets of three columns. Between the electrical
columns are three columns where no balls are populated. Electrical is defined as columns that contain
signal ball or power/ground balls. Additional columns of inactive balls may be available for mechanical
support.

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 16Gb DDR5 SDRAM Die Rev A
DDR5 Package Pinout and Assignments

Figure 5: x4/x8 Ballout Using MO-210-AN – 82-Ball

1 2 3 4 5 6 7 8 9 10 11
A A
DNU LBDQ VSS VPP ZQ VSS LBDQS DNU
B B
VDD VDDQ DQ2 DQ3 VDDQ VDD
C C
VSS DQ0 DQS_t NF, DQ1 VSS
NF/DM_n/TDQS_t
D D
VDDQ VSS DQS_c NF, VSS VDDQ
NF/TDQS_c
E E
VDD NF,DQ4 NF,DQ6 NF,DQ7 NF,DQ5 VDD

F F
VSS VDDQ VSS VSS VDDQ VSS

G G
CA_ODT MIR VDD CK_t VDDQ TEN

H H
ALERT_n VSS CS_n CK_c VSS VDD

J J
VDDQ CA4 CA0 CA1 CA5 VDDQ

K K
VDD CA6 CA2 CA3 CA7 VDD

L L
VDDQ VSS CA8 CA9 VSS VDDQ

M M
CAI CA10 CA12 CA13 CA11 RESET_n

N N
DNU VDD VSS VDD VPP VSS VDD DNU

Notes: 1. Additional columns and rows of inactive balls in MO-210-AN terminal pattern (x4/x8) with support balls are for
mechanical support only and should not be tied electrically high or low.
2. Some of the additional support balls can be selectively populated at the suppliers' discretion.
3. DQ4-DQ7 higher-order DQ pins are connected but not used in the x4 configuration.
4. DM, TDQS_t and TDQS_c are not valid for the x4 configuration.
5. A comma "," separates the configuration. A slash "/" defines a mode register-selectable function,
command/address function, density or package dependence.

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11 Micron Technology, Inc. reserves the right to change products or specifications without notice.
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 16Gb DDR5 SDRAM Die Rev A
DDR5 Package Pinout and Assignments

Figure 6: x16 Ballout Using MO-210-AT –102 Ball

1 2 3 4 5 6 7 8 9
A A
LBDQ VSS VPP ZQ VSS LBDQS
B B
VDD VDDQ DQU2 DQU3 VDDQ VDD

C C
VSS DQU0 DQSU_t DMU_n DQU1 VSS

D D
VDDQ VSS DQSU_c RFU VSS VDDQ

E E
VDD DQU4 DQU6 DQU7 DQU5 VDD

F F
VDD VDDQ DQL2 DQL3 VDDQ VDD

G G
VSS DQL0 DQSL_t DML_n DQL1 VSS

H H
VDDQ VSS DQSL_c RFU VSS VDDQ

J J
VDD DQL4 DQL6 DQL7 DQL5 VDD

K K
VSS VDDQ VSS VSS VDDQ VSS

L L
CA_ODT MIR VDD CK_t VDDQ TEN

M M
ALERT_n VSS CS_n CK_c VSS VDD

N N
VDDQ CA4 CA0 CA1 CA5 VDDQ

P P
VDD CA6 CA2 CA3 CA7 VDD

R R
VDDQ VSS CA8 CA9 VSS VDDQ

T T
CAI CA10 CA12 CA13 CA11 RESET_n

U U
VDD VSS VDD VPP VSS VDD

Notes: 1. Additional columns and rows of inactive balls in MO-210-AU terminal pattern (x16) with support balls are for
mechanical support only and should not be tied electrically high or low.
2. Some of the additional support balls can be selectively populated at the suppliers' discretion.

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12 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 Package Pinout and Assignments

Table 4: Pinout Description

Symbol Type Function
CK_t, CK_c Input Clock:CK_t and CK_c are differential clock inputs. All command/address and
control input signals are sampled on the crossing of the positive edge of CK_t
and negative edge of CK_c.
CS_n Input Chip Select:All commands are masked when CS_n is registered HIGH. CS_n pro-
vides for external rank selection on systems with multiple ranks. CS_n is consid-
ered part of the command code and is used to enter and exit the parts from
power down mode and self refresh mode. While not in self refresh mode, the
CS_n input buffer operates with the same ODT and VREF parameters as config-
ured by the CA_ODT strap setting or mode register. When in self refresh mode,
the CS_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of
VDDQ.
DM_n, DMU_n, Input Input Data Mask: DM_n is an input mask signal for write data. Input data is
DML_n masked when DM_n is sampled LOW coincident with that input data during a
write access. DM_n is sampled on both edges of DQS. DM_n is not supported on
x4 devices. For x8 devices, the function of DM_n is enabled by the mode register.
For x16 devices, the function of DMU_n/DML_n is enabled by the mode register.
CA[13:0] Input Command/Address Inputs:Command/Address (CA) signals provide the com-
mand and address inputs according to the Command Truth Table. Because some
commands are multicycle, the pins may not be interchanged between devices
on the same bus.
RESET_n Input Active Low Asynchronous Reset:Reset is active when RESET_n is LOW, and
inactive when RESET_n is HIGH. RESET_n must be HIGH during normal opera-
tion. RESET_n is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and
20% of VDDQ.
DQ Input/Output Data Input/Output:Bidirectional data bus. If CRC is enabled via the mode regis-
ter, CRC code is added at the end of a data burst.
DQS_t, DQS_c, Input/Output Data Strobe:Output with read data, input with write data, edge-aligned with
DQSU_t, DQSU_c, read data, centered in write data. For x16 devices, DQSL corresponds to the data
DQSL_t, DQSL_c on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data
strobes DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c,
DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the
system during reads and writes. The device supports differential data strobe
only, not single-ended.
TDQS_t, TDQS_c Output Termination Data Strobe:Applicable to x8 devices only. When enabled via the
mode register, the device enables the same termination resistance function on
TDQS_t/TDQS_c that is applied to DQS_t/DQS_c. When disabled via the mode
register, DM/TDQS provides the data mask function depending on the MR set-
ting; TDQS_c is not used. x4/x16 devices must disable the TDQS function via the
mode register.
ALERT_n Input/Output Alert:If there is an error in CRC, ALERT_n drives LOW for the period time inter-
val and returns HIGH. During the connectivity test mode, this pin functions as an
input. Usage of this signal is system-dependent. In cases where this pin is not
connected, ALERT_n must be bonded to VDDQ on the system board.
TEN Input Connectivity Test Mode Enable:A HIGH on this pin enables CONNECTIVITY
TEST MODE operation along with other pins. It is a CMOS rail-to-rail signal with
AC HIGH and LOW at 80% and 20% of VDDQ. Usage of this signal is sys-
tem-dependent. This pin is pulled LOW internally with a weak pulldown resistor
to VSS .

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13 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 Package Pinout and Assignments

Table 4: Pinout Description (Continued)

Symbol Type Function
MIR Input Mirror:Used to inform the system that this device is being run in mirrored mode
instead of standard mode. With the MIR pin connected (strapped) to VDDQ, the
device internally swaps even-numbered CA with the next higher odd-number
CA. The MIR pin must be tied to VSS if no CA mirror is required. Mirror pair
examples: CA2 with CA3 (not CA1) CA4 with CA5 (not CA3). Note: the CA[13]
function is only relevant for certain densities (including stacking). In the case
that CA[13] is not used, its ball location, considering whether MIR is used or not,
should be connected (strapped) to VDDQ. No active signaling requirements
required.
CAI Input Command and Address Inversion:With this pin connected (strapped) to
VDDQ, the device internally inverts the logic level present on all CA signals. The
CAI pin must be connected to VSS if no CA inversion is required. No active signal-
ing requirements required.
CA_ODT Input ODT for Command and Address:Apply Group A settings if the pin is con-
nected (strapped) to VSS; apply Group B settings if the pin is connected
(strapped) to VDDQ. See the mode register defaults table for details. No active
signaling requirements required.
LBDQ Output Loopback Data Output:The output of this device on the Loopback Output
Select defined in MR53:OP[4:0]. When loopback is enabled, it is in driver mode
using the default RON described in the Loopback Function section. When loop-
back is disabled, the pin is either terminated or High-Z based on MR36:OP[2:0].
LBDQS Output Loopback Data Strobe Output:A single-ended strobe with the rising edged
aligned with loopback data edge, falling edge aligned with data center. When
loopback is enabled, it is in driver mode using the default RON described in the
Loopback function section. When loopback is disabled, the pin is either termi-
nated or High-Z based on MR36:OP[2:0].
RFU Input/Output Reserved for future use.
DNU Do not use.
NF No function: Internal connection is present but has no function.
VDDQ Supply DQ power supply; 1.1V nominal.
VDD Supply Power supply; 1.1V nominal.
VSS Supply Ground
VPP Supply Activating power supply; 1.8V nominal.
ZQ Reference Reference pin for ZQ calibration. This ball is tied to an external 240 ohm resistor
(RZQ), which is tied to VSS.

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14 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
Package Dimensions

Package Dimensions
Figure 7: 82-Ball VFBGA – MO-210-AN (x4/x8)

0.155

Seating plane

A 0.12 A
1.8 CTR
Nonconductive
overmold

82X Ø0.473 ±0.05

Dimensions apply
to solder balls post-
Ball A1 ID Ball A1 ID
reflow on Ø0.42 SMD
ball pads.
11 10 9 8 4 3 2 1

A
B
C
D
11 ±0.1
E
9.6 CTR F
G
H
J
K
L
M
0.8 TYP
N

0.8 TYP 0.9 ±0.1

8 CTR 0.346 ±0.05

9 ±0.1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

CCM005-0005-1684161373-30
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15 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
Package Dimensions

Figure 8: 102-Ball VFBGA – MO-210-AT (x16)

0.155

Seating plane

1.8 CTR
A 0.12 A
nonconductive
overmold

102X Ø0.473 ±0.05

Dimensions apply to Ball A1 ID Ball A1 ID
solder balls post-reflow
on Ø0.42 SMD ball pads.
9 8 7 3 2 1
A
B
C
D
E
F
G
14 ±0.1
H
12.8 CTR J
K
L
M
N
P
R
T
0.8 TYP U

0.8 TYP 0.9 ±0.1

6.4 CTR 0.346 ±0.05

9 ±0.1

Notes: 1. All dimensions are in millimeters.

2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu).

Table 5: Package Thermal Resistance Characteristics

Die Revision Package Parameter Value Unit Symbol
Rev A 82-ball “HB” Junction-to-case (TOP) 2.6 °C/W ΘJC
Junction-to-board 12.8 °C/W ΘJB
102-ball “HC” Junction-to-case (TOP) 2.6 °C/W ΘJC
Junction-to-board 12.8 °C/W ΘJB

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16 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 IDD,IPP,IDDQ Current Limits

DDR5 IDD,IPP,IDDQ Current Limits

DDR5 SDRAM current limits are measured and categorized based on the definitions found in the
DDR5 Product Core data sheet. Refer to the IDD and IDDQ specification parameters and test condi-
tions for details related to each current limit. Notes 1 and 2 apply to entire table

Table 6: DDR5 IDD, IPP, IDDQ Current Limits – 16Gb Die Revision A
Parameter Width DDR5-4800 Unit Notes
x4
103
IDD0 x8 mA
x16 122
x4
8
IPP0 x8 mA
x16 10
x4
IDDQ0 x8 31 mA
x16
x4
142
IDD0F x8 mA
x16 164
x4
10
IPP0F x8 mA
x16 13
x4
IDDQ0F x8 33 mA
x16
x4
IDD2N x8 92 mA
x16
x4
IPP2N x8 6 mA
x16
x4
IDDQ2N x8 33 mA
x16
x4
IDD2NT x8 149 mA
x16

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17 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 IDD,IPP,IDDQ Current Limits

Table 6: DDR5 IDD, IPP, IDDQ Current Limits – 16Gb Die Revision A
Parameter Width DDR5-4800 Unit Notes
x4
IPP2NT x8 6 mA
x16
x4
IDDQ2NT x8 32 mA
x16
x4
IDD2P x8 88 mA
x16
x4
IPP2P x8 6 mA
x16
x4
IDDQ2P x8 24 mA
x16
x4
IDD3N x8 142 mA
x16
x4
IPP3N x8 7 mA
x16
x4
IDDQ3N x8 31 mA
x16
x4
IDD3P x8 140 mA
x16
x4
IPP3P x8 7 mA
x16
x4
IDDQ3P x8 24 mA
x16
x4 318
IDD4R x8 377 mA
x16 530

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18 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 IDD,IPP,IDDQ Current Limits

Table 6: DDR5 IDD, IPP, IDDQ Current Limits – 16Gb Die Revision A
Parameter Width DDR5-4800 Unit Notes
x4
IPP4R x8 9 mA
x16
x4 43
IDDQ4R x8 57 mA
x16 92
x4 328
IDD4RC x8 389 mA
x16 546
x4
IPP4RC x8 9 mA
x16
x4 44
IDDQ4RC x8 57 mA
x16 93
x4 345
IDD4W x8 349 mA
x16 479
x4 36
IPP4W x8 37 mA
x16 64
x4 116
IDDQ4W x8 198 mA
x16 348
x4 311
IDD4WC x8 316 mA
x16 421
x4 35
IPP4WC x8 37 mA
x16 64
x4 116
IDDQ4WC x8 194 mA
x16 344
x4
IDD5B x8 277 mA
x16

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19 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 IDD,IPP,IDDQ Current Limits

Table 6: DDR5 IDD, IPP, IDDQ Current Limits – 16Gb Die Revision A
Parameter Width DDR5-4800 Unit Notes
x4
IPP5B x8 28 mA
x16
x4
IDDQ5B x8 32 mA
x16
x4
IDD5C x8 135 mA
x16
x4
IPP5C x8 12 mA
x16
x4
IDDQ5C x8 32 mA
x16
x4
IDD5F x8 262 mA
x16
x4
IPP5F x8 26 mA
x16
x4
IDDQ5F x8 32 mA
x16
x4
IDD6N(0-85C) x8 102 mA 3,4
x16
x4
IPP6N (0-85C) x8 15 mA 3,4
x16
x4
IDDQ6N (0-85C) x8 16 mA 3,4
x16
x4
IDD6E (85-95C) x8 200 mA 4,5
x16

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20 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
DDR5 IDD,IPP,IDDQ Current Limits

Table 6: DDR5 IDD, IPP, IDDQ Current Limits – 16Gb Die Revision A
Parameter Width DDR5-4800 Unit Notes
x4
IPP6E (85-95C) x8 25 mA 4,5
x16
x4
IDDQ6E (85-95C) x8 19 mA 4,5
x16
x4 448
IDD7 x8 502 mA
x16 775
x4 23
IPP7 x8 23 mA
x16 35
x4 50
IDDQ7 x8 64 mA
x16 100
x4
IDD8 x8 80 mA
x16
x4
IPP8 x8 6 mA
x16
x4
IDDQ8 x8 19 mA
x16

Notes: 1. Some IDD currents are higher for x16 organization due to larger page-size architecture.
2. Maximum values for IDD currents considering worst-case conditions of process, temperature, and voltage.
3. Applicable for MR4:OP[2:0]=001b, 010b.
4. Supplier data sheets include a maximum value for IDD6.
5. Applicable for MR4:OP[2:0]=011b, 100b, 101b.

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21 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.
 16Gb DDR5 SDRAM Die Rev A
Revision History

Revision History
Rev. D – 02/2023
• Functional block diagrams updated

Rev. C – 01/2023
• Removed 52B, 56B speed bins (not supported in 16Gb Die Revision A).
• Added functional block diagrams.
• Moved thermal characteristics table under package dimension topic.

Rev. B – 10/2021
• Removed Micron Confidential marking.
• Updated DDR5 Function Matrix table to add default mode register states.

Rev. A – 09/2021
• Initial release

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006

208-368-4000, micron.com/support
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes
occur.
CCM005-0005-1684161373-30
16gb_ddr5_sdram_dierevA.pdf - Rev. D 02/2023 EN
22 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2021 Micron Technology, Inc. All rights reserved.