College Name: NMAM Institute of Technology, Nitte

Examination: Semester End Examination

Program: B.Tech. Semester: 3 QP Set No.: 1
Course Title: Computer Organization and Architecture

PART - A: MULTIPLE CHOICE QUESTIONS 20 Marks

1. The method which offers higher speeds of I/O transfers is ___________
A) Interrupts B) Memory mapping
C) Program-controlled I/O D) DMA
2. In memory-mapped I/O ____________
A) The I/O devices have a separate B) The I/O devices and the memory share the
address space same address space
C) A part of the memory is specifically set D) The memory and I/O devices have an
aside for the I/O operation associated address space
3. The ________ circuit is basically used to connect devices to the bus.
A) Router B) Processor
C) Bridge D) Interface
4. Which of the following is not true about DMA?
DMA is an approach of performing data The DMA controller acts as a processor for
transfers in bulk between memory and the DMA transfers and overlooks the entire
external device without the intervention of process.
the processor.
The DMA controller has 3 registers. DMA is a Disk Memory Accumulator
5. The method of synchronizing the processor with the I/O device in which the device sends a
signal when it is ready is?
A) Exceptions B) Signal Handling
C) DMA D) Interrupts
6. Micro program is
A) The name of a source program in B) set of microinstructions that defines the
micro computer individual operations in response to a machine-
language instruction
C) a primitive form of macros used in D) a very small segment of machine code
assembly language programming
7. To overcome the lag in the operating speeds of the I/O device and the processor we use
A) Buffer Spaces B) Status Flags
C) Interrupt Signals D) Exceptions
8. The method of synchronising the processor with the I/O device in which the device sends a
signal when it is ready is?
A) Exceptions B) Signal Handling
C) Interrupts D) DMA
9. The process wherein the processor constantly checks the status flags is called as
___________
A) Polling B) Inspection
C) Reviewing D) Echoing
10. The key feature of the PCI BUS is _________
A) Low cost connectivity B) Plug and Play capability
C) Expansion of Bandwidth D) None of the mentioned
11. The device which is allowed to initiate data transfers on the BUS at any time is called _____
A) ) BUS master B) Processor
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 C) BUS arbitrator D) Controller
12. ______ BUS arbitration approach uses the involvement of the processor.
A) Centralised arbitration B) Distributed arbitration
C) Random arbitration D) All of the mentioned
13. The DMA differs from the interrupt mode by __________
A) The involvement of the processor for B) ) The method of accessing the I/O devices
the operation
C) The amount of data transfer possible D) High speed transfer
14. The return address from the interrupt-service routine is stored on the ___________
A) System heap B) Processor register
C) Processor stack D) Memory
15. The classification of BUSes into synchronous and asynchronous is based on __________
A) The devices connected to them B) The type of data transfer
C) The Timing of data transfers D) None of the mentioned
16. The delays caused in the switching of the timing signals is due to __________
A) Memory access time B) WMFC
C) Propagation delay D) Processor delay
17. The device which starts data transfer is called __________
A) Master B) Transactor
C) Distributor D) Initiator
18. ________ are the different type/s of generating control signals.
A) Hardwired B) Micro-instruction
C) Micro-programmed D) Both Micro-programmed and Hardwired
19. The PCI follows a set of standards primarily used in _____ PC’s.
A) Intel B) Motorola
C) IBM D) SUN
20. To resolve the clash over the access of the system BUS we use ______
A) Multiple BUS B) BUS arbitrator
C) Priority access D) DMA
21. A complete transfer operation over the BUS, involving the address and a burst of data is called
_____
A) Transaction B) Transfer
C) Move D) Procedure
22. In DMA transfers, the required signals and addresses are given by the __________
A) ) Processor B) Device drivers
C) DMA controllers D) The program itself
23. The signal sent to the device from the processor to the device after receiving an
interrupt is ___________
A) Interrupt-acknowledge B) Return signal
C) Service signal D) Permission signal
24. Hard wired control is faster than micro programmed control
A) true B) false
C) same speed D) Can’t decide
25. MFC is used to inform completion of memory operation from -------------Device
A) Addressed b) Control
C) ALU D) Memory
26. -------- is way of generating control signals by flip flops, gates and other digital circuits
A) Micro programmed control B) Hard wired control
C) both D) Bus
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27. How many types of memory transfer operation:
A) 1 B) 2
C) 3 D) 4
28. The instruction -> Add LOCA, R0 does _______
A) Adds the value of LOCA to R0 and stores B) Adds the value of R0 to the address of LOCA
in the temp register
C)Adds the values of both LOCA and R0 and D)Adds the value of LOCA with a value in
stores it in R0 accumulator and stores it in R0
29 ISR stand for:
A) Interrupt save routine B) Interrupt service routine
C) Input stages routine D) Indirect Service Routine
30 Which is an important data transfer technique :
A) CPU B) DMA
C) CAD D) CAM
31 ______operations are the results of I/O operations that are written in the computer
program:
A) Programmed I/O B) DMA
C) Handshaking D) Strobe
32 In devices 2 status reporting signals are:
A) BUSY B) READY
C) Both a & b D) BBY
33 The time required to complete one instruction is called:
A) Fetch time B) Execution time
C) Control time D) Access Time
34 _________with which computers perform is way beyond human capabilities:
A) Speed B) Accuracy
C) Accuracy D) Versatility
35 Each interaction b/w CPU and I/O module involves:
A) Bus arbitration B) Bus revolution
C) Data bus D) Control signals
36 Which exception is also called software interrupt:
A) Interrupt B) System calls
C) Traps D) Device Interrupt
37 The processing speed of a computer depends on the __________of the system:
A) Clock speed B) Motorola
C) Cyrix D) Memory
38 Register are assumed to use positive-edge triggered _____:
A) Flip-flop B) Logics
C) Circuit D) Operation
39 In every transfer, selection of register by bus is decided by:
A) Control signal B) No signal
C) All signal D) Bus Signal
40 The configuration, in which no difference between memory and I/O devices is seen by the
CPU, is referred to as __________
A) memory unit B) memory mapped I/O
C) memory address register D) Control unit
41 Condition codes are also referred to as ___.
A) Index register B) Stack pointer
C) Segment pointer D) Flag
(Ensure no repetition in the questions and options.)
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Answer Key:
(Write correct options in capital letters viz. A, B, C or D)

Q. No. Correct Q. No. Correct Q. No. Correct

Option Option Option
1. D 11. A 21. A
2. B 12. A 22. C
3. D 13. D 23. A
4. D 14. C 24. A
5. D 15. C 25. D
6. B 16. C 26. A
7. B 17. D 27. B
8. C 18. D 28. C
9. A 19. C 29. B
10. B 20. B 30. B

Q. No. Correct Q. No. Correct

Option Option
31. A 41. D

32. C 42.

33. B 43.

34. A 44.

35. A 45.

36. B 46.

37. A 47.

38. A 48.

39. A 49.

40. B 50.