Applied Electronics Worksheet II

1. Find VCE.VCB, VBE, IB, IC and IE in the figure and also Determine whether or not the transistor
are saturated

2. The transistor in the figure has βDC of 50 determine the value of RB required to ensure
saturation where VIN IS 5V.What must VIN be to cut off the transistor?Assume VCE(satu) = 0V.

3. Drive the formula for 𝛼𝐷𝐶 in terms of 𝛽𝐷𝐶 .

4. A certain 2N3904 DC bias circuit with the following value is in saturation. IB =500μA,
VCC=10V and RC=180Ὠ and ℎ𝑓𝑓 =150. If you increase VCC to 15V, does the transistor come to
out of saturation? If so, what are collector-to-emitter voltage and the collector current?
5. Design a DC bias circuit for an amplifier in which the voltage gain is to be minimum of 50 and
the output signal voltage is to be ‘’riding’ ’on a dc level of 5V. The maximum input signal
voltage at the base is 10mv rms. VCC=12V and VBB=4V.Assume re=8Ὠ.
6. Design a biased transistor circuit using VCC = VBB = 10V for Q-point of IC = 5mA and VCE =
4V Assume βDC =100.the design involves finding RB, RC and the minimum power rating of the
transistor. (The actual power rating should be greater).

7. Determine whether the transistor in figure is biased in cutoff, saturation and linear region. keep
in mind that IC= βDC IB is valid only in linear region.

1|Page
8. Given the information appearing in Fig.(A) determine where IB=40μA and VC=6V
(a) IC. (c) RB.
(b) RC. (d) VCE.

(A) (B)
9. For the emitter-stabilized bias circuit of Fig.(B) determine:
(a) IB, IC
(c) VCE, VC, VB and, VE

10. Given the information provided in Fig (A). determine: where VCE=7.3V, IB=20μA and
VE=2.1V. (A) β. (B) VCC & RB.

(A) (B) (C)

11. Given the information provided in Fig. (B) Determine: when VCC=12V.
(a) IC. (c) VB.
2|Page
(b) VE. (d) R1
12. (A) Determine IC, VCE, and IB for the network of Fig (C) using the approximate approach
even though the condition established is not satisfied.
(B) Determine IC, VCE, and IB using the exact approach.
(C) Compare solutions and comment on whether the difference is sufficiently large to require
standard equation when determining which approach to employ.
(D) Change β to 120 (50% increase), and determine the new values of IC and VCE for the
network.
13. For the collector feedback network of Fig.(A) determine:
(a) IC. (c) VE.
(b) VC. (d) VCE

14. Given VC = 8 V for the network of Fig. (B) Determine:

(a) IB. (c) β.
(b) IC (d) VCE

(A) (B)

15. For the E-MOSFET network given in the following figure, which has a minimum value of
𝐼𝐷(𝑜𝑛) = 200𝑚𝐴 at 𝑉𝐺𝑆 = 4𝑉 and 𝑉𝐺𝑆(𝑡ℎ) = 2𝑉. Determine: -

A) 𝑉𝐺𝑆 , Input voltage

B) The output voltage (𝑉𝐷𝑆 )
C) The gate voltage
D) Drain voltage

16. For the network given below, determine: -

A) The overall voltage & current gain

3|Page
 B) Calculate input & output impedance
C) Determine lower cutoff frequency due to𝐶1 , 𝐶2 𝑎𝑛𝑑 𝐶3
D) The overall lower cutoff frequency
E) Sketch the low-frequency response of the amplifier.

F) Determine 𝑓𝐻𝑖 𝑎𝑛𝑑 𝑓𝐻𝑜

G) Sketch the frequency responses of the amplifier for the high-frequency region.
H) Plot the frequency response of amplifiers and find Bandwidth
17) For the JFET amplifier circuit of Fig. below, determine
A) The current and voltage gain
B) Input and output impedance
C) lower- and higher-cutoff frequencies and sketch the frequency response.

4|Page
18. For the network given below, determine:
A) Voltage Current gain
B) Input and output impedance
C) Lower cut-& higher cut-off frequency for single stages
D) Overall lower and higher cut-off frequency
E) Plot the frequency response of multistage amplifier and find Bandwidth

19. For the network of multistage amplifier given bellow, Determine:

A) Voltage and Current gain
B) Input and output impedance
C) Overall lower- and higher- cut-off frequencies
D) Plot the overall frequency response of multistage amplifier and find bandwidth

5|Page
20. Design a voltage-divider bias network using a depletion-type MOSFET with I_DSS=10mA
and V_P=-4V to have a Q-point at I_D=2.5 mA using a supply of 24 V. In addition, set V_G=4V
and use R_D=2.5R_S with R_1=22MΩ. Use standard values.

Assignment: - Q4, Q6, Q9, Q12, Q13, Q15, Q16, Q17, Q18, Q19 & Q20

N.B: -Show all necessary steps clearly, unless your work will be invalid

6|Page
 Applied Electronics I Worksheet I

1. Determine VO and ID for the series circuit of figure below.

2. Determine ID , VD and VO mine for the circuit of figure below.

3. Determine VO , I1 , ID1 , and ID2 for the parallel diode configuration of Figure below.

4. Determine the current I for the network of Figure below

5. Determine Vo and ID for the networks of Figure below

Page | 1
EME applied electronics – I worksheet -I
 (A) (B)
6. Determine the voltage across each diode in the figure below, assuming the practical model.

(A) (B)
7. Determine VO1, VO2, and I for the network of Figure below.

8. (A) Given Pmax = 14 mW for each diode of Figure below, determine the maximum current
rating of each diode (using the approximate equivalent model)
(B) Determine Imax for Vimax = 160 V.
(C) Determine the current through each diode at Vimax using the results of part (b).
(D) If only one diode were present, determine the diode current and compare it to the
maximum rating.

9. Determine the peak and average power delivered to RL in figure below.

Page | 2
EME applied electronics – I worksheet -I
 10. Fined the average value of each voltage in figure below.

(A) (B)
11. Consider the circuit in figure below.
(A) What types of circuit is this? And What is the total peak secondary voltage?
(B) Find the peak voltage across each half of secondary.
(C) Sketch the voltage waveform across load resistance
(D) What is the peak current through each diode?
(E) What is the PIV for each diode?

12. Show how to connect the diodes in a center tapped rectifier in order to produce a negative
going full-wave voltage across the load resistor.
13. What PIV rating is required for the diodes in bridge rectifier that produces an average output
voltage of 50V?
14. A certain full- wave rectifier has a peak output voltage of 30V. a 50μF capacitor input filter is
connected to the rectifier. Calculate the peak- to- peak ripple and the dc output voltage
developed across a 600Ω load resistance.
15. What value of filter capacitor is required to produce 1% ripple factor for a full-wave rectifier
having a load resistance of 1.5KΩ? Assume the rectifier produces a peak output of 18V.

Page | 3
EME applied electronics – I worksheet -I
 16. Determine VO for each network of Figure below for the input shown.

17. Describe the output waveform of each circuit in figure below. Assume the RC time constant is
much greater than the period of the input.

18. Design a clamper to perform the function indicated in figure below.

Notice: - Assignment I- Q3, Q4, Q7, Q8, Q10, Q12, Q14, Q15, Q16 (A&D), Q18
Submission date:-

Page | 4
EME applied electronics – I worksheet -I
 Applied Electronics Worksheet II

1. Find VCE.VCB, VBE, IB, IC and IE in the figure and also Determine whether or not the transistor
are saturated

2. The transistor in the figure has βDC of 50 determine the value of RB required to ensure
saturation where VIN IS 5V.What must VIN be to cut off the transistor?Assume VCE(satu) = 0V.

3. Drive the formula for 𝛼𝐷𝐶 in terms of 𝛽𝐷𝐶 .

4. A certain 2N3904 DC bias circuit with the following value is in saturation. IB =500μA,
VCC=10V and RC=180Ὠ and ℎ𝑓𝑓 =150. If you increase VCC to 15V, does the transistor come to
out of saturation? If so, what are collector-to-emitter voltage and the collector current?
5. Design a DC bias circuit for an amplifier in which the voltage gain is to be minimum of 50 and
the output signal voltage is to be ‘’riding’ ’on a dc level of 5V. The maximum input signal
voltage at the base is 10mv rms. VCC=12V and VBB=4V.Assume re=8Ὠ.
6. Design a biased transistor circuit using VCC = VBB = 10V for Q-point of IC = 5mA and VCE =
4V Assume βDC =100.the design involves finding RB, RC and the minimum power rating of the
transistor. (The actual power rating should be greater).

7. Determine whether the transistor in figure is biased in cutoff, saturation and linear region. keep
in mind that IC= βDC IB is valid only in linear region.

1|Page
8. Given the information appearing in Fig.(A) determine where IB=40μA and VC=6V
(a) IC. (c) RB.
(b) RC. (d) VCE.

(A) (B)
9. For the emitter-stabilized bias circuit of Fig.(B) determine:
(a) IB, IC
(c) VCE, VC, VB and, VE

10. Given the information provided in Fig (A). determine: where VCE=7.3V, IB=20μA and
VE=2.1V. (A) β. (B) VCC & RB.

(A) (B) (C)

11. Given the information provided in Fig. (B) Determine: when VCC=12V.
(a) IC. (c) VB.
2|Page
(b) VE. (d) R1
12. (A) Determine IC, VCE, and IB for the network of Fig (C) using the approximate approach
even though the condition established is not satisfied.
(B) Determine IC, VCE, and IB using the exact approach.
(C) Compare solutions and comment on whether the difference is sufficiently large to require
standard equation when determining which approach to employ.
(D) Change β to 120 (50% increase), and determine the new values of IC and VCE for the
network.
13. For the collector feedback network of Fig.(A) determine:
(a) IC. (c) VE.
(b) VC. (d) VCE

14. Given VC = 8 V for the network of Fig. (B) Determine:

(a) IB. (c) β.
(b) IC (d) VCE

(A) (B)

15. For the E-MOSFET network given in the following figure, which has a minimum value of
𝐼𝐷(𝑜𝑛) = 200𝑚𝐴 at 𝑉𝐺𝑆 = 4𝑉 and 𝑉𝐺𝑆(𝑡ℎ) = 2𝑉. Determine: -

A) 𝑉𝐺𝑆 , Input voltage

B) The output voltage (𝑉𝐷𝑆 )
C) The gate voltage
D) Drain voltage

16. For the network given below, determine: -

A) The overall voltage & current gain

3|Page
 B) Calculate input & output impedance
C) Determine lower cutoff frequency due to𝐶1 , 𝐶2 𝑎𝑛𝑑 𝐶3
D) The overall lower cutoff frequency
E) Sketch the low-frequency response of the amplifier.

F) Determine 𝑓𝐻𝑖 𝑎𝑛𝑑 𝑓𝐻𝑜

G) Sketch the frequency responses of the amplifier for the high-frequency region.
H) Plot the frequency response of amplifiers and find Bandwidth
17) For the JFET amplifier circuit of Fig. below, determine
A) The current and voltage gain
B) Input and output impedance
C) lower- and higher-cutoff frequencies and sketch the frequency response.

4|Page
18. For the network given below, determine:
A) Voltage Current gain
B) Input and output impedance
C) Lower cut-& higher cut-off frequency for single stages
D) Overall lower and higher cut-off frequency
E) Plot the frequency response of multistage amplifier and find Bandwidth

19. For the network of multistage amplifier given bellow, Determine:

A) Voltage and Current gain
B) Input and output impedance
C) Overall lower- and higher- cut-off frequencies
D) Plot the overall frequency response of multistage amplifier and find bandwidth

5|Page
20. Design a voltage-divider bias network using a depletion-type MOSFET with I_DSS=10mA
and V_P=-4V to have a Q-point at I_D=2.5 mA using a supply of 24 V. In addition, set V_G=4V
and use R_D=2.5R_S with R_1=22MΩ. Use standard values.

Assignment: - Q4, Q6, Q9, Q12, Q13, Q15, Q16, Q17, Q18, Q19 & Q20

N.B: -Show all necessary steps clearly, unless your work will be invalid

6|Page
ECEg3104 - Applied Electronics-I Worksheet Chapter -1

1. Calculate the value of 𝑛𝑖 for gallium arsenide (GaAs) at T = 300 K. The constant B =
3.56 × 1014 𝑐𝑚−3 𝑘 −3/2 and the bandgap voltage Eg = 1.42 eV.
2. For a p-type silicon in which the dopant concentration 𝑁𝐴 = 5 × 1018 /𝑐𝑚3 , find the hole
and electron concentrations at T = 300 K.

3. For a silicon crystal doped with phosphorus, what must 𝑁𝐷 be if at T = 300 K the hole
concentration drops below the intrinsic level by a factor of 108 ?

4. A young designer, aiming to develop intuition concerning conducting paths within an

integrated circuit, examines the end-to-end resistance of a connecting bar 10μm long,
3μm wide, and 1μm thick, made of various materials. The designer considers:
a) intrinsic silicon

b) n-doped silicon with 𝑁𝐷 = 5 × 1016 /𝑐𝑚3

c) p-doped silicon with 𝑁𝐴 = 5 × 1016 /𝑐𝑚3

d) aluminum with resistivity of 2.8 μ·cm

Find the resistance in each case. For intrinsic silicon, use the data in Table 3.1. For
doped silicon, assume 𝜇𝑛 = 3𝜇𝑝 =1200𝑐𝑚2 /V.s

5. Find the current that flows in a silicon bar of 10μm length having a 5μm x 4μm cross-section and
having free-electron and hole densities of 104/cm3 and 1016/cm3, respectively, when a 1 V is
applied end-to-end. Use 𝜇𝑛 = 1200 cm2/V · s and 𝜇𝑝 = 500 cm2/V · s

6. Holes are being steadily injected into a region of n-type silicon. In the steady state, the
excess-hole concentration profile shown in Fig. 1.1 is established in the n-type silicon
region. Here “excess” means over and above the thermal-equilibrium concentration (in the
absence of hole injection), denoted 𝑝𝑝0. If N = 1016/cm3, 𝑛𝑖 = 1.5 × 10 /cm, 𝐷𝑝 = 12 cm2
/s, and W = 50 nm, find the density of the current that will flow in the x direction.

Fig. 1.1
ECEg3104 - Applied Electronics-I Worksheet Chapter -1

7. Calculate the built-in voltage of a junction in which the p and n regions are doped equally
with 5 × 1016 atoms/cm3. Assume 𝑛𝑖 = 1.5 × 1010 /𝑐𝑚3 . With the terminals left open,
what is the width of the depletion region, and how far does it extend into the p and n
regions? If the cross-sectional area of the junction is 20 μm2, find the magnitude of the
charge stored on either side of the junction.
8. If, for a particular junction, the acceptor concentration is 1017 /𝑐𝑚3 and the donor
concentration is 1016 /𝑐𝑚3 . Assume 𝑛𝑖 = 1.5 × 1010 /𝑐𝑚3 .
a) Find the junction built-in voltage.
b) Find the width of the depletion region (W) and its extent in each of the p and n
regions when the junction terminals are left open.
c) Calculate the magnitude of the charge stored on either side of the junction. Assume
that the junction area is 100μm2 .
9. By how much does 𝑉0 change if 𝑁𝐴 or 𝑁𝐷 is increased by a factor of 10?
10. Calculate 𝐼𝑠 and the current I for V = 750 mV for a pn junction for which 𝑁𝐴 = 1017 /𝑐𝑚3 ,
𝑁𝐷 = 1016 /𝑐𝑚3 , A = 100μm2 , 𝑛𝑖 = 1.5 × 1010 /𝑐𝑚3 , 𝐿𝑝 = 5 μm, 𝐿𝑛 = 10 μm, 𝐷𝑝 = 10
cm2 /s, and 𝐷𝑛 = 18 cm2 /s.
Problems on Transistor

EQ33. A common base transistor amplifier has an input resistance of 20 Ω and output resistance
of 100 kΩ. The collector load is 1 kΩ. If a signal of 500 mV is applied between emitter and
base, find the voltage amplification. Assume αac to be nearly one.

Q35. In a common base connection, current amplification factor is 0.9. If the emitter current is
1mA, determine the value of base current.

Q37. In a common base connection, the emitter current is 1mA. If the emitter circuit is open, the
collector current is 50 μA. Find the total collector current. Given that α = 0.92.

Q39. For the common base circuit shown in Fig. 3, determine IC and VCB . Assume the transistor
to be of silicon.

Fig. 3

Q41. Calculate IE in a transistor for which β = 50 and IB = 20 μA.

Q43. For a transistor, β = 45 and voltage drop across 1kΩ which is connected in the collector
circuit is 1 volt. Find the base current for common emitter connection.

Q45. An n-p-n transistor at room temperature has its emitter disconnected. A voltage of 5 V is
applied between collector and base. With collector positive, a current of 0.2 μA flows. When the
base is disconnected and the same voltage is applied between collector and emitter, the current is
found to be 20 μA. Find α, IE and IB when collector current is 1 mA.

Q47. For a certain transistor, IB = 20 μA; IC = 2 mA and β = 80. Calculate ICBO.

Q49. Determine VCB in the transistor circuit shown in Fig. 10 (i). The transistor is of silicon and
has β = 150.
Fig.10

Fig. 10 (i) shows the transistor circuit while Fig. 10 (ii) shows the various currents and voltages
along with polarities.

Q51. A transistor has the following ratings : IC (max) = 500 mA and βmax = 300.
Determine the maximum allowable value of IB for the device.

Q53. For the circuit shown in Fig. 12 , draw the d.c. load line.

Fig.12

Q55. In a transistor circuit, collector load is 4 kΩ whereas quiescent current (zero signal collector
current) is 1 mA. (i) What is the operating point if VCC = 10 V ? (ii) What will be the operating
point if RC = 5 kΩ ?

Q57. Determine the Q point of the transistor circuit shown in Fig. 18. Also draw the d.c. load
line. Given β = 100 and VBE = 0.7V.
Fig.18

Q61. If the collector current changes from 2 mA to 3mA in a transistor when collector-
emitter voltage is increased from 2V to 10V, what is the output resistance ?

Q63. For a single stage transistor amplifier, the collector load is RC = 2kΩ and the input
resistance Ri = 1kΩ. If the current gain is 50, calculate the voltage gain of the amplifier.

Q65. Determine whether or not the transistor in Fig. 24 is in saturation. Assume Vknee = 0.2V.

Fig.24

value corresponding to IC(sat) is increased, the collector current remains at the saturated value
(= 9.8 mA).

Q67. For the circuit in Fig. 27, find the base supply voltage ( VBB) that just puts the transistor
into saturation. Assume β = 200.
Fig.27 ,

Q69. Determine the state of the transistor in Fig. 28 for the following values of collector resistor
: (i) RC = 2 kΩ (ii) RC = 4 kΩ (iii) RC = 8 kΩ.

Fig. 28

Q71. The maximum power dissipation of a transistor is 100mW. If VCE = 20V, what is the
maximum collector current that can be allowed without destruction of the transistor?

Q73. For the circuit shown in Fig. 31, find the power dissipated in the transistor. Assume β =
100.

Fig. 31
 Addis Ababa Science and Technology University

College of Engineering

Department of Electrical and computer Engineering

Applied Electronics I

Instruction

 Make maximum group size should be Eight students each group will do one
unique question among 20 questions and last two questions.
 Questions selection is using lottery system, and section 1 six questions , section2
and section 3 will choose seven questions each .
 Your writing should be neat and clear
 For some of questions following individual instruction give with questions
 After selecting each section number of question by their representative, you will
report to me question numbers of each section.

Q1. Design a + 12 volt DC power supply using bridge rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q2. Design a -12 volt DC power supply using bridge rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system
2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q3. Design a + 12 volt DC power supply using center tap transform rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q4. Design a - 12 volt DC power supply using center tap rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q5. Design a + 24 volt DC power supply using bridge rectifier circuit.

Instruction:
1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q6. Design a -24 volt DC power supply using bridge rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q7. Design a -9 volt DC power supply using rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q8. Design a +9 volt DC power supply using rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q9. Design a +5 volt DC power supply using rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q10. Design a -5 volt DC power supply using rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q-11, Design a voltage regulator using zener diode that will maintain an output of 20V across a
1kΩ load with an input that varies between 30V to 50V. (i.e: Determine proper R s and IZM or
PD rating.)

Q12, Sketch Vo for the following clipper circuit.

13, Design a clamper to perform the function illustrated below.

14, Sketch Vo for the following clipper circuit.

15, Design a voltage regulator using zener diode that will maintain an output of 20V across a
1kΩ load with an input that varies between 30V to 50V. (i.e: Determine proper Rs and IZM or
PD rating.)

16. For common-emitter amplifier shown in fig let Vcc =9v , R1=27kΩ , R2=15kΩ. RE=1.2kΩ,
and Rc =2.2kΩ. The transistor has β=100 and va =100V. Calculate the dc bias current Ig. If the
amplifier operates between a source for which Rsign= 10KΩ and a load of 2kΩ replace the
transistor operates between a source for which Rsig =10KΩ and a load of 2kΩ, replace the
transistor with its hybrid- model, and find the values of Rin, the voltage gain V0/Vsign, and
the current gain .

Q17. Design a +15 volt DC power supply using bridge rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q18. Design a -15 volt DC power supply using transformer tap full wave rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q19. Design a -24 volt DC power supply using proper rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Q20. Design a +48 volt DC power supply using proper rectifier circuit.

Instruction:

1. Draw the neat block and schematic diagram of the designed dc power supply system

2. Determine the required components specification

3. Sketch the appropriate wave form of each stage of the circuit

4. Write a brief note how the circuit works

5. Practically test the system in the laboratory

Common Questions

A. Produce a report about frequency response of BJT amplifiers, your report should include
working principle, effect of frequency on amplifier gain , Bode plot (gain vs frequency
plot , etc.

B. Produce a report on each of the following specific topics your report should working
principle , biasing methods small signal modeling , etc .
a) JFET Common Gate configuration
b) JFET Common-Drain configuration
c) MOSFET
1/1/2020 Applied Electronics I Final Exam.pdf

1 of 2  Search document 

1. Name the different types of extrinsic semiconductors. How are they obtained from the intrinsic semiconductors?
(3pts.)
2. Compare the forward and reverse V- I characteristics of rectifier diode with that of a Zener voltage regulator
diode. (3pts.)
3. A loaded Zener regulator is shown below with VZ = 10 V, IZK = 0.25 mA, and IZM = 49 mA. Assuming Z Z = 0
Ω and V Z remains a constant 10 V over the range of current values, determine:
a. The minimum and the maximum load currents for which the Zener diode will maintain regulation. (4pts.)
b. The minimum and maximum value of R L that can be used? (3pts.)

4. Considering the following network:

A. What is the type of dc biasing circuit? ( 1pts.)
B. Determine IBQ, ICQ, and VCEQ. (5pts.)
C. Draw the dc load line and locate the Q-point commenting its position. ( 2pts.)
D. What is the type of small signal amplifier configuration? ( 1pts.)
E. Draw the ac equivalent circuit using Hybrid π model. ( 2pts.)

F. Calculate Zi, Zo, & Av. (6pts.) [take ro  Ω and rb  Ω ]

5. a) Describe the differences between BJT transistors and FET transistors. (2pt.)
b) Consider n-channel JFET, n-channel Enhancement-MOSFET and Depletion-MOSFET. Explain the basic
differences in terms of construction and operation principles. ( 3pts.)
6. Define the meaning of the following terms: (2pts.)
a) Cutoff frequency
b) Mid-range frequency (BW)

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