INTERVIEW QUESTIONS

1.Why we go for sv when we have already Verilog?

Ans:

Verilog System Verilog

1 Support structured paradigm Support structured and object-oriented
paradigms
2 Has the file extension .v or .vh Has the file extension .sv and. svh
3 Influenced by C and Fortran Influenced by Verilog. VHDL and C++
4 Supports wire and reg data types Supports various data types such as enum ,
struct, union, class and string.
5 has a single always block to implement to has always_comb, always_ff, and always_latch
combinational and sequential logic procedural block
6. Based on hierarchy of modules Based on classes
7 Uses module level testbench Uses class based testbench
8 Hardware Description language used to Hardware Description and hardware
model electronic systems Verification used to model, design, simulate,
test and implement electronic systems
9 Standardized as IEEE 1364 Standardized as IEEE 1800

Smart data structures don't exist in Verilog. Such as run-time sizing arrays that automatically handle
allocation and deallocation of chunks of the array.

System Verilog brings a higher level of abstraction to the Verilog designer. Constructs and commands like
Interfaces, new Data types (logic, int), Enumerated types, Arrays, Hardware-specific always (always_ff,
always comb) and others allow modeling of RTL designs easily, and with less coding

• Constrained-random stimulus generation

• Functional coverage

• Higher-level structures, especially Object-Oriented Programming, and transaction level modeling

• Multi-threading and inter process communication (IPC)

• Support for HDL types such as Verilog’s 4-state values

• Tight integration with event-simulator for control of the design.

OOP (Object Oriented Programming):

Object oriented programming involves the development of applications with modular, reusable
components.

Built on three important principles:

➢ Encapsulation
➢ Inheritance
➢ Polymorphism
Encapsulation: The technique of hiding the data within the class and making it available only through the
methods, is known as encapsulation.

1. Local

2. Protected

Inheritance is the principle of transferring the functionality and features of a “parent” to a “child”.

These three principles facilitate ease of code development, debugging, maintenance, reuse, and code
expansion

2. What is polymorphism …what are the rules for polymorphism?

Ans: Polymorphism means many forms. Polymorphism in System Verilog provides an ability to an object
to take on many forms. Method handles of super-class can be made to refer to the subclass method, this
allows polymorphism or different forms of the same method. How, many forms of a method can be made
by referring to the subclass method?
will see with an example,

Rules:

➢ Make the method as virtual in base and derived.

➢ Base class handle has no access to derived class methods even after handle assignment.
➢ With base class handle we cannot call methods which exists only in derived class.

3.Why SUPER Keyword?

Ans: super keyword is used in derived class to refer to the member of the base class. Super keyword must
be the first statement in derived class.

4. Tell me about distributed constraint?

Ans: after randomization repetition of the same value occurs to control the repetition of the value we use
dist operator, some values with the more weight will get allocated more times to a random variable. it take
aa list of values and weights separated by := and :/ operator.

The: = operator assigns the specified weight to the item, or if the item is a range, specified weight to every
value in the range.
 addr dist { 2 := 5, [10:12] := 8 };

for addr == 2 , weight 5

addr == 10, weight 8

addr == 11, weight 8

addr == 12, weight 8

The: / operator assigns the specified weight to the item, or if the item is a range, specified weight/n to
every value in the range. Where n is the number of values in the range.

addr dist { 2 :/ 5, [10:12] :/ 8 };

for addr == 2 , weight 5

addr == 10, weight 8/3

addr == 11, weight 8/3

addr == 12, weight 8/3

5.What is coverage? What are the types of coverages? Difference between the types?

Ans: Coverage is a generic term for measuring progress to complete design verification. Your simulations
slowly paint the canvas of the design, as you try to cover all of the legal combinations. The coverage tools
gather information during a simulation and then post-process it to produce a coverage report. You can use
this report to look for coverage holes and then modify existing tests or create new ones to fill the holes.
This iterative process continues until you are satisfied with the coverage level.

types: Code coverage

Functional coverage

Code Coverage Functional Coverage

Tell how well HDL code has been exercised by your Measures how well the functionality of the design
test benach has been covered by your test bench. User has to
define the functionality to be measured thorugh
coveage
Verifies completeness of verification env in terms Verifies completeness of verification env as per the
of hitting expression lines etc. of RTL code requirement spec and also functional coverage
point
Does not use design specification Use design specification
Support in all language Verilog does not support functional coverage. To
do functional coverage, system Verilog, specman E
or Vera are needed.
6. Suppose I have 90% code coverage; I want to increase 95% then what should I do?

Ans: To increase 95% we add cover bins and check why cover bins are not trigger

7. Suppose I have 90% functional coverage, I want to increase 95%, then what should I do?

Ans: To increase 95% in functional coverage. we check at particular block and adding missing conditions
and then trying to trigger to increase coverage.

8. What is Abstract class?

Ans:
➢ a class is declared as abstract with the keyword virtual.
➢ An abstract class is also known as Virtual class.
➢ An abstract class can never be directly instantiated. It can only be inherited or derived
➢ An abstract class can contain methods for which there are only a prototype and no implementation
just a method declaration.
9. What is Virtual interface? Why is it used?

Ans: A virtual interface is a pointer to an actual interface in SystemVerilog. It is most often used in
classes to provide a connection point to allow classes to access the signals in the interface through
the virtual interface pointer. (or)
A class is a dynamic property, which is created at run time while an interface is a static property, which is
created at compile time. So, it is not possible to instantiate a physical interface inside a class.

As the interface can't be instantiated inside a class or program block, we need a virtual interface to point
the physical interface. So, the virtual interface is a pointer to the actual interface and using virtual interface,
a class can point to different physical interfaces, dynamically (at run time).

A handle of virtual interface is used to reference a physical interface.

10. What is Shallow copy and deep copy. What are the keywords?

Ans: Shallow copy: A bitwise copy of an object, where a new object is created and it has the same copy of the
values in the original object, is called a Shallow copy. If any of the object fields refer to the other object then in
such cases only the reference address is copied.

Keyword is A=new B;

Deep copy: When the process of copying occurs repetitively and a copy of the object is always copied in
another object, then it is called deep copy.

Keyword is b=copy(a);

(or)

SystemVerilog deep copy copies all the class members and its nested class members. unlike in shallow copy,
only nested class handles will be copied. In shallow copy, Objects will not be copied, only their handles will
be copied. to perform a full or deep copy, the custom method needs to be added
11. What are Arrays? Different types of arrays?

Ans: An array is a collection of variables, all of the same type and accessed using the same name plus one
or more indices

➢ Fixed size arrays (eg: int ar[6])

➢ Packed and un-packed array (eg: int [7:0]ar and int ar[3:0])
➢ Dynamic array (eg: int ar [])
➢ Associative array (eg: bit arr[index_type])
➢ Queues (eg: bit q[$])

12. What is Randomization? Keywords used?

Ans: Randomization is the process of making something random, SV randomization is the process of
generating random values to a variable.

keyword is rand or randc

13. How will you do randomization for a variable?

Ans: System Verilog provides multiple methos to generate random data.

$unrandom() and $random()

$urandom_range()

std::randomize()

randomize()

14. Constraints…types of constraints?

Ans: SV allows users to specify constraints in a compact, the basic constraints are nothing more then a way
to let us define what legal values should be assigned to the random variables.

Types of constraint:

➢ Unique constraint
➢ Inline constraint
➢ Weighted distribution
➢ Conditional constraints
➢ Implication constraints
➢ Solve…. before constraint
➢ Inheritance constraint

15. Inline constraint?

Ans: System Verilog allows you to add an extra constraint using randomize with. this is nothing but adding
an extra constraint to any existing ones in effect.
16. Can u write a constraint for even numbers up to 100 which is going to the queue?

Ans: class A;

rand bit [7:0]arr[$];

constraint a_a { arr.size() inside {100};

foreach(arr[i])

arr[i]==i*2; }

endclass

program tb;

A a;

int i;

initial begin

a=new();

a.randomize();

$display("qe size =%0d",a.arr.size());

foreach(a.arr[i]) begin

$display("arr[%0d]=%0d",i,a.arr[i]);

end

end

endprogram

17. Different types of Functional coverages?

Ans: Functional coverage is a user-defined metric thar measures how much of the design specification has
been exercised in verification.There are two types of functional coverage

Data-oriented coverage: checks combinations of data values have occurred. We can get data-
oriented coverage by writing cover groups, cover points and also by cross coverage

Control-oriented coverage: checks whether sequences of behavior have occurred. We can get
assertion coverage by writing system Verilog assertions

18. Types of bins?

Ans:

• Implicit bins or Automatic bins

• Explicit bins or User-defined bins
 • Wildcard bins
• Ignore bins
• Illegal bins

19. Difference between always @(*) and always_comb?

Ans:

always@(*) always_comb()
1.it waits until a change occurs on a signal in the 1.it automatically executes once at time zero
inferred sensitivity list
2. always@ (*) is only sensitive to change to the 2.always_comb is sensitive to change within the
arguments of a function contents of a function
3.at RTL level, procedural block can be used to 3.always_comb procedural block also requires that
model combination, latched, sequential logic variables on the left-hand side of assignments
cannot be written to by any other procedural
block.

20.Difference between the overlapped and non-overlapped implication in assertions?

Ans:

Overlapped Non-overlapped
1.representation (|->) 1.representation (|=>)
2.there is a match on the antecedent then the 2. there is a match on the antecedent then the
consequent expression is evaluated in the same consequent expression is evaluated in the next
clock cycle clock cycle

21.what is fork join_none and fork join_any?

Ans:

fork join_none fork join_any

1.fork join_none will not wait for the completion of 1.fork join_any will be unblocked after the
processes inside the fork block completion of any of the processes
2.fork join_any fork block is non-blocking 2.fork join_any fork block is blocking

22.how you will get the signals in DUT? why we require clocking block?

Ans: The way to access internal signals of the DUT is to create an interface. In this case, I mean the software
programming concept of an interface that separates the testbench functionality from the DUT.

A clocking block specifies timing and synchronization for a group of signals.

The clocking block specifies,

 • The clock event that provides a synchronization reference for DUT and testbench
• The set of signals that will be sampled and driven by the testbench
• The timing, relative to the clock event, that the testbench uses to drive and sample those
signals

Clocking block can be declared in interface, module or program block.

23. difference between bit and logic? what we will use in monitor?

bit logic
1.bit has only 2 states (i.e. 0&1) 1.logic data type has 4 states (0,1,X,Z)
2.it can stimulate faster and less memory required 2.logic has additional bits that encode the X and Z
3.logic variable use when we want uninitialized and
unknown states

24. Write the complete structure of coverage class?

Ans: Cover group consists of cover points and cross

Cover point→ declaration of bins, illegal bins, ignore bins ,limited number of auto bins
created(auto_bin_max)

Cross → cross declared with cover point label name

Covegroup covr;

A: coverpoint a1 {

Ignore_bins h={6,7};

Illegal_bins k={8,9};

B: coverpoint b1 {

Ignore_bins h={6,7};

Illegal_bins k={8,9}; }

cros: cross A,B;

endgroup
25. environment hierarchy? what are the components in env?

Ans:

Components in Environment:

➢ Generator
➢ Driver
➢ Monitor
➢ Scoreboard

26. difference between break and continue?

Ans:

Break Continue
1.it stop the execution of remaining iteration of the 1.it stop only the current iteration of the loop
loop
2.break resumes the control of the program to the 2.continue resumes the control of the program to
end of loop enclosing that break the next iteration of the loop enclosing continue
3.it causes early termination of loop 3.it causes early execution of the next iteration
4.break stops the continuation of loop 4.continue do not stops the continuation of loop, it
stops current iteration
5.break can be used with switch and label 5.it cannot be executed with switch and labels
6. Syntax: Break 6. Syntax: Continue

27. difference between $random() and $urandom()?

Ans:

$random is fatal distribution of signed 32 bit random

$urandom is fatal distribution of unsigned 32 bit random.

28. What is interface? Which keyword is used for signal declaration?

Ans:

An interface is a named bundle of wires, the interfaces aim is to encapsulate communication.

Also specifies the

1.directional information, i.e modports

2.timing information, i.e clocking blocks

An interface can have parameters, constants, variables, functions, and tasks.

Uses keywords: interface

------

endinterface

29. What are modports?

Ans: Modports are used to specify the direction of signals with respect to module/components. Modports
are declared inside the interface with keyword modport

30. What is clocking block? Uses of it?

Ans: A clocking block specifies timing and synchronization for a group of signals.

The clocking block specifies,

➢ The clock event that provides a synchronization reference for DUT and testbench
➢ The set of signals that will be sampled and driven by the testbench
➢ The timing, relative to the clock event, that the testbench uses to drive and sample those signals
➢ Clocking block can be declared in interface, module or program block.

31. How to randomize variable without creating an object?

Ans: The scope randomize function, std::randomize() enables users to randomize data in the current scope
without the need to define a class or instantiate a class object.

32. How we can parallelly start two processes?

Ans: By using Thread fork-join block. Fork-join block will start all the processes inside the it parallelly and
wait for completion of all processes.
33. How to stop process 2, before processer one completes (At any time)?

Fork

Process1

Process2

Join

Ans: As fork-join run all the process concurrently we can not stop process 2 before process 1 ends, instead
we use join_any (with considering some delays in process 2) and disable fork; , so when we use join_any
process 1 will run and it will come out of block and disable fork will execute.

34. Write a constraint for any array? Size should be in the range of 10 to 20 and Each value should be
unique?

Ans: class que;

rand bit [3:0] arr[$];

constraint pkt_a { arr.size() inside {[10:20]}; unique{arr}; }

function void print();

$display("qu =%p",arr);

endfunction

endclass

program tb;

que a;

initial begin

a=new();

a.randomize();

a.print();

$display("que size =%0d",a.arr.size());

end endprogram
35. Difference between rand and randc?

Ans: Rand is a random variable whose same value may be arrived at before returning all the possible values.
It can be compared to throwing dice.

Randc, on the other hand, refers to a random cyclic variable whose same value cannot be returned unless
all the possible values have been returned. It can be compared to picking a card from a group of cards
without making any replacements.

36. Write a checker for the scenario below, If I am writing into 1st address with data 1, 2nd address with
data 2, 3rd address with data 3 and so on and i am reading it randomly, suppose if i write data 4 into the
2nd address how will you make sure that while reading you will get the latest updated value?

37. If both code coverage and functional coverage is 100%. Is my verification is successfully completed?
Ans:

➢ No!!!! Do multiple reviews of the test cases and functional coverage.

➢ Do review the waveform of few test cases to check test is doing as expected.
➢ Do read the specification multiple time and check that there is functional coverage for each
functional scenario.

38.If my code coverage is 100% and functional coverage is 80%. How to improve functional coverage?
Ans: you don't have test cases which are covering the functional scenarios which are coded in functional
coverage. so, you need to create the test cases which can exercise those functional scenarios.

39. If my functional coverage is 100% and code coverage is 80%. How to improve code coverage?
Ans: There is hole in your functional coverage. you don't have test cases which exercise those code. So
write the test cases which exercise those code and modify the functional coverage code to add those
missing functional scenarios.

➢ There is also chance that design having the dead code.

40. What is the difference between the mailbox and queue?

Ans: mailbox essentially behaves like a queue. it is quite different from the queue data type. A simple queue
can only push and pop items from either the front or the back. However, a mailbox is a built-in class that
uses semaphores to have atomic control the push and pop from the queue. Moreover, you cannot access
a given index within the mailbox queue, but only retrieve items in FIFO order.
41. Four processes are present, write code such that after completion of any one process kill remaining
process?

Ans: program tb;

initial begin

fork

//process 1

begin:T1

$display($time,"\tProcess-1 Started");

#5;

$display($time,"\tProcess-1 Finished");

end

//process 2

begin:T2

$display($time,"\tProcess-2 Started");

#20;

$display($time,"\tProcess-2 Finished");

end

//process 3

begin:T3

$display($time,"\tProcess-3 Started");

#15;

$display($time,"\tProcess-3 Finished");

end

//process 4

begin:T4

$display($time,"\tProcess-4 Started");
 #2;

$display($time,"\tProcess-4 Finished");

end

join_any

disable fork;

end

endprogram

42. For above, write code such that after completion of any two process kill remaining process?
Ans: program tb;
initial begin
int count;
event e;
fork
//process 1
begin:T1
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
count = count+1;
$display("count=%0d",count);
if(count==2)
->e;
end
//process 2
begin:T2
$display($time,"\tProcess-2 Started");
#12;
$display($time,"\tProcess-2 Finished");
count = count+1;
 $display("count=%0d",count);
if(count==2)
->e;
end
//process 3
begin:T3
$display($time,"\tProcess-3 Started");
#15;
$display($time,"\tProcess-3 Finished");
count = count+1;
$display("count=%0d",count);
if(count==2)
->e;
end
//process 4
begin:T4
$display($time,"\tProcess-4 Started");
#20;
$display($time,"\tProcess-4 Finished");
count = count+1;
$display("count=%0d",count);
if(count==2)
->e;
end

join_any
wait(e.triggered());
end
endprogram
43. How do connect Monitor and scoreboard?

Ans: In system Verilog we connect monitor and scoreboard by using mail box or semaphore. In monitor we
put some data and get the same data scoreboard.

44. In SV environment, can we connect the queue in place of mailbox?

Ans: No, mailbox is same as queue, but a mailbox is a built-in class that uses semaphores to have atomic

control the push and pop from the queue. Moreover, you cannot access a given index within the mailbox

queue, but only retrieve items in FIFO order.

35. Take scenario: Address -8-bit Data-8 bit Write constraint to generate address multiples of 4

and in data give more weight to 0 to 32 and less weight to 33 to 256?

Ans: class sample;

randc bit [7:0]addr;

randc bit [7:0]data;

constraint sample_a { data dist { [0:32]:=35, [33:256]:/25};}

endclass

program tb;

sample s;

int i;

initial begin

s=new();

repeat(10)

begin

s.randomize() with {addr[1:0]==0;};

 $display("data=%0d addr=%0d",s.data,s.addr);

end

end

endprogram

UVM
1. Why we go for UVM?

Ans:

➢ It is supported by multiple simulator vendors

➢ Sequence methodology gives a more intuitive interactive control of generated items (rather than
generators and callbacks)
➢ Config mechanisms can simplify control of components deep within hierarchy
➢ Factory mechanisms can simplify modifications of components deep within hierarchy or under the
control of another source (VIP, for example)

2. Adv of UVM compare to SV?

Ans:

➢ modularity and reusability.

➢ It separating test from testbench.
➢ Simulator independent.
➢ Configuration mechanism
➢ Factory mechanism
➢ Reporting mechanism- filter the level of messages with help of verbosity
➢ It has in built base class library (copy, compare, print. Etc..)
➢ Phase mechanism—this mechanism for only uvm_componets not for uvm_object because outside
of the env.
➢ TLM (It supports multiple languages)-port to port connection.

3. What are UVM phases? Which is main phase?

Ans:

➢ Build phases
➢ Run phases
➢ Cleanup phases

Main phase: Run phases

4. What is UVM test bench and its components?

Ans:

5. Why we need to use 'uvm_component_utils for components?

Ans: for factory registration of component definition

6. How will you differentiate the active agent and passive agent in uvm?

Ans: Active agent is where a driver and sequencer are need to generate stimulus and also has input monitor

Passive agent is where only an output monitor exits to observe data.

7. Uvm_sequence: Is it object or component? Why?

Ans:

➢ uvm_sequence is object.
➢ It contains only one argument that is name.
➢ no phasing mechanism in object.

8. Why do we use start () method? Where do we declare it?

Ans: start () method is used in test uvm_component in run phase. It used to connection between sequence
and sequencer.