IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India

2-Bit Magnitude Comparator using GDI Technique

*
Vijaya Shekhawat, Tripti Sharma and Krishna Gopal Sharma
ECE Department
FET-MITS (Deemed University)
Lakshmangarh, Distt- Sikar, Rajasthan, INDIA
Email: [email protected]@gmaiLcom and sharmaJ(g@gmaiLcom

Abstract- In recent years, low power design has become one of though heavily pipeline is useful to achieve high throughput
the prime focuses for the digital VLSI circuit. Keeping the same but it may not be suitable for all applications, such as in the
in mind a new design of 2-Bit GDI based Magnitude Comparator ARM microprocessor [8] which is often need to execute a
has been proposed and implemented with the help of full adder comparison instruction with a single clock cycle. Hunag
which is the basic building block of ALU. Proposed GDI proposed comparator using single clock cycle based on the
technique based magnitude comparator has an advantage of less
priority-encoding algorithm [9]. It not only improves the
power consumption with respect to various design parameters;
operating speed but also make circuit more power efficient In
less on-chip area covered as less number of transistors are
Parallel MSB checking algorithm [10] and MUX-based
required in circuit design as compared to conventional CMOS
structure [11] where proposed to improve the performance of
magnitude comparator. Both the circuits are designed and
comparator at the expense of twice the number of transistor.
simulated using Tanner EDA Tool version 12.6 at 45nm process
technology. All of aforementioned works give high performance using
dynamic logic. But dynamic logic is not suitable for low
Keywords- Magnitude Comparator; GDI Technique; Full power operation as compared to static logic; dynamic activity
Adder and Low Power.
factor is 0.5 and 0.1 for static logic which is advantageous.

The CMOS technology [12] have resulted many circuit

I. INTRODUCTION design logic style during the last two decade [13] and [14].
Recently, the market demand for mainly three things: low The various topologies such as conventional CMOS, nMOS
power, high speed and less area for designing the circuit So pass transistor logic, transmission gates and pseudo nMOS
intensified research is going on low power, high speed logic style. By using all this logic style 2-Bit magnitude
embedded systems used in mobiles, laptops etc has led to scale comparator has been implemented by Vandana[15] and
down technology to nano regimes, allow to implement more Anjuli [16].
functionality on single chip,
The work done in [15] and [16] has shown that the output
The magnitude comparator is a fundamental arithmetic voltage swing is better in CMOS logic design and
component of digital system, Now-a-days, most important transmission gate design, Whereas, Transmission gate logic
problem in computer science is sorting. Sorting is useful in require more no. of transistor as compare to CMOS design.
fundamental process such as in communication and computing But Pseudo nMOS and PTL logic style less no transistor in
systems. Sorting of data problem can be solved by comparator, comparison to CMOS logic style. There is output voltage
where comparator play an important role in the areas of swing degradation in PTL and Pseudo nMOS logic style,
parallel computing, multiprocessing and multi-access
To overcome this problem a new logic style (GDI
memories, A magnitude comparator is also used in Digital
Technique) has been proposed by A, Morgenshtein [17], OD!
Signal Processors (DSP) for data processing, microprocessor
technique is superior over other design technique in term of
for decoding instruction and microcontroller for controlling
low power and high speed VLSI design, In OD! technique,
temperature of furnace in industry.
simple use basic GDI cell consisting of only two transistors
The traditional method to implement the comparator is by and three inputs; to implement various complex function, The
flattering the logic function directly, but this method is only feature of this technique is improved logic level swing,
suitable for the comparator with less number of inputs [1], characteristic performance and also allows a simple design of
When large number of input is applied, circuit complexity any logic circuit using a small GDI cell. It is proved that GDI
increases drastically and the operating speed is degraded technique required lesser number of transistor and low power
accordingly. Alternative way to implement the comparator is consumption for the implementation of different logic style, in
by using a parallel adder [2]. In this method, the adder has comparison with CMOS logic style, nMOS Pass transistor
become the major factor for reducing the operating speed, A logic and transmission gate [18].
thousand numbers of transistors are used to increase the speed
The 2-Bit ODI Magnitude Comparator is proposed which
of adder [3]-[5], Richard [6] proposed a new logic all-n-logic
has an advantage; less number of transistors and low power
(ANL) to improve the operating speed. Wang [7] used this
consumption, The paper is organized into five sections,
logic and implemented 64 bit high-speed comparator with two
Section I give the introduction and literature review of
phase clock. It is designed by using six pipeline circuit, and
magnitude comparator and Section II present basic of
each comparison operation through these six pipelines, Even
magnitude comparator and conventional CMOS magnitude

[978-1-4799-4040-0/14/$31.00 ©2014 IEEE]

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 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India

comparator, Section III proposed 2-Bit GDI magnitude

comparator, Section IV shows the performance analysis of 11 B>A (Fl)
proposed 2-Bit GDI magnitude comparator and conventional
/ A N Bit Magll1tude
CMOS comparator, Section V concludes the paper with the
result Comparator

II. CONVENTIONAL CMOS MAGNITUDE COMPARATOR

B=A (Fl)
11
Now days CMOS (Complementary Metal Oxide
Semiconductor) logic style is the primary technology in the I B
Semiconductor Industry. Conventional method is used to B<A IF3)
construct schematic of 2-Bit magnitude comparator using
CMOS technique. Here is the brief description of CMOS
inverter, Fig. 2. N- bit Magnitude Comparator.

Fig. 1 show symbol of CMOS inverter consists of pMOS TABLE I. TRUTH TABLE OF 2 -BIT MAGNITUDE COMPARATOR
and nMOS transistor connected at the drain and gate terminal,
a supply voltage VDD at the pMOS source terminal and GND
Al AO 81 80 F2 FI F3
connected at the nMOS source terminal. Whereas input (A) is
connected to the gate terminals and output (Abar) is connected 0 0 0 0 1 0 0
to the drain terminal.
0 0 0 1 0 1 0
If input A=O, then pMOS is ON and provide low
impedance path from VDD to output (Abar). At that time 0 0 1 0 0 1 0
nMOS is in OFF condition, thus output (Abar) approach to
0 0 1 1 0 1 0
high level that is VDD. If input A= l, then nMOS is ON and
pMOS is in OFF condition, nMOS provide low impedance 0 1 0 0 0 0 1
path from output (Abar) to ground. Therefore, output (Abar)
approach to low level that is OV. The substrate pMOS is 0 1 0 1 1 0 0
always connected to VDD and nMOS substrate is always
0 1 1 0 0 1 0
connected to GND. The CMOS inverter provides two
important advantages, low static power dissipation and high 0 1 1 1 0 1 0
noise margin. It is also balanced device, so it is called ratio­
1 0 0 0 0 0 1
less device.

An N-Bit magnitude comparator is shown in Fig. 2, it 1 0 0 1 0 0 1

compare two n bit binary number A and B and the outcome of

1 0 1 0 1 0 0
n bit magnitude comparator is denoted by A< B (FI), A= B
(F2), A> B (F3). 1 0 1 1 0 1 0

To determine whether A is greater than B or vice versa and 1 1 0 0 0 0 1

then firstly check the most significant bit If most significant
1 1 0 1 0 0 1
bit of both inputs is different, e.g. suppose most significant of
A is 1 and most significant bit of B is 0 then A> B, if condition 1 1 1 0 0 0 1
is reverse then A<8. If most significant bit of both the input is
equal then go for next bit and then compare the next bit of 1 1 1 1 1 0 0
both the input If both the inputs are same then A= B.
The outcome of 2-Bit magnitude comparator is shown in
Table I for different combination of input According to
different condition of input, the equations are as follow:

A> B := A1 B1 + AO BO(A1 B1 + A1B1)

:= A1 B1 + AO BO(X1) (I)

A=B := (A1 B1 + A1 B1)(AO BO + AOBO)

Fig. 1. CMOS Inverter := Xl XO (2)

A < B := A1B1 + AOBO(A1 B1 + A1B1)

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 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India

:= AIBI + AOBO(Xl) (3)

According to this condition, 2-Bit conventional CMOS

magnitude comparator schematic is made as shown in Fig .3.

Fig. 3. Schematic of 2- Bit Magnitude Comparator using Conventional CMOS Logic Style

TABLE II. FUNCTIONS IMPLEMENTED USING GDI CELL

Looking into Fig.3, it reveals that 2-Bit Magnitude
Comparator requires large number of transistors i.e.; 66. This N P G Out Function
large transistor count consumes more power and larger area,
so to overcome this problem GDI technique is used to 0 1 A A Inverter
construct magnitude comparator.
0 B A AB Function I

III. PROPOSED GD! 2-BIT MAGNITUDE COMPARTOR B 1 A A+B Function 2

The basic GDI cell is shown in Fig. 4 at first sight by seeing 1 B A A+B OR
basic GDI cell it remind us standard CMOS inverter, but there
is some important difference B 0 A AB AND
• In Basic GOI cell, there is three input G (Common
C B A AB+AC MUX
gate input of nMOS and pMOS), P (input to the
source/drain of pMOS) and N (input to the B B A AB+AB XOR
source/drain of pMOS).
• Substrate of both nMOS and pMOS are connected to B B A AB+AB XNOR
N or P (respectively), so these points are contrast with To design MUX usually require 8-12 transistor by using
CMOS inverter [19]. traditional CMOS or PTL logic style which is bit complex
In Table II, different functions are implemented by using design., whereas we require just 2 transistor in GOI technique
simple GD! with different input configurations. to implement MUX which is quite simple. The main attracting
point in GOI technique, to implement Function I and
p Function2 GDI technique requires 2 transistors whereas in
CMOS technique requires 6 transistors. GOI technique allow
user to use less no. of transistor, simpler gate and low power
dissipation in many implementation, in comparison to CMOS,
Pass transistor and transmission gates [6]. But the demerit of
G- GOI technique is swing degradation problem, this problem can
Ol..1.t
be overcome by adding buffer.

The logic diagram of 2-Bit Magnitude Comparator based

on full adder is shown in Fig. 5. A basic full adder has three
inputs and two outputs. In full adder logic sum output is useful
N to get output F2 and Cout is useful to get output Fl. As shown
Fig. 4. Basic GDI cel in Fig. 5, require XOR gate, MUX & AND gate for logic
circuit of full adder which useful to design magnitude

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 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India

comparator, For the logic sum require XOR gate and f?r car�y IV. SIMULATION RESULT & DISCUSSION
output (Cout) require AND & OR gate. XOR gate IS basIc
The simulation of conventional CMOS and proposed GDI
building block of full adder; many refmements have been done
magnitude comparator is performed on Tanner EDA tool
to reduce the number of transistor and also for better
version 12.6 using 45nm technology with input voltage
performance of XOR gate.
varying from 0.7V to I V. In order to prove that proposed GDI
As discussed, GDI technique require less transistor for
magnitude comparator design is consuming low power and
AND, OR and XOR gate in compare conventional CMOS
have high performance, simulation is carried out for power
logic technique. So GDI technique is preferred to construct
consumed at different range of input voltage, temperature and
this logic function in compare to CMOS logic style. If one
frequency. The Fig. 7, reveal that power consumed by the
inverted input is given to XOR gate then it act like XNOR
proposed GDI comparator is 82.2% at 0.7 V and 83.9% at IV
gate, so reduce the number of transistor XOR gat� with
. is less in compare to conventional CMOS magnitude
inverter input is replace with XNOR gate. GDI techmque IS
comparator, Fig. 8, compares the power consumed by CMOS
used to construct 2-Bit magnitude comparator based on full
and proposed GDI magnitude comparator with respect to
adder is shown in the Fig. 6. For the output of F3, the
different temperature at 0.8V, which show that power
condition used is, if F2 and Fl is 0 then F3 is I. GDI
consumed by of proposed GDI magnitude comparator is less
technique magnitude comparator requires (30 transistor) less
(81% approx.) in comparison to CMOS magnitude
no of transistor in compare to conventional CMOS magnitude
comparator.
comparator (66 transistor).
1.00E-07
�
2 �
<=
0 1.00E-OS
R
"

E
;;;
<=
0
U 1.00E-09
...
v
:::
0
0..

1.00E-l0
0.7 O.S 0.9 1
Input Voltage(V)

--+-Conventional CMOS Comparator

_Proposed GDI Comparator

Fig. 5. Logic diagram 2-Bit magnitude comparator using full adder Fig. 7. Power consumption at varying Input Voltage

1.00E-07
�

J�2��
l �
<=
0 1.00E-OS
B1
"R
E
;;;
<=

D'"
0
U
1.00E-09
...
v
:::
0
0..
1.00E-l0
-10 o 10 20 30 40 50

Temperature (DC)
--+-Conventional CMOS Comparator

_Proposed GDI Comparator

Fig. 6. Schematic of 2 Bit Magnitude Comparator using GDI Technique Fig. 8. Power comparison over the range of temperature

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 IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), May 09-11, 2014, Jaipur, India

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