PCI Bus Architecture

Introduction
• Introduction
• History of the Bus
• Performance
• Plug and Play
• How it works
• Other types of the PCI Bus
• Future of the PCI Bus
• Conclusion
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 Overview
• If you were installing a new sound, network, or video card
in your computer in the ’90s, it was probably built to the
old PCI standard, which described how to link these
devices via physical wires to other parts of your computer.
• PCI was exciting for its time. PCI devices are easier to
install than devices built to the previous ISA (Industry
Standard Architecture). When an ISA device was plugged
into the I/O bus, a computer could access it by
communicating over the matching address on the bus. But
it was hard to know in advance what devices would
respond to a request, where the devices were located in I/O
space, if the computer had the correct drivers to interact
with the ISA card, or for devices to avoid conflicting with
each other. 3
PCI vs ISA

4
 Introduction of Config. Space
• PCI changed this by introducing the notion of
“configuration space,” a set of registers on the device area
that allows the system to ask the card for information about
itself, and respond accordingly.
• PCI also had greater bandwidth than its predecessors, and
thus it quickly became ubiquitous. However, as time went
on, PCI’s limitations became more apparent:
– The speed of a set of PCI devices was limited to that of
the slowest device on the bus. Connecting one outdated
peripheral would slow down all devices.
– At the same time, demand for speed was at an all-time
high, as gigabit ethernet became widespread, and PCI
devices couldn’t keep up.
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Config Space

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7
 Introduction
• A computer bus is used to transfer data from one location
or device on the motherboard to the central processing unit
where all calculations take place.
• Two different parts of a Bus
– Address bus-transfers information about where the data
should go
– Data bus-transfers the actual data

8
 History
• PCI(Peripheral Component Interconnect) bus is based on ISA (Industry
Standard Architecture) Bus and VL (VESA Local) Bus.
• Introduced by Intel in 1992
• Revised twice into version 2.1 which is the 64-bit standard that it is
today.
• Great feature of PCI Bus was that it was invented as an industry
standard
• PCI provides direct access to system memory for the devices that are
connected to the bus which is then connected through a bridge that
connects to the front side bus.
• This configuration allowed for higher performance without slowing
down the processor

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 History
•The PCI Bus was
The picture can't be display ed.

originally 33Mhz and

then changed to
66Mhz.
•PCI Bus became big
with the release of
Windows 95 with “Plug
and Play” technology
•“Plug and Play”
utilized the PCI bus
concept.
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 PCI System Bus Performance
• What makes the PCI bus one of the fastest I/O bus
used today?
• Three features make this possible:
– Burst Mode: allows multiple sets of data to be sent
(Kozierok, 2001a)
– Full Bus Mastering: the ability of devices on the PCI
bus to perform transfers directly (Kozierok, 2001c)
– High Bandwidth Options: allows for increased speed of
the PCI (Kozierok, 2001a)

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 How PCI Compares to Other Buses
Bus Bus Speed MB/sec Advantages Disadvantages
Bus Type Width

ISA 16 bits 8MHz 16 MBps low cost, low speed, Jumpers

compatibility, & DIP switches.
widely used becoming obsolete

PCI 64 bits 133 MHz 1 GBps very high speed, incompatible with
Plug & Play, older systems,
dominant board- can cost more
level bus
CompactPCI 64 bits 33MHz 132 MBps designed for lower speed than
industrial use, hot PCI, need adapter for
swapping/Plug & PC use, incompatible
Play, ideal for with older systems
embedded
systems

Table 1: How PCI compares to other buses (Tyson, 2004a; Quatech, 2004c) 12
 Plug and Play
• Requirements for full • Tasks it automates:
implementation: – Interrupt Requests
(IRQ)
– Plug and Play BIOS
– Direct Memory Access
– Extended System (DMA)
Configuration Data – Memory Addresses
(ESCD)
– Input/Output (I/O)
– Plug and Play Configuration
operating system
(Tyson, 2004b)

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 How PCI Works: Installing A
New Device
• Once a new device has 3. The device will respond
been inserted into a PCI with its identification and
slot on the motherboard send its device ID to the
1. Operating System Basic BIOS through the bus.
Input/Output System 4. PnP checks the Extended
(BIOS) initiates Plug and System Configuration Data
Play (PnP) BIOS. (ESCD) to make sure the
2. PnP BIOS scans the PCI configuration data already
bus for any new exists for the card. (If the
hardware connected to card is new, then there will
the bus. If new hardware be no data for it.)
is found, it will ask for
identification.

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 New Device Cont…
5. PnP will assign an Interrupt 7. Windows will determine the
Request Line, Direct device and attempt to install
Memory Access, memory its driver. The operating
address and Input/Output system may ask the user to
settings to the card, then
stores the information in the insert a disk containing the
ESCD. driver or direct it to where the
6. When the Windows software driver is located. In the
loads, it will check the PCI event that Windows is
bus and the ESCD to see if unable to determine what the
there is new hardware. device is, it will provide a
Windows will alert the user dialog window so the user
that new hardware has been can identify the hardware
found if there is new and load its driver.
hardware installed and will
also identify the hardware.
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 How a Device Works
• Example: PCI-based 3. If the sound card is in
recording mode, the bus
sound card controller will assign a high
1. The sound card will convert priority to the data coming
the analog signal to a digital from the sound card. It will
signal. send the sound cards data
2. The digital audio data carried over the bus bridge to the
across the PCI bus to the bus system bus.
controller, which determines 4. The system bus will save the
which device on the PCI data in system memory.
device has the priority to send When the recording is
data to the central processing complete, then it will be up to
unit (CPU) and whether the the user to save the data from
data will go directly to the the sound card on either the
CPU or to the system hard drive, or will remain in
memory. memory for additional
processing.
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 Other Types of PCI
• Original PCI
• PCI 2.3
• PCI-X
– PCI-X 2.0 (second
revision)
• PCI Express

Figure: PCI-X 2.0 card

(http://ch272.thinkquest.hostcenter.ch/cgi-
local/community.pl?action=pc_theme&lang=ge)

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 Future of PCI:
Requirements

• Support multiple market segments

• Backwards compatible
• Scalable performance
• Advanced features including QoS, power
management, and data integrity

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 PCIe
• To take on the limitations of PCI, PCIe needed to tackle
issues with bus sharing and bus contention.
• When multiple devices were on the same PCI bus, PCI was
forced to “clock down” and match the speed of the slowest
device on the bus.
• PCIe uses some electrical cleverness to address this. By
encoding data using the 8b/10b line code, PCIe is able to
encode both data and clock information in a single signal,
removing the need for an external clock and greatly
increasing potential bandwidth. (Newer versions of
PCIe have continued to improve on this; PCIe 3.0 and
onward encode with 128b/130b and enable even faster
transfer rates.)

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 PCIe as Network
• Additionally, PCIe needed a way to handle high-speed data
streaming. If a device didn’t have enough buffering to
contain all the data it wanted — as is the case with, say,
high-definition video — then naturally you’d like the
device to continuously stream the data. However, while
that device was busily streaming a huge amount of data, it
would put a stranglehold on the bus, preventing all the
other devices from doing anything. PCIe resolves this issue
by allowing for packet fragmentation, breaking up the data
stream into smaller packets that can be transmitted via the
transaction layer protocol that underlies the PCIe fabric.
• Thus, it’s easier to think of PCIe as a network, rather than a
physical bus. Each device has an address, and the spec
describes functionality for flow control, error detection,
and retransmissions, none of which existed in PCI.
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PCI Express Solution

21
 Advanced Switching
with PCI express

• Signals take place at

link level
• Allows for QoS and
fan out capabilities
• Utilizes system
bandwidth

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 Conclusion
• Due to the need for growing data transfer
rates among IO devices, the original PCI
Architecture has become outdated

• A new model of PCI, called PCI Express

will replace the dated architecture giving it
life for another decade

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 Lab Exercise
$ lspci | cut -d: -f1-2
0000:00:00.0 Host bridge
0000:00:00.1 RAM memory
0000:00:00.2 RAM memory
0000:00:02.0 USB Controller
0000:00:04.0 Multimedia audio controller
0000:00:06.0 Bridge
0000:00:07.0 ISA bridge
0000:00:09.0 USB Controller
0000:00:09.1 USB Controller
0000:00:09.2 USB Controller
0000:00:0c.0 CardBus bridge
0000:00:0f.0 IDE interface
0000:00:10.0 Ethernet controller
0000:00:12.0 Network controller
0000:00:13.0 FireWire (IEEE 1394)
0000:00:14.0 VGA compatible controller

$ cat /proc/bus/pci/devices | cut -f1

0000
0001
0002
0010
0020
0030 24
 Cont.
$ tree /sys/bus/pci/devices/
/sys/bus/pci/devices/
|-- 0000:00:00.0 -> ../../../devices/pci0000:00/0000:00:00.0
|-- 0000:00:00.1 -> ../../../devices/pci0000:00/0000:00:00.1
|-- 0000:00:00.2 -> ../../../devices/pci0000:00/0000:00:00.2
|-- 0000:00:02.0 -> ../../../devices/pci0000:00/0000:00:02.0
|-- 0000:00:04.0 -> ../../../devices/pci0000:00/0000:00:04.0
|-- 0000:00:06.0 -> ../../../devices/pci0000:00/0000:00:06.0
|-- 0000:00:07.0 -> ../../../devices/pci0000:00/0000:00:07.0
|-- 0000:00:09.0 -> ../../../devices/pci0000:00/0000:00:09.0
|-- 0000:00:09.1 -> ../../../devices/pci0000:00/0000:00:09.1
|-- 0000:00:09.2 -> ../../../devices/pci0000:00/0000:00:09.2
|-- 0000:00:0c.0 -> ../../../devices/pci0000:00/0000:00:0c.0
|-- 0000:00:0f.0 -> ../../../devices/pci0000:00/0000:00:0f.0
|-- 0000:00:10.0 -> ../../../devices/pci0000:00/0000:00:10.0
|-- 0000:00:12.0 -> ../../../devices/pci0000:00/0000:00:12.0
|-- 0000:00:13.0 -> ../../../devices/pci0000:00/0000:00:13.0
`-- 0000:00:14.0 -> ../../../devices/pci0000:00/0000:00:14.0

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End of Presentation

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