3D RISC-V STA Flow Using Integrity 3D-

IC Platform
Rapid Adoption Kit (RAK)

Product Version:

Integrity 3D-IC Platform - Innovus 23.12

TEMPUS – SSV 22.14-s061_1

October 2024
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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Contents

Purpose ........................................................................................................................... 3
Audience ......................................................................................................................... 4
RAK Version.................................................................................................................... 4
Prerequisite ..................................................................................................................... 4
Terms .............................................................................................................................. 4
Module 1: Stack STA Analysis (Hierarchy Mode) .......................................................... 6
Step 1: Create Spef and MMMC files. .........................................................................6
Step 2: Launch Tempus. ..............................................................................................7
Step 3: Enable analysis in Tempus. ............................................................................7
Step 4: Bring up die database in Tempus. ..................................................................7
Step 5: Start to perform analysis. ................................................................................8
Step 6: View the report. ...............................................................................................8
Module 2: Stack STA Analysis (Flatten Mode) .............................................................. 9
Step 1: Launch Integrity 3D-IC. ...................................................................................9
Step 2: Enable analysis in Integrity 3D-IC...................................................................9
Step 3: Bring up die database in Integrity 3D-IC.........................................................9
Step 4: Start to perform analysis. ..............................................................................10
Step 5: View the report. .............................................................................................11
Support .......................................................................................................................... 12
Feedback ...................................................................................................................... 12

Purpose
This Rapid Adoption Kit (RAK) is aimed at providing an introduction and guideline for
performing STA on the Integrity 3D-IC platform.
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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Audience
This RAK is developed for 3D-IC chip designers who intend to explore the timing
analysis and behavior through STA analysis with given design conditions.

RAK Version
This RAK is intended to be used with the riscv_3dic_v3q_sta.tgz RISC-V version.

Contents of this RAK can be reproduced in batch mode via the Makefile by running the
following in the RAK installation directory:

Hierarchy Mode:
Linux> make demo_bm

Flat Mode:
Linux> make demo_sta

Prerequisite
This RAK resumes from the data generated from the RAK "3D RISC-V Codesign and
Analysis Using Integrity 3D-IC Platform RAK." That data can also be regenerated via a
batch command.

Terms
iHDB Integrity Hierarchical Database

MMMC Multi Mode Multi Corner

BM Boundary Model

CUI Stylus Common UI

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Overview
• As the reduction of critical size on chips becomes saturated or stagnant,
designers are now focusing on building devices in the third dimension out of the
plane where the chip sits, through heterogeneous packaging in a 3D-IC
configuration.
• The heterogeneous packaging structure might include multiple chiplets being
placed on a common silicon interposer, or aggregate memory units, CPUs, and
other functional modules by advanced interconnect within the chiplets.
• Signoff scenarios and design size will be exploded while composing die into
stack analysis.
• Tempus hierarchical flow can reduce the design size by using BM for each die
• Tempus flow can reduce the signoff scenario and perform an accurate timing
analysis with reasonable pessimism.
• This RAK uses the following flowchart to introduce how to use the Integrity 3D-IC
platform to complete STA flow :

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Module 1: Stack STA Analysis (Hierarchy Mode)

Before running the STA flow, you should have completed system planning and die
implementation. For System Planning part, tool support TCL based commands, also
support 3DBlox language import, for more details about 3Dblox™ introduction please
refer to the RAK ” 3D RISC-V System Planning with 3Dblox™ Language Using Integrity
3D-IC Platform”.

Note: This lab was developed with Integrity 3D-IC build 23.12 and Tempus build 22.14-
s061_1. Make sure that the tool version is set up before you start the following steps.
It can be set with the following command:
Linux> source setup.csh

The whole STA flow can be automatically run in batch mode through the control of a
Makefile, as shown here:

Linux> make demo_bm

The whole STA flow also can be automatically run in CUI batch mode through the
control of a Makefile, as shown here:

Linux> make STYLUS=1 demo_bm

The interactive steps are shown in each step.

This RAK requires the following scripts to execute. You can find all required scripts in
./script like follows:

./script/conver_top.tcl
./script/demo_bm.tcl

Step 1: Create Spef and MMMC files.

Read data for pnr_routed and extract RC, and then create spef/mmmc.

setMultiCpuUsage -localCpu 8

set_module_model -default_dir ./DBS

set init_mmmc_file input_data/3d_efs_init/viewDefinition.tcl

restore_module_model riscv_top -type pre_pnr -tag oio2inn

set_module_model -cell top_die -tag pnr_routed -type lef -\

allow_port_mismatch

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

set_module_model -cell bottom_die -tag pnr_routed -type lef -\

allow_port_mismatch

commit_module_model

updateStatus -force designIsRouted

extractRC

set ::enc_save_binary 0

create_module_model -tag pnr_routed -type {spef mmmc pnr}

Step 2: Launch Tempus.

You can launch 3D-IC STA flow by entering tempus

Note: This lab was developed with Integrity 3D-IC build 23.12 and Tempus build 22.14-
s061_1.

Linux> tempus

Step 3: Enable analysis in Tempus.

To enable the analysis, the following settings are needed at the beginning of Tempus.

setMultiCpuUsage -localCpu 8

set load_netlist_ignore_undefined_cell 1

set timing_enable_model_rcdb_flow 1

Step 4: Bring up die database in Tempus.

For the die database, you query the boundary_model and mmmc files (as signoff
scenarios). To bring up the complete 3D-IC database, you can continue to run the
following iHDB commands in Tempus:

set_module_model -default_dir ./DBS

set_module_mode -top riscv_top -tag pnr_routed -add_ons {mmmc

spef} -logical_only

set_module_model -cell top_die -tag pnr_routed -type

boundary_model

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

set_module_model -cell bottom_die -tag pnr_routed -type

boundary_model

commit_module_model

Note: The riscv_top SPEF file is required for this flow. This SPEF file is generated in
convert_top.tcl. You can find the SPEF file in ./DBS/riscv_top/pnr_routed/spef.

Step 5: Start to perform analysis.

Specify the constraint and report timing.

setDelayCalMode -signoff_alignment_settings true

setAnalysisMode -analysisType onChipVariation

set_interactive_constraint_modes [all_constraint_modes ]

set_propagated_clock [all_clocks]

report_timing

Step 6: View the report.

The timing report appears in the scrolling.

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Module 2: Stack STA Analysis (Flatten Mode)

Before running the STA flow, you should have completed system planning and die
implementation. For System Planning part, tool support TCL based commands, also
support 3DBlox language import, for more details about 3Dblox™ introduction please
refer to the RAK ” 3D RISC-V System Planning with 3Dblox™ Language Using Integrity
3D-IC Platform”.

Note: This lab was developed with Integrity 3D-IC build 23.12 and Tempus build 22.14-
s061_1. Make sure the tool version is set up before you start the following steps.
It can be set with the following command:
Linux> source setup.csh

Whole STA flow can be automatically run in batch mode through the control of a
Makefile, as shown here:

Linux> make demo_sta

Whole STA flow also can be automatically run in CUI batch mode through the control of
a Makefile, as shown here:

Linux> make STYLUS=1 demo_sta

The interactive steps are shown in each step.

Step 1: Launch Integrity 3D-IC.
You can launch Integrity 3D-IC by entering integrity_3dic:

Linux> integrity_3dic

Step 2: Enable analysis in Integrity 3D-IC.

To enable the analysis, the following settings are needed at the beginning.

setMultiCpuUsage -localCpu 16

set ::ilmg_module_model_use_physical_dual_view 1

set load_netlist_ignore_undefined_cell 1

Step 3: Bring up die database in Integrity 3D-IC.

To bring up the complete 3D-IC database, you can continue to run the following iHDB
commands in Integrity 3D-IC.
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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

set_module_model -default_dir ./DBS

set init_mmmc_file input_data/3d_efs_init/viewDefinition.tcl

set init_lef_file input_data/libs/lef/gsclib045.lef

restore_module_model riscv_top -type pre_pnr -tag oio2inn

partition {top_die bottom_die}

deletePartition {top_die bottom_die} -update_ptn_lef

updateStatus -force designIsRouted

extractRC

set_module_model -cell top_die -tag pnr_routed -add_ons {spef} -

phys_hier

set_module_model -cell bottom_die -tag pnr_routed -add_ons

{spef} -phys_hier

commit_module_model

Step 4: Start to perform analysis.

Specify the constraint and report timing.

setAnalysisMode -clockPropagation forcedIdeal

win

report_timing -gui -max_paths 10

report_timing

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Step 5: View the report.

The timing report appears in the scrolling.

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 3D RISC-V STA Flow Using Integrity 3D-IC Platform

Support
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an extensive knowledge base, access to software updates for Cadence products, and
the ability to interact with Cadence Customer Support. Visit
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Feedback
Email comments, questions, and suggestions to [email protected].

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