EE477L MOS VLSI Circuit Design - Spring 2025

Lab 2
TAs: Tony Huang, Xiao Tuo, and Haodi Hu
Due on February 19, 2025 11:59 pm

General Note
1. This assignment is based on individual work. No collaboration is allowed.
2. The design you did in this lab will be used as part of your final project. If you aim for the top team for
winning the bonus points, be sure to optimize your design with regards to area, delay, power, etc.
3. You are expected to submit a pdf as your lab report, which includes screenshots and any explanatory text
you find necessary. Notice that lab reports with other formats will not be graded.
4. You don’t need to submit any source file unless specifically stated.

5. Submit the pdf report to DEN course web page

6. Ask your questions ONLY in Piazza or use office hours. Do NOT send emails asking technical questions.
7. The logic functions are realized with static CMOS logic. No other implementation will be accepted, e.g.,
pass transistor logic.

8. (Suggestion) For routing M2, M4 , . . ., draw the metallic tracks in the direction parallel to the ground and
power rails.
9. (Suggestion) For routing M3, M5 , . . ., draw the metallic tracks in the direction perpendicular to the ground
and power rails.

Submission Guideline
1. Report should be named as LAB2 FirstnameLastname USCID.pdf. For example,
LAB2 TommyTrojan 1234567890.pdf.

2. In the report, include all required screenshots and make sure your every screenshot shows your username.
Include any text you find necessary for helping graders to grade your report. The following figure demonstrates
an example.

3. Only the last submission will be graded.

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1 Introduction
In this lab, we will design the schematic and layout of different static CMOS logic gates to achieve higher driving
strengths. In the last lab, we balanced the worst-case delay path in two respects:
1. equalize the approximate pull-up and -down resistance
2. match the approximate output resistance to the baseline inverter, i.e., the balanced-delay inverter with minimal
size

2 Design of Multiple Gates

In the first lab, we designed logic gates with balanced delays and minimal sizes. Although the logic gates should
work no matter whether the load capacitance is small or large, the speed could depend mainly on the load if the
loading capacitance is much larger than its intrinsic output capacitance. To address this problem, we can scale
up the widths of all driving transistors while keeping the minimum lengths. Doing so effectively reduces the on-
resistance. For instance, if the widths of a balanced gate double, then the on-resistance becomes half. Note that
the output capacitance also doubles, so the resulting delays usually drop by less than 50 percent. For light or small
loads, gates with high driving strength might not increase speed but bring in more leakage current. Optimization
of delays needs careful calculation.
In this lab, we will create higher driving strength versions of a few logic gates we have designed. We will also
design static-CMOS XOR gates of various driving strengths.

2.1 NOT Gates

By doubling the widths of all the transistors of the NOT 1X we made in Lab 1, we get a new inverter, NOT 2X, with
half on-resistance. In this section, we will also NOT 4X that has an on-resistance a quarter of the NOT 1X’s. Figure 1
depicts the schematic circuit, and table 1 tabulate the transistor sizes.

VDD

PA

A A
NA PA
NA NOT 2X 240 nm 480 nm
NOT 4X 480 nm 960 nm

Table 1: Transistor widths of NOT 2X

Figure 1: NOT gates and NOT 4X

2.2 NAND Gates

In this section, you need to design two NAND gates with two different driving strengths. The schematic circuit is
provided in fig. 2. The transistor widths are tabulated in table 2.
In the report, you have to verify its functionality by testing all possible input combinations. To conduct a
propagation delay measurement, you have to toggle only one of the inputs and measure the time difference between
50% input level and 50% output level. To perform a complete measurement, you have to test all possible single-
input-toggle transitions that result in specific output transition. You should also tabulate the delays in a table.
Moreover, you have to point out the worst delay. Take the measurement of propagation delay of rising output as an
example. The possible input transitions are (A, B) = (1, 1) → (A, B) = (0, 1) and (A, B) = (1, 1) → (A, B) = (1, 0).

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 VDD VDD

A PA PB B

A·B

A NA

B NB NA NB PA PB
NAND 2X 480 nm 480 nm 480 nm 480 nm
NAND 4X 960 nm 960 nm 960 nm 960 nm

Figure 2: NAND gates Table 2: Transistor widths of NAND 2X and NAND 4X

2.3 NOR Gates

Figure 3 shows the transistor-level NOR logic. Let the minimum-size balanced NOR be NOR 1X. The variants that
double and quadruple the driving strengths are NOR 2X and NOR 2X. Their transistor sizes are listed in table 3.

VDD

B PB

A PA

A+B

A NA NB B NA NB PA PB
NOR 2X 240 nm 240 nm 960 nm 960 nm
NOR 4X 480 nm 480 nm 1920 nm 1920 nm

Figure 3: NOR gates Table 3: Transistor widths of NOR 2X and NOR 4X

In the report, you can verify its functionality by testing it with the same input patterns as you do for the NAND
gates. To perform a complete propagation delay measurement, you have to test all possible single-input-toggle
transitions that result in specific output transition. You should also tabulate the delays in a table. Moreover, you
have to point out the worst delay. Take the measurement of propagation delay of rising output as an example. The
possible input transitions are (A, B) = (0, 1) → (A, B) = (0, 0) and (A, B) = (1, 0) → (A, B) = (0, 0).

3 Design of XOR Gates

A two-input exclusive-OR (XOR) gate compares the inputs and produces logic 1 if they are different. The formal
expression for a two-input XOR is XOR(A, B) = A ⊕ B = AB + AB If we take the complemented result, we
get another gate, exclusive-NOR (XNOR). XNOR gates give logic one if its inputs are the same. The two-input
expression is XN OR(A, B) = AB + ĀB̄. In this section, we will design XOR gates with three different driving
strengths.
To implement this XOR, we need input complements. They can be generated with inverters. In this lab, you
have to use balanced-delay inverters (that you designed in Lab 1) to generate complemented inputs.

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 First, we need to design an XOR gate with balanced delays and minimal size. In Lab 1, we know that the
mobility ratio ( µµnp ) of this fabrication technology is around 2. Based on this result, we can size all the transistors.
Here, an alternative way to realize an XOR gate is offered. It enables the removal of contacts at some non-output
internal nodes, hence lower parasitic capacitance. Observing A ⊕ B = AB + AB, we learn that when A = 1, the
outcome is B, and when A = 0, the outcome is B. According to this observation, we can derive two VDD-to-ground
branches to implement an XOR gate, as shown in fig. 4. The left branch realizes the case when A = 1, whereas the
right represents the case when A = 0.
Next, we need to design two XOR gates with double and quadruple driving strengths (XOR 2X and XOR 4X),
respectively. To minimize the area, we can implement them with an XNOR gate followed by an inverter. It can be
understood from the fact that XOR(A, B) = XN OR(A, B). Since the gate drives its load with an inverter, we can
adjust its driving strength by changing its output stage’s driving strengths. Figure 5 shows the schematic circuit of
XOR 2X and XOR 4X. Although XOR 1X can be designed this way, it is not preferable because an additional inverter
takes more area, increases the delay, and introduces more leakage.
The sizes of transistors of XOR 1X XOR 2X and XOR 4X cells are tabulated in table 4.

VDD VDD VDD

PA0 B PB1 PA2 A

A
A
VDD NA0 A PA1 PB2 B

Output
PB0 A NA1 NB2 B
B
B

NB0 B NB1 NA2 A

Figure 4: XOR gate: XOR 1X

NA1 NB1 NA2 NB1 PA1 PB1 PA2 PB2

XOR 1X 240 240 240 240 480 480 480 480
XOR 2X 240 240 240 240 480 480 480 480
XOR 4X 240 240 240 240 480 480 480 480
NA0 NB0 PA0 PB0 NC PC
XOR 1X 120 120 240 240 N/A N/A
XOR 2X 120 120 240 240 240 480
XOR 4X 120 120 240 240 480 960

Table 4: Transistor widths of XOR 1X, XOR 2X, and XOR 4X (unit: nm)

In the report, you can verify its functionality by testing it with the same input patterns as you do for the
NAND or NOR gates. To perform a complete propagation delay measurement, you have to test all possible input
transitions that result in specific output state transitions. A valid input transition means toggling one of the inputs
at a time. You should also tabulate the delays in a table. Moreover, you have to point out the worst delay. Take
the measurement of propagation delay of rising output as an example. the possible input transitions are tabulated
in table 5.

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 VDD VDD VDD

PA0 B PB1 PA2 A VDD

A
A
VDD NA0 A PA1 PB2 B PC

Output
PB0 A NA1 NB2 B NC
B
B

NB0 B NB1 NA2 A

Figure 5: XOR gates: XOR 2X and XOR 4X

Current (A,B) (0,0) (0,0) (1,1) (1,1)

Next (A,B) (0,1) (1,0) (0,1) (1,0)

Table 5: Rising output due to single-input-toggle transition

4 Report Checklist
1. Schematic of all the gates (NOT 2X, NOT 4X, NAND 2X, NAND 4X, NOR 2X, NOR 4X, XOR 1X, XOR 2X, XOR 4X)

2. Layout of all the gates

3. Symbols of all the gates
4. Screenshots of DRC results for all the gates
5. Screenshots of LVS results for all the gates

6. Functionality verification by plotting input and output waveforms for all the gates with FO4 testbench and
extracted views
7. A Table listing propagation delays for rising and falling outputs for all the gates with FO4 testbench and
extracted views

8. Highlight the highest rising and falling propagation delays for each gate