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The document provides a detailed overview of a 16-bit microprocessor architecture, including its memory access capabilities, pin configurations, and operational modes. It describes the multiplexing of address and data lines, the function of various control signals, and the internal structure of the processor, including execution and bus interface units. Additionally, it outlines the types of registers used within the processor, such as general-purpose and segment registers.
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0% found this document useful (0 votes)
12 viewsMIC-UNIT-01
The document provides a detailed overview of a 16-bit microprocessor architecture, including its memory access capabilities, pin configurations, and operational modes. It describes the multiplexing of address and data lines, the function of various control signals, and the internal structure of the processor, including execution and bus interface units. Additionally, it outlines the types of registers used within the processor, such as general-purpose and segment registers.
Uploaded by
pravindsawateCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 16
feabuvtl o4 2086 _Miceapypce ner.
© ck iz 16 bik mloveprocessor
@® cr has Do addvess Uneg and 14 data Lines
© addvess and data Unes are multiplexed. Cae ADs)
@ Memory accessing capacity te upto LMS (2 #L™ms)
© cr can aceecs 644% on F/o Parks.
© opevaring clock prequencies ave SMHY SMH Lo MHF.
@ Fe can operates fn single processoy mede ( minfmun3)
and _mullkprecetroy Cyanimum mode),
© CF vequivés single phace doe with 33y, duty eyde .
@ GF provides 256 typed og _vechoved coptwane Tohnrupte pin Diagram, op S086 bs nary Mig
SEN tte
qu 7 —40-faVee— 7 z
AME : A
“Ape ys" + se eft :
re at :
——* a
“| . = : ‘ - I
* il ‘
Geuerstch
Ap, cg " om ! :
Ady 4g 3086 er ba HO. RA a,
Ae 40-F-HLDA— oh
Abe e We Tack
toy & i
LAD 4 ae TER '
= see
ADE re 9 RSe
NMES IF ot BHT
pATR ES ES
He S— READY
Heep = ee Ex
|
Tgoa6 a 14 bit miovopvaceccoy.
This miovapracescor operates jo. ingle pracecsay (minimum
| mode): or mulprocesvor Cmaximum made) configurations |
[ene pin canPiquraen fs ag chown ip gy
“come Of Hoe pins serve a pavticulay Funcken in. minimun ~
made and others function fn manimum mede .!
> The addvess/data lines ave rhe mulliptered
~~ addvecs bus and data lus used for
transmission of) addvece bits and data bit,
16 bik data Cvo-Yic) fe .cavvied acevacs
lL 4 > data Lines, fe :
6 bit. addvess. C Ao-A1¢)) 1 Garvied acevacs
addvece Wes.
1 | ADo~ APIs Addvecs bits and data bits ave ve separated by
using ALE signal.
Atg/se - Au [ss > The addvescfetatus. Tes ave
mulkplexed to provide, Gavi, addvede bits and
status bits, The addvese lines Gig ~A16) and status
nes CSe- Ss) ave sepavated ey ustoge ALE signal .
the statis bits og ic always at Logid 0.
the statue Une Se jndivi rhe Cobdikien of the
Interrupt . !
the stodue Unes S4-Se indicate: tel ctatus of
mievepracestoy conneoed to any. © ent.
S4-S_- UNes indicates which ‘ceqmn ent vegister ic
presently being wed toy Memany. GOoeCs .
Addrece bits ave pyuenk on addvess tines during, T,
Clock cycle. and ctakus bite are pvétent aluvfng,
Ts, Ts -and-N, dod. cycle, . f
Be fq £3 Seqment vegister.
o o ES ame
o L cS k ;
£ ‘oO cs ov None
£ i DS |
te
BuE/ Sz C eur Hiqh ¢ Enable and CReod) - ct is active’ tow signal. tt ic used to
vead dota byte from memory localion ov £/0 perks.
Fhe Signal remain ‘ristaed diving: hald acknowledge’
READY =S Tis ix pal ere signal qvom rrslow memory,
ov t/o ports. the signal is athve high. ch t< acknowledgement
signal cent by memery ey peripherals to tne mievoprececsor
that they ave ready to Lecelve dolla .
2a : 5
INTR - Totevvupt vequest > ©
= ct ie fotewrupt vequest sent by peripherals.
= ct i achive high, level dviqgered inpub signal .
— This 4% sampled duving last clock eye op eacl
instrudion to determine tne evenly Op Therap
requetty
=sfew any Inferrupt véquect iq occuved the praceevor
entere the inhewupt atknewledge cycle.
NME. (NON madkable Enhervupk =.
— Ft ia This Is edge-tyiggeved Mput totervupt nrequact
vohidh Cauces a Type 2 fptevrupt.
— The HME ig nok Maskable, internally. by. Cohtuiawe.
TEST =s- This Is input signal examined by. SWART’
incbyucton
— This i¢ adive low input signal.
- of hic signal qoe low eneculion will
continue, ce the processor vemains in an
dle ctate. reseT > Creceb) | a
= ght achive high Input signal.
vin) When. this signal goes high, the processor enhey
he hho, veter stake and terminate the cuvvent
adivity. and ctavk emecution From FPPPOH .
TPeve = doek inpuk ss
c= Tis te Inpuk signal.
yim This chook signal provider the basic Tninq for
proceccoy opeyalan and bus control activity.
aah ies aeeymmebrte Tent aakgevcladgervent
| Bt ie gelive low outpuk signal.
= Be atknowledgment signal generated b
micwoprocessoy bo fntew= in vetponce to inkerrupt
| srequeck cinalee
ALE > Addyvecs latch enable
~ st te achive: high signal .
= ‘Thic output signal indicates +e owailalitiey. 6 oy te,
valid addvece on addvecs Lines,
= hts cignok te Cennesiedtn enable pir ep-latehads .
= tole signal tc connected to ladch enable inpuboy ladcher
|oT/R => atu Pransall fegrave ;
> Mie output : ry
= This saclve low oukpu signal.
=) Tt ie eontral signal genewated by processor to
write data byte to memory. tacation on oulput porte.
Holp'- Héld >
~ tt ie gelive high input signal:
~ Fp This signal goes high C1) indfoaber that anoher
macter i£ requesHng the’ bus access.
> hen cinother mackey dewite needs He Use Of the
addvess , data and: contre bus it sende q Holo
vequect to +e procecrey through tit Une,
Hio# — Hold accnowledgement
= fh te achve high oufpub signal .- i
= ft ic acknowledgement signal gqenemabed by
precescoy on veeeving Horp svrequeck ,
QS) QSq_ ~ Queue ttatup => t
The Queue status pins provider the mformalfen
about the statuc op the inchwdtn queue.
AS; Ako Thdicalion.
i} o NO opevalon
10 4 Fivct bute op optode from quate .
t ° Empty, queue.
L L
sSulecequent byte prom gute. ®
peso > cbatup Fignal 7
— Mele ctotug signal indicahes the 1 OT operation
being cavvied ou Ly the ene
- These signals beeome acHve during. T4. op previous
cycle and vemain adive duwing. Ty_a0d Te on wrrent ade,
~ the status Unet ave encoded vdow.
Code accece
Read Memory,
write memory
So. ©) Sp Endication
o oO 0 Entevrupt acmovledge,
go of Read S/o port
o t+ 0 write C/o poxt
o tt Holt
nO MetO
Loo8
emer eT)
4 4+ +
passive
Lock => loc
= Thic owput signal indicates thak omer cyckem bys
master will] be prevented trom gaining. the sytkm
foul .
= The hoo Lock prepin inshrueHon adivates Leck
gignal and vemains achve unkl tne completion op
the neat instruction.
RR/ Go Ral ar, => C Requett/ qrant )
~ Thee pine are used by other lowal but macter
Fp maatmum mode to force the proceeror to
velease the Loa! lus at he end ¢y the procescars
eurvenrk louc eyde, if
= Thee ping ave bidivectional wits Re] hawing
higher prvi ovity. than Ra/ GT;
= Apter receiving. request 69 Hhere Lines , the UpU
sends aun owledqm ent Signal on same Line, x
ariteduve oy F0S6. - 7
[__|the go26 cpu id divided nto turo independent __
functional park
O_Bus_fotevtace unit C EU)
@_execulon unir ( EY)
-The execution unit ene he “BTU wheve to Fetch
Instructions ov data.
- the enecukon unit Fezade the frstrycton and
enuecules the instructions.
= the enecuton unit contains Conrrol civeuteny whreb
aonkrels. inkermad operations .
= A deteder in EU tronclates raatraiong into
Sevieg of achons.:~
- Eu has ALU Whith pentorrms aritymahe aod )ogia
operations . | + ene=main fundions oy EU ove jie a
1+ O-pecoding op instructions \
; @® Enecution op Petre thio i a
us iptertace unit Cerud Ct
Tee BrU Sends addvess op inebrucions
~_ ft #ttehec inctrudiond gram memory.
- th vead dota prom memory and, porbe
tft _Wwritet_data_to_memory and porte . i
_ N= fn simple words the BRU handles all tans peer ay
_ datw and addvecses 60 the buses for encculfeo Unit,
Avchitedive oy 2086 Microprocessor has differen
tuyper_op_reglttens. a :
© General purpace_Regictenrc : :
© seqpek Registers . * *
@ -Endex and pointer Registers. i
| @ Ang Regicter, 7
@ eeneval purpoce regicters
= Theve ave four general purpose vegicters fn fogs
= they ave Accumulater, Bare vegitter, counter regitterr
and data vedgicter.
Acuumulatey CA’) => t
tor te 146 bit vegicter. :
ft id uced to stove ene 16 bits 1) data. 1
+ St ie used to stove one data operand in any arithmaie
Gnd legit opevatenc . the vesuit op arinmane er Lge _
spevaton he again
“a tt ig 16 bit wegister used to store 14 bits of
‘| general daly ; \ i
= Trig used ac counter register in.ctring. and loop
instyucHons.
— BR & te on vepshor we divid
- The tower 3 bik op bn cvegister i designated as CL
and higher @ bits t deciqnaked ac oH.
ox Tou lie
egisher (10 ie 7 ;
Tae te 12 bit vegistes used to store 16 bits of general data,
TH ig used ag an imphiat opevand or ‘desHnalon .
T_the lower & bite 69 Px vegister i< designated ag DL
and higher ¢ bits i decignaked as DH.
DH. OL
oa |
os Pape Po
Gece
GRE aves Hts Caqwram Fepscens
ol aj
segment Regittens- >> Segment veqictenc ave used to
stove ceqment address Or bare address op wespechve
seqmentt .
theve four < t_vegistems .
i) Code cegment regicter Cos)
Hi) sctaek reement ee CSD
Ti) pata segment vegicter CPs)
iv) _Eatya segment register CES) D code ceqment Reqicler = fh ls [4 bit register,
St fs used to stove the segment address or. bace
addvess ey code cegment.”
schac, segment Regicter=s et te 16 bit register.
st ke Used to stove the add: ceqmenr address or
loa address oy stack seqmen’,
Bxdwa Data Segment vegistey = gt k 16 bit egiler,
Cris Used to “tore the segment addvess or bace
raddress: oy data “eqment.
Excya ceqment rvegkter => chic 16 bit reaicter.
ft & Used to Stove the
Cipstrucions Felehed From memory are stored fo
instuden queue register
L enckraditve.qretye rogictor fb
tthe lengkh of incbucHon quede veqistem te 6 byhe
So Six loyhes op) fashuchons ean be shoved Mn gee
inshrucion queue vegister,
Lopstruchons are stored in FIFO ESSE Tn Fick
our’) manner.
I-rhen instructions ave given to dezoding, and ~~~
Anecuking, :
= whi Fetching a insbudhon is fo paraiied with
emecuhOn Gpevmahe” thak Mnerease Gb peed oF enecubion Ww
IE seg eer used ty show the chetus of
yeculh loy. setting ar veseting SI ingle bit.
Frlag vegictor on 8086 i« divided foto tuo part ~
Te ehatus Hag and machine conire) Plag,
status flags shows the status op vesulh
Maaline bn}ro) Flags are used to contro] Some
operahons, ¢
- the lower byte oUF 6p 16 bits are on Alag aregpsheg
ig Status Hagrand higher loyte is machine Contra
L he diphew & Ftags.
ys el as se ae go 8 8H KH US HU US 8 Ut
Toe De [oe Ter Terre Seer ee] xT Te [eT
OF - OvesFHEW wag.
DF- wivecHonal Hag.
TR- Cntevrupt Hag.
TRA “Trap Fag.”
cf = sign Hag.
Ar ~ zero Hap.
AC - Ausillianu, Cawy Fag,
p= pawity Fag, 9%
oy - COW Ag.
S-sigo Bag — This flag. [< Sek when the ‘vesulF 4p
_____[ any _compulaon ic “negative . for Signed computahion_
thé_sign Flag equafe the MsB oy He yecult.
Z- Zeve Hag — Thit Pag ie cot ip vesulFop
computaion 34 Zero .\orherwise thie Play remain fo
etek Condition.
-AUoui Tian Cary, Age — :
is Prag wil Tof< partly ping, will Sek iy veculk ¢
aa Lanyartbmatic_ov Logical eperalion eonsic Oy even
+ orherwiee fk will) remain tn yecek
number dy ‘one's
Lesaditien.
cowry Fra — Dy Carry ik generated fn arithmalhe
and lb épevatien hen “this “carry #/aq_vsii) ef,
Onerwise “it wil) remain fn vecel cdaditian.
_Levevtio™ Plage, — Thit Flag Sels When ovtr4laW
gccuver, on “vecuit op
