®

RT3613EE

Multi-Phase PWM Controller for CPU Core Power Supply

General Description Features
The RT3613EE is a 3/2/1 multi-phase synchronous buck  Intel IMVP9 Serial VID Interface Compatible Power
controller designed to meet Intel IMVP9 compatible CPU Management States
specification with a serial VID control interface. The  3/2/1 Phase PWM Controller
RT3613EE adopts G-NAVPTM (Green Native AVP) which  G-NAVP TM (Green Native Adaptive Voltage
is Richtek's proprietary topology derived from finite DC Positioning) Topology
gain of EA amplifier with current mode control, making it  0.5% DAC Accuracy
easy to set the droop to meet all Intel CPU requirements  Differential Remote Voltage Sensing
of AVP (Adaptive Voltage Positioning). Based on the G-  Built-in ADC for Platform Programming and
NAVP TM topology, the RT3613EE features a new Reporting
generation of quick response mechanism (Adaptive Quick  Accurate Current Balance
Response, AQR) to optimize AVP performance during load  System Thermal Compensated AVP
transient and reduce output capacitors. The RT3613EE  Diode Emulation Mode at Light Load Condition
supports mode transition function with various operating  Fast Transient Response-Adaptive Quick Response
states. A serial VID (SVID) interface is built in the (AQR)
RT3613EE to communicate with Intel IMVP9 compliant  VR Ready Indicator
CPU. The RT3613EE supports VID on-the-fly function with  Thermal Monitoring and Indicator
three different slew rates: Fast, Slow and Decay. By  Current Monitoring
utilizing the G-NAVPTM topology, the operating frequency  IMVP9 System Input Power Monitoring
of the RT3613EE varies with VID, load and input voltage  OVP, OCP, UVLO, UVP
to further enhance the efficiency even in CCM. Moreover,  Multi-Vendor Dr.MOS
the G-NAVPTM with CCRCOT (Constant Current Ripple  Switching Frequency Range Setting
COT) technology provides superior output voltage ripple  Slew Rate Setting
over the entire input/output range. The built-in high accuracy  DVID Enhancement
DAC converts the SVID code ranging from 0V to 2.74V  Acoustic Noise Suppression
with 10mV per step. The RT3613EE integrates a high  Small 32-Lead WQFN Package
accuracy ADC for platform and function settings, such as
ICCMAX, switching frequency, over-current threshold and Applications
AQR trigger level. The RT3613EE provides VR Ready and  IMVP9 Intel Core Supply
thermal indicators. It also features complete fault  Notebook Computer Multi-Phase CPU Core Supply
protection functions including over-voltage (OV), under-  AVP Step-Down Converter
voltage (UV), over-current (OC) and under-voltage lockout
(UVLO).

Simplified Application Circuit

RT3613EE
To PCH VR_READY RT3613EE
PWM1 RT9610C MOSFET To PCH VR_READY
VR_HOT# PWM1 Dr.MOS

PWM2 RT9610C MOSFET VCORE VR_HOT#

VCLK Dr.MOS
To CPU PWM2 VCORE
VCLK
VDIO PWM3 RT9610C MOSFET To CPU
VDIO PWM3 Dr.MOS
ALERT#
To Driver DRVEN ALERT#
To Dr.MOS DRVEN

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

1
RT3613EE
Ordering Information Pin Configuration
RT3613EE (TOP VIEW)

ANS_EN

VREF06
Package Type

COMP

RGND
VSEN

IMON
QW : WQFN-32L 4x4 (W-Type)

NC
FB
Lead Plating System 32 31 30 29 28 27 26 25

ISEN2P 1 24 VCC
G : Green (Halogen Free and Pb Free) ISEN2N 2 23 PSYS
ISEN1N 3 22 SET1
ISEN1P 4
GND
21 SET2
Note : ISEN3P 5 20 SET3
ISEN3N 6 19 VCLK
Richtek products are : TSEN 7
33
18 VDIO
 RoHS compliant and compatible with the current require- VIN 8 17 ALERT#
9 10 11 12 13 14 15 16
ments of IPC/JEDEC J-STD-020.

VR_READY
PWM3
PWM1
VRON

NC
DRVEN
PWM2

VR_HOT#
 Suitable for use in SnPb or Pb-free soldering processes.

Marking Information WQFN-32L 4x4

8D= : Product Code
8D=YM YMDNN : Date Code
DNN

Functional Pin Description

Pin No. Pin Name Pin Function
4, 1, 5 ISEN [1:3] P Positive inputs of current-sense amplifier of channel 1, 2 and 3.
3, 2, 6 ISEN [1:3] N Negative inputs of current-sense amplifier of channel 1, 2 and 3.
Thermal sense input and function settings for advanced ramp magnitude in
7 TSEN PS1, advanced ramp magnitude in PS0, zero loadline enable and DVID voltage
compesation.
Input voltage pin. Connect an RC filter whose time constant need less than
8 VIN
switch period for sensing input voltage.
9 VRON Controller enable pin. A logic high signal enables the controller.
10 VR_READY VR ready indicator.
12, 13, 11 PWM [1:3] PWM outputs for channel 1, 2 and 3.
14, 32 NC No internal connection.
External driver (discrete power MOSFET driver or Dr.MOS) mode control. For
15 DRVEN discrete power MOSFET driver application, connecting 100kΩ resistor to GND
is required.
16 VR_HOT# Thermal monitor output. (Active low).
17 ALERT# SVID alert. (Active low)
18 VDIO VR and CPU data transmission interface.
19 VCLK Synchronous clock from the CPU.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

2
 RT3613EE
Pin No. Pin Name Pin Function
Function settings for loop response speed-up adaptiv quick response(AQR)
20 SET3 trigger level, zero current detection, sum OCP ratio and undershoot
suppression.
Function settings for anti-overshoot trigger level, current gain (Ai), DVID fast
21 SET2 slew rate, acoustic noise suppression and high frequency ACLL voltage
compensation in PS1.
Function settings for ICCMAX, TON width setting (switching frequency) and
22 SET1 VBOOT. Connect the SET1 pin to 5V and turn on the VRON pin, if the soldering
is good, the output voltage is 1.8V.
System input power monitor. Place the PSYS resistor as close to the IC as
23 PSYS
possible.
Controller power supply. Connect this pin to 5V and place an RC filter, R = 6.2
24 VCC and C = 4.7μF. The decoupling capacitor should be as close as physically
possible to the VCC pin.
Current monitor output for controller. This pin outputs a voltage proportional to
25 IMON
the output current.
Voltage source output. During controller internal setting period, it outputs 3.2V.
In normal operation, it outputs 0.6V to offset IMON signal. While controller shuts
26 VREF06
down or in PS4, voltage source shuts down. An exact 0.47uF capacitor and
3.9Ω resistor from this pin to GND are required for stability.
Return ground. This pin is the negative input of output voltage differential
27 RGND
remote sense.
Voltage sense input. This pin is connected to the terminal of controller output
28 VSEN
voltage.
29 COMP Error amplifier output pin.
Negative input of the error amplifier. This pin is for output voltage feedback to
30 FB
controller.
Acoustic noise suppression function setting. When pulling to VCC, this function
31 ANS_EN
can be enabled. This pin is not allowed to be floating.
33 Ground. The exposed pad must be soldered to a large PCB and connected to
GND
(Exposed Pad) GND with enough VIA numbers for maximum power dissipation.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

3
RT3613EE
Functional Block Diagram

VR_READY
VR_HOT#

ANS_EN
ALERT#

VRON
VSEN
TSEN
PSYS

VCLK
SET1

SET2

SET3

VDIO

VCC
IMONAVG

UVLO GND
MUX

ADC
SVID Interface
Configuration Registers
Control Logic PIN Function Loop Control/
Setting Code Protection Logic
DRVEN

FLRAMP_PS0[1:0] Ring-back
Control VIN
FLRAMP_PS1
RGND DAC
ERROR
VID AMP PWM
+ Offset + CMP
FB Cancellation + PWM1
- TON
+ -
ZCDx GEN/
COMP PWM2
HFACLL_LIFT_PS1[1:0] VCBx Driver
ISEN1P TONSET[3:0] Interface PWM3
+ Gm
ISEN1N - IIMON1
+
ICB1
IZD1 - UDS[2:0]
IOC1 RAMP
Ai[1:0]
ISEN2P + Gm
ISEN2N - IIMON2
ICB2
IZD2
IOC2 VSEN
AQR_TH[2:0] AQR/
ISEN3P + Gm ANTIOVS
ISEN3N ANTIOVS_TH[2:0] To TONGEN
- IIMON3
ZCDx
ICB3
IZD3 VSEN OVP/
IOC3 IMON IOCx UVP/
IMONAVG To Protection Logic
Filter IMON OCP
PER CSGM
Current
ICBx VCBx
+ Balance
- 0.6V/3.2V
Zero
IZDx Current ZCDx
ZCD_TH[1:0] Detection

IMON VREF06

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

4
 RT3613EE
Operation
G-NAVPTM Control Mode SVID Interface/Control Logic/Configuration
TM
The RT3613EE adopts G-NAVP (Green Native AVP) Registers
which is Richtek's proprietary topology. It is derived from SVID Interface receives or transmits SVID signal with CPU.
current mode constant on-time control with finite DC gain Control Logic executes command (Read/Write registers,
of error amplifier and DC offset cancellation. The topology setVID, setPS) and sends related signals to control VR.
can achieve easy loadline design and provide high DC Configuration Registers include function setting registers
accuracy and fast transient response. When sensed and CPU required registers.
current signal reaches sensed voltage signal, the
RT3613EE generates a PWM pulse to achieve loop IMON Filter
modulation. Figure 1 shows the basic G-NAVPTM behavior IMON Filter is used to average current signal by analog
waveforms. The COMP signal is the sensed voltage, that low-pass filter. It outputs IMONAVG to the MUX of ADC for
is inverted and amplified signal of output voltage. While current reporting.
current loading is increasing, referring to Figure 1, COMP
rises due to output voltage droop. Then rising COMP MUX and ADC
forces PWM turn on earlier and closely. While inductor The MUX supports the inputs of SET1, SET2, SET3,
current reaches loading current, COMP enters another TSEN, PSYS and IMONAVG. The ADC converts these
steady state of higher voltage and corresponding output analog signals to digital codes for reporting or function
voltage is in the steady state of lower voltage. The loadline, settings.
output voltage dropping by an amount proportional to
loading current, is achieved.

Steady State Load Transient

Loading Current ΔIcc

VOUT

VID

ΔIcc x RLL

Sensed Current Signal

COMP

PWM

Figure 1. G-NAVPTM Behavior Waveform

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

5
RT3613EE
UVLO Current Balance
Detects the VCC voltage. As VCC overs threshod, Per-phase current sense signal is compared with sensed
controller issues POR = high and waits VRON. After both average current. The comparison result adjusts each phase
POR and VRON are ready, then controller is enabled. PWM width to optimize current and thermal balance.

Loop Control/Protection Logic Zero Current Detection

It controls power-on/off sequence, protections, power state Detects whether each phase current crosses zero current.
transition, and PWM sequence. The result is used for DEM power saving and overshoot
reduction (Anti-overshoot function).
DAC
Generates a reference VID voltage according to the VID AQR/ANTIOVS
code sent by Control Logic. According to setVID AQR is a new generation of quick response mechanism
command, Control Logic dynamically changes VID voltage (Adaptive Quick Response, AQR) which detects loading
to the target with required slew rate. rising edge and allows all PWM to turn on. PWM pulse
width triggered by AQR is adaptive to loading level. AQR
ERROR AMP trigger level can be set by PIN-SETTING. ANTIOVS can
Inverts and amplifies the difference between output voltage help overshoot reduction which detects loading falling edge
and VID with externally set finite DC gain. The output signal and forces all PWM in tri-state until the zero current is
is COMP for PWM trigger. detected.

PER CSGM TONGEN/Driver Interface

Senses per-phase inductor current. The outputs are used PWM comparator output signal triggers TONGEN to
for loop response, current balance, zero current detection, generate PWM pulse. The PWM sequence is controlled
current reporting and over-current protection. by loop control. PWM pulse width is determined by
frequency setting, current balance output and adaptive
SUM CSGM
quick response (AQR) settings. Once AQR is triggered,
Senses total inductor current with RIMON gain adjustment. VR allows all PWM to turn on at the same time. Driver
SUM CSGM output current ratio can also be set by PIN- Interface provides high/low/tri-state to drive external driver.
SETTING (Ai[1:0]). It helps wider application range of DCR In power saving mode, driver interface forces PWM in tri-
and load line. SUM CSGM output is used for PWM trigger. state to turn off high side and low side power MOSFET
according to zero current detection output. In addition,
RAMP
PWM state is controlled by protection logic. Different
RAMP helps loop stability and transient response.
protections force required PWM state.
PWM CMP
OVP/UVP/OCP
The PWM comparator compares COMP signal and sum
Over-voltage protection/Under-voltage protection/Over-
current signal based on RAMP to trigger PWM.
current protection.
Offset Cancellation
Cancel the current signal/comp voltage ripple issue to
control output voltage accuracy.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

6
 RT3613EE
Absolute Maximum Ratings (Note 1)
 VIN to GND ------------------------------------------------------------------------------------------------------------------- −0.3V to 28V
 VCC to GND ----------------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
 RGND to GND --------------------------------------------------------------------------------------------------------------- −0.3V to 0.3V
 Other Pins -------------------------------------------------------------------------------------------------------------------- −0.3V to 6.8V
 Power Dissipation, PD @ TA = 25°C
WQFN-32L 4x4 ------------------------------------------------------------------------------------------------------------- 3.59W
 Package Thermal Resistance (Note 2)
WQFN-32L 4x4, θJA -------------------------------------------------------------------------------------------------------- 27.8°C/W
WQFN-32L 4x4, θJC ------------------------------------------------------------------------------------------------------- 7°C/W
 Junction Temperature ------------------------------------------------------------------------------------------------------ 150°C
 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------- 260°C
 Storage Temperature Range --------------------------------------------------------------------------------------------- −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 VIN to GND ------------------------------------------------------------------------------------------------------------------- 4.5V to 24V
 Supply Input Voltage, VCC ----------------------------------------------------------------------------------------------- 4.5V to 5.5V
 Junction Temperature Range --------------------------------------------------------------------------------------------- −10°C to 105°C

Electrical Characteristics
(VCC = 5V, typical values are referenced to TJ = 25°C, Min and Max values are referenced to TJ from −10 °C to 105 °C, unless
other noted)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Input
Supply Voltage VCC 4.5 5 5.5 V
Supply Current IVCC VRON = H, not switching -- 6.5 -- mA
Supply Current at PS4 IVCC_PS4 VRON = H, not switching -- 0.08 0.097 mA
Shutdown Current ISHDN VRON = L -- -- 10 A
Slew Rate
Dynamic Fast Slew Rate SetVID fast 48 -- --
SR
VID Slew SetVID slow, slew rate default = 1/4 mV/s
Slow Slew Rate (Y/U/H-line) 12 -- --
Rate fast
EA Amplifier
DC Gain ADC RL = 47k 70 -- -- dB
Gain-Bandwidth Product GBW CLOAD = 5pF -- 5 -- MHz
CLOAD = 10pF (Gain = 4,
Slew Rate SREA 5 -- -- V/s
Rf = 47k, VOUT = 0.5V to 3V)
Output Voltage Range VCOMP RL = 47k 0.3 -- 3.6 V
Maximum Source/Sink
IOUTEA VCOMP = 2V -- 5 -- mA
Current
Input Offset Voltage VOSEA TA = 25°C 3 3 mV

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

7
RT3613EE
Parameter Symbol Test Conditions Min Typ Max Unit
Current Sensing Amplifier
Input Offset Voltage VOSCS 0.6 -- 0.6 mV
Impedance at Positive Input RISENxP 1 -- -- M
Differential voltage range of DCR
CS Input Voltage VCSIN sense. (VCSIN= Inductor current x 10 -- 100 mV
DCR x DCR divider)
Internal current mirror gain of per
Current Sense Gain Error AMIRROR phase current sense 0.97 1 1.03 A/A
IIMON / ICS,PERx
TON Setting
VIN = 19V,VID = 1.8V, KTON =
On-Time Setting tON -- 185 -- ns
1.36
VDAC = 1.8V under PS1
Minimum Off-Time tOFF -- 130 -- ns
condition
Protections

Under-Voltage Lockout VUVLO Falling edge 3.9 4.1 4.3 V

Threshold VUVLO Rising edge hysteresis 100 170 250 mV
Respect to VID voltage, VID > VID VID VID
Over-Voltage Protection mV
VOV 1.88V + 300 + 350 + 400
Threshold
VID  1.88V -- 2.23 -- V
Under-Voltage Protection
VUV Respect to VID voltage 760 660 550 mV
Threshold
VRON and VR_READY
Logic-High VIH 0.7 -- --
VRON Threshold V
Logic-Low VIL -- -- 0.3
Leakage Current of VRON 1 -- 1 A

VR_READY Pull Low Voltage VVR_READY IVR_READY = 10mA -- -- 0.13 V

Serial VID and VR_HOT#

Respect to INTEL Spec. with
VCLK, VDIO Logic-High VIH 0.65 -- --
50mV hysteresis V
Input Voltage
Logic-Low VIL -- -- 0.45
Leakage Current of VCLK and
ILEAK_IN 1 -- 1 A
VDIO
VVDIO IVDIO = 10mA
Pull Low Voltage VALERT# IALERT# = 10mA -- -- 0.13 V
VVR_HOT# IVR_HOT# = 10mA
Leakage Current of ALERT#,
ILEAK_OUT 1 -- 1 A
VR_HOT#,

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

8
 RT3613EE
Parameter Symbol Test Conditions Min Typ Max Unit
ANS_EN
VCC –
ANS_EN Input Logic-High VIH -- --
0.7 V
Voltage
Logic-Low VIL -- -- 1
VREF
VREF06 Voltage VVREF06 Normal operation 0.59 0.6 0.61 V
ADC
Digital IMON Set dVIMONICCMAX VIMON VVREF06 = 1.6V -- 255 -- Decimal
PSYS Maximum PSYS VPSYS = 1.6V -- 255 -- Decimal
Average Period of IMON tIMON -- 200 -- s
ADC
VR_Hot# Assert Threshold Falling -- 1.092 1.118
VR_Hot# De-Assert
Rising 1.106 1.132 1.16
Threshold
Thermal ALERT# Assert VTSEN Falling, thermal alert status1 V
1.106 1.132 1.16
Threshold register bit 1 assert
Thermal ALERT# Assert Fallng, thermal alert status1
1.148 1.176 1.207
Threshold register bit 1 de-assert
Average Period of TSEN tTSEN -- 800 -- s
ITSEN
TSEN Source Current ITSEN VTSEN = 1.6V, TA = 25°C 79.2 80 80.8 A

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

9
 RT3613EE
Typical Application Circuit
For TGL-UP3 4+2 28W Performance, ICCMAX = 69A

RT3613EE VIN
DRVEN 15
DRVEN 5V R27 C11
NC for Dr.MOS R1 VCC BOOT
C10 2.2  0.1µF C12 C13
100k Q1
1uF GND R28 22µF 22µF
R2 UGATE
24
5V VCC 0 Optional L1
6.2  C1 12
PWM1 PWM PHASE
4.7uF Q2x2 0.22µH
VREF R3 20 DRVEN EN LGATE R29 DCR=0.98m 
SET3 R30 R31 C15
RT9610C
34k C14
R4 2.55k 2.55k 0.1µF
21 SET2 R32
4 VCC_SENSE VSS_SENSE
1.78k ISEN1P
R5 3 R33 3.74k
22 ISEN1N
SET1 C16
205k R6 R7 680  R48 R49
0.1µF
12.1 374 100 100
VIN
R8 R9 R10 5V R34 C18 VCORE_OUT
VCC BOOT
20k 953  28.7k 2.2  0.1µF C19 C20
C17 Q3 C31 C32 C33

+
1uF GND R35 22µF 22µF
R12 22µFx12 LOAD
UGATE 220uF
VREF R11 0 Optional L2
110k 7 13 Optional
TSEN PWM2 PWM PHASE
RNTC1 0.22µH
174k R13 Q4x2 DCR=0.98m 
DRVEN EN LGATE R36
8.66k R37 R38 C22
100k/β=4250 RT9610C
C21
R14 8 2.55k 2.55k 0.1µF
VIN VIN 1 R39
2.2  C2 ISEN2P
220nF C3 R40 3.74k
Optional 2
ISEN2N
23 680  C23
PSYS 0.1µF
R15
VIN
VREF NC 26 5V R41 C25
VREF06 VCC BOOT
R17 2.2  0.1µF C26 C27
R16 C24
R42 Q5 22µF 22µF
3.9 16.9k R19 1uF GND
25 IMON UGATE
R18 RNTC2 0 Optional L3
C4 23.2k 11
PWM3 PWM PHASE
0.47uF 3.83k 100k/β=4250 Q6x2 0.22µH
DRVEN EN LGATE R43 DCR=0.98m 
R44 R45 C29
VCCST 3.3V RT9610C
C28
2.55k 2.55k 0.1µF
5 R46
R20 R21 R22 R23 R24 ISEN3P
6 R47 3.74k
NC 100 45  1k 10k ISEN3N
10 C30
VR_READY 680 
16 0.1µF
VR_HOT
19
VCLK 31 5V
To CPU 18 ANS_EN
VDIO 0V
17
ALERT
9 VRON 14
Enable NC
28 32
VSEN NC
C5 C6

270pF 120pF
R25 R26 29
VCC_SENSE COMP 33 (Exposed Pad)
GND
C7 9.31k 30.1k 30
Optional C8 FB
Optional 27
VSS_SENSE RGND
C9
Optional

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

10
 RT3613EE
Typical Operating Characteristics
VR Power On from EN VR Power Off from EN

V CCIN V CCIN
(700mV/Div) (700mV/Div)
VR_READY VR_READY
(1V/Div) (1V/Div)
PWM1 PWM1
(4V/Div) (4V/Div)

EN EN
(1V/Div) (1V/Div)
VIN = 19V, VID = 1.8V, No Load VIN = 19V, VID = 1.8V, No Load

Time (500μs/Div) Time (50μs/Div)

VR OCP CORE VR UVP

130%ICCMAX VIN = 19V, VID = 1.8V

V CCIN V CCIN
(700mV/Div) (700mV/Div)
VR_READY VR_READY
(1V/Div) (1V/Div)

IMON PWM2
(2V/Div) (4V/Div)

PWM1 PWM1
(4V/Div) (4V/Div)

Time (10μs/Div) Time (5μs/Div)

CORE VR OVP VR Dynamic VID Up

VIN = 19V, VID = 1.8V

V CCIN V CCIN
(100mV/Div) V CCIN
(1V/Div)
offset 1.8V
VR_READY VCLK
(1V/Div) VCLK
VDIO
(1V/Div)
PWM2
VDIO ALERT
(4V/Div)
(1V/Div)
PWM1 ALERT
(4V/Div) (1V/Div) VIN = 19V, VID = 1.6V to 1.8V, Slew Rate = Slow

Time (50μs/Div) Time (10μs/Div)

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

11
 RT3613EE

VR Dynamic VID Down VR Dynamic VID Up

V CCIN
V CCIN
(100mV/Div)
offset 1.8V
V CCIN
(100mV/Div) V CCIN
offset 1.8V
VCLK VCLK
VCLK VDIO VCLK VDIO
(1V/Div) (1V/Div)
VDIO ALERT VDIO ALERT
(1V/Div) (1V/Div)
ALERT ALERT
(1V/Div) VIN = 19V, VID = 1.8V to 1.6V, Slew Rate = Slow (1V/Div) VIN = 19V, VID = 1.6V to 1.8V, Slew Rate = Fast

Time (10μs/Div) Time (10μs/Div)

VR Dynamic VID Down VR Mode Transient

V CCIN
V CCIN
(100mV/Div) V CCIN
offset 1.8V (30mV/Div)
offset 1.8V

VCLK VDIO
(1V/Div)
VCLK VDIO PWM1
(1V/Div)
(4V/Div)
VDIO ALERT
(1V/Div)
PWM2
ALERT (4V/Div)
(1V/Div) VIN = 19V, VID = 1.6V to 1.8V, Slew Rate = Fast VIN = 19V, VID = 1.8V, PS0 to PS2, ILOAD = 2A

Time (10μs/Div) Time (50μs/Div)

VR Mode Transient Thermal Monitoring

V CCIN
(30mV/Div)
offset 1.8V

VDIO
(1V/Div)

PWM1 VTSEN
(4V/Div) (500mV/Div)

PWM2
(4V/Div) VR_HOT
VIN = 19V, VID = 1.8V, PS2 to PS0, ILOAD = 2A (1V/Div) VIN = 19V, VTSEN Sweep from 1V to 2V

Time (50μs/Div) Time (5ms/Div)

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

12
 RT3613EE

∆VIMON vs. Load Current

1.6

1.4

1.2

1.0
∆VIMON (V)

0.8

0.6

0.4

0.2
ICCMAX = 78A
0.0
0 5 10 15 20 25 30 35 40 45 50 55 60
Load Current (A)

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

13
RT3613EE
Application Information
Power-ON Sequence After all internal settings are done and VBOOT = 0V,
In order to confirm sufficient power supply for proper VR_READY asserts to inform system that controller is
operation, the VR triggers UVLO if VCC pin drops below ready to communicate with CPU. If VBOOT = 1.8V,
4.3V (max). UVLO protection shuts down controller and VR_READY asserts until DVID to VBOOT. VR_READY
forces high-side MOSFET and low-side MOSFET off. When asserts within 2.5ms (max) after Chip Enable = H (VRON
VCC > 4.45, the RT3613EE issues POR = high and waits = H and VCC > 4.45V). The pull-high power of VRON pin
for VRON signal. After POR = high and VRON > 0.7V, is recommended as 1.05V, the same power as SVID
controller powers on (Chip Enable = H) and starts VR interface. That can ensure SVID power is ready while
internal settings, which include internal circuit offset VRON = H. For the VR normal operation, VIN should be
correction and function settings (PIN-SETTING). Users ready before VCC and VCC is strongly suggested to be
can set multi-functions through SETx and TSEN pins. ready before driver power(PVCC) to prevent current flowing
Figure 2 shows the typical timing of controller power-on. back to VCC from PVCC through PWMx pin or DRVEN
pin. Moreover, VRON must be the last one to asserts after
both VCC and PVCC are ready (>UVLO).

VIN

VCC

PVCC

VRON

Chip Enable
(VRON=H and VCC>4.45V)

Offset PIN-SETTING Offset

VR Initial Setting Mode Cancellation2
Cancellation1 Mode
Mode Mode

VR_READY

SVID Command

VSEN

Figure 2. Typical Timing of Controller Power-On

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

14
 RT3613EE
Maximum Active Phases Number Setting PIN-SETTING Mechanism
The number of active phases is determined by ISENxN The RT3613EE provides multiple parameters for platform
voltages. The detection is only active and latched at chip setting and BOM optimization. These parameters can be
enable rising edge (VRON = H and VCC > 4.45V). While set through SETx and TSEN pins. The RT3613EE adopts
voltage at ISENxN > (VCC - 0.7V), maximum active phase two-step PIN-SETTING mechanism to maximize IC pin
number is (x-1). For example, pulling ISEN3N and to VCC utilization. Figure 4 shows the timing chart of PIN-
programs a 2-phase operation. The unused ISENxP pins SETTING mechanism. Figure 5 illustrates this operating
are recommended to connect to VCC and the unused mechanism for SETx.
PWM pins can be floating. Figure 3 is a 2-phase operation The voltage at VREF06 pin ramps up to 3.2V after chip
example, the pull up voltage of ISEN3N should be enable = H. First, external divider voltage is sensed as
connected together with VCC of RT3613EE and the pull Vdivider. ADC codes Vdivider and stores in the Divider-
up resistor should be 10kΩ. Register. Second, internal current 80μA sources the divider
and generates another voltage as Vcurrent. VIXR = (Vcurrent-
Vdivider) is coded and stored in the IXR-Register. Vdivider
and Vcurrent can be represented as follows :

Vdivider  R2  3.2V
R1 R2

Vcurrent  R2  3.2V  80 A  R1 R2

R1  R2 R1  R2

Divider-Register and IXR-Register sets specified functions.

For example, Divider-Register of SET1 sets ICCMAX and
TON width setting; IXR-Register of SET1 set TON width
setting and VBOOT. All setting functions are summarized
in Table 1.

VIN
RT3613EE 5V
R39 C19
VCC BOOT Q3 C20 C21
C18 R40
UGATE
GND L2
Optional
13 PWM PHASE
PWM2
DRVEN EN LGATE R43 R44 R45 C23
Q4 x 2
RT9610C C22
Optional
R46
ISEN2P 1
R47
ISEN2N 2
680 C27
0.1µF

PWM3 11
R2
6.2Ω 24 VCC ISEN3P 5
5V R54
C1 ISEN3N 6
4.7µF
10kΩ

Figure 3. 2-Phases Operation Setting

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

15
RT3613EE
Chip Enable
(VRON=H and VCC>4.45V)

Offset PIN-SETTING Offset

VR Initial Setting Mode Cancellation1 Mode Cancellation2
Mode Mode
1.8V

VSEN (VBOOT=1.8V)
0V

3.2V

VREF06 0.6V

80uA

80uA Switch of SETx 0uA

80uA x (R1//R2)
3.2 x R2/(R1+R2)

SETx 0.6 x R2/(R1+R2)

SETx
SETx
Divider-
IXR-Register
Register

Figure 4. Timing Chart of PIN-SETTING Mechanism

80µA 80µA

VREF06 = VREF06 =
3.2V 3.2V

SETx SETx R1
R1
Divider-Register Divider-Register
SETx ADC SETx
ADC
SETx SETx
IXR-Register R2 IXR-Register R2

Figure 5. Operating Mechanism for SETx

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

16
 RT3613EE
Table 1. Summary of Pin Setting Functions
Function Setting Symbol Description
Divider TON width setting According to required frequency, to select
TONSET[3]
Register[4] (Switching frequency) TON width.
Divider According to platform, to set
ICCMAX ICCMAX[3:0]
Register[3:0] corresponding ICCMAX.
SET1 IXR TON width setting According to required frequency, to select
TONSET[2:0]
Register[4:2] (Switching frequency) TON width.
VBOOT_SET= 0: VBOOT=0V, wait for
IXR SVID command after controller power on.
VBOOT VBOOT_SET
Register[1] VBOOT_SET= 1: Automatically DVID
to VBOOT=1.8V after controller power on.
Divider Anti-overshoot trigger ANTIOVS for reduction of overshoot at
ANTIOVS_TH[2:0]
Register[4:2] level loading falling edge. To set trigger level.
Divider
Current gain Ai[1:0] Current gain setting
Register[1:0]
IXR DVID Fast_SR = 0 : 48mV/us; for
DVID fast slew rate DVID Fast_SR
Register[4] Y/U/H-line.
SET2 ANS_EN = 0 and ANS_EN pin pull low :
IXR Acoustic noise Disable.
ANS_EN
Register[3] suppression ANS_EN = 1 and ANS_EN pin pull high :
Enable.
High frequency ACLL
IXR HFACLL_LIFT To provide positive offset in high
voltage compensation
Register[2:1] _PS1[1:0] frequency ACLL.
in PS1
Adaptive quick
Divider AQR for loop response speed-up of
response(AQR) AQR_TH[2:0]
Register[4:2] loading rising edge. To set trigger level.
trigger level
Divider Zero current detection Detects whether each phase current
ZCD_TH[1:0]
Register[1:0] threshold crosses zero current. To set trigger level.
SET3
IXR SUM_OC = 0 : 160% x ICCMAX
Sum OCP ratio SUM_OC
Register[4] SUM_OC = 1 : 130% x ICCMAX
To improve undershoot by applying a
IXR Undershoot
UDS[2:0] positive offset at loading edge. To set
Register[3:1] suppression
trigger level.
Advanced Ramp is developed to solve
Divider Advanced ramp loop natural lag due to PCB parasitic
FLRAMP_PS1
Register[5] magnitude in PS1 inductance and prevent adjacent PWM
turn-on.
Advanced Ramp is developed to solve
Divider Advanced ramp loop natural lag due to PCB parasitic
FLRAMP_PS0[1:0]
TSEN Register[4:3] magnitude in PS0 inductance and prevent adjacent PWM
turn-on.
Divider Zero LL_EN = 0 : Disable zero load line.
Zero load line Zero LL_EN
Register[2] Zero LL_EN = 1 : Enable zero load line.
DVID_LIFT = 0 : Disable.
Divider DVID voltage
DVID_LIFT DVID_LIFT = 1 : 5uA current source sinks
Register[1] compensation level
from FB pin.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

17
RT3613EE
Referring to PIN-SETTING tables 2 to 7, users can search
corresponding Vdivider or VIXR according to the desired
function setting combinations. Then SETx external
resistors can be calculated as follows :

3.2V  VIXR
R1 
80 A  Vdivider
R1 Vdivider
R2 
3.2V  Vdivider

Richtek provides a Microsoft Excel-based design tool to

calculate the desired PIN-SETTING resistors.
TSEN pin also has function settings except for thermal
monitoring function. It only utilizes divider part of PIN-
SETTING mechanism. The functions TSEN sets include
zero loadline and DVID voltage-compensation. The detailed
operation is described in Thermal Monitoring and Indicator
section.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

18
 RT3613EE
Table 2. SET1 Pin Setting for ICCMAX, KTON and VBOOT
Vdivider_SET1 (mV) ICCMAX(A) VIXR_SET1 (mV)
KTON VBOOT
Min. Typ. Max. 1 Phase 2 Phase 3 Phase Min. Typ. Max.
6.5 25 43 26 30 44 6.5 50 91.5 0V
0.64
57 75 92.5 27 33 49 108.5 150 189.5 1.8V
107.5 125 142 28 36 54 210.5 250 287.5 0V
0.73
158 175 191.5 29 39 59 312.5 350 385.5 1.8V
208.5 225 241 30 42 64 414.5 450 483.5 0V
0.82
259 275 290.5 31 45 69 516.5 550 581.5 1.8V
309.5 325 340 32 48 74 618.5 650 679.5 0V
0.91
360 375 389.5 33 51 79 720.5 750 777.5 1.8V
410.5 425 439 34 54 84 822.5 850 875.5 0V
1
461 475 488.5 35 57 89 924.5 950 973.5 1.8V
511.5 525 538 36 60 94 1026.5 1050 1071.5 0V
1.09
562 575 587.5 37 63 99 1128.5 1150 1169.5 1.8V
612.5 625 637 38 66 104 1230.5 1250 1267.5 0V
1.18
663 675 686.5 39 69 109 1332.5 1350 1365.5 1.8V
713.5 725 736 40 72 114 1434.5 1450 1463.5 0V
1.27
764 775 785.5 41 75 119 1536.5 1550 1590 1.8V
814.5 825 835 26 30 44 6.5 50 91.5 0V
1.36
865 875 884.5 27 33 49 108.5 150 189.5 1.8V
915.5 925 934 28 36 54 210.5 250 287.5 0V
1.45
966 975 983.5 29 39 59 312.5 350 385.5 1.8V
1016.5 1025 1033 30 42 64 414.5 450 483.5 0V
1.64
1067 1075 1082.5 31 45 69 516.5 550 581.5 1.8V
1117.5 1125 1132 32 48 74 618.5 650 679.5 0V
1.82
1168 1175 1181.5 33 51 79 720.5 750 777.5 1.8V
1218.5 1225 1231 34 54 84 822.5 850 875.5 0V
2.09
1269 1275 1280.5 35 57 89 924.5 950 973.5 1.8V
1319.5 1325 1330 36 60 94 1026.5 1050 1071.5 0V
2.36
1370 1375 1379.5 37 63 99 1128.5 1150 1169.5 1.8V
1420.5 1425 1429 38 66 104 1230.5 1250 1267.5 0V
2.55
1471 1475 1478.5 39 69 109 1332.5 1350 1365.5 1.8V
1521.5 1525 1528 40 72 114 1434.5 1450 1463.5 0V
2.91
1572 1575 1577.5 41 75 119 1536.5 1550 1590 1.8V

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

19
RT3613EE
Table 3. SET2 Pin Setting for ANTIOVS_TH and Ai Gain
Vdivider_SET2 (mV) ANTIOVS_TH
Ai
Min. Typ. Max. (mV)
6.5 25 43 0.125
57 75 92.5 0.25
90
107.5 125 142 0.375
158 175 191.5 0.5
208.5 225 241 0.125
259 275 290.5 0.25
120
309.5 325 340 0.375
360 375 389.5 0.5
410.5 425 439 0.125
461 475 488.5 0.25
150
511.5 525 538 0.375
562 575 587.5 0.5
612.5 625 637 0.125
663 675 686.5 0.25
180
713.5 725 736 0.375
764 775 785.5 0.5
814.5 825 835 0.125
865 875 884.5 0.25
210
915.5 925 934 0.375
966 975 983.5 0.5
1016.5 1025 1033 0.125
1067 1075 1082.5 0.25
240
1117.5 1125 1132 0.375
1168 1175 1181.5 0.5
1218.5 1225 1231 0.125
1269 1275 1280.5 0.25
270
1319.5 1325 1330 0.375
1370 1375 1379.5 0.5
1420.5 1425 1429 0.125
1471 1475 1478.5 0.25
Disable
1521.5 1525 1528 0.375
1572 1575 1577.5 0.5

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

20
 RT3613EE
Table 4. SET2 Pin Setting for DVID Fast Slew Rate, Acoustic Noise Suppression and High Frequency ACLL
Voltage Compensation in PS1
VIXR_SET2 (mV) High frequency ACLL
DVID Fast Slew Acoustic Noise
voltage compensation in
Min. Typ. Max. Rate Suppression
PS1 (index)
6.5 50 91.5 60
108.5 150 189.5 80
Disable
210.5 250 287.5 100
312.5 350 385.5 48mV/us Disable
414.5 450 483.5 (Y/U/H-line) 60
516.5 550 581.5 80
Enable
618.5 650 679.5 100
720.5 750 777.5 Disable

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

21
RT3613EE
Table 5. SET3 Pin Setting for AQR_TH and ZCD_TH
Vdivider_SET3 (mV) AQR_TH ZCD_TH
Min. Typ. Max. (mV) [Vcx (mV)]
6.5 25 43 1.81
57 75 92.5 2.57
440
107.5 125 142 3.17
158 175 191.5 3.93
208.5 225 241 1.81
259 275 290.5 2.57
520
309.5 325 340 3.17
360 375 389.5 3.93
410.5 425 439 1.81
461 475 488.5 2.57
600
511.5 525 538 3.17
562 575 587.5 3.93
612.5 625 637 1.81
663 675 686.5 2.57
680
713.5 725 736 3.17
764 775 785.5 3.93
814.5 825 835 1.81
865 875 884.5 2.57
760
915.5 925 934 3.17
966 975 983.5 3.93
1016.5 1025 1033 1.81
1067 1075 1082.5 2.57
840
1117.5 1125 1132 3.17
1168 1175 1181.5 3.93
1218.5 1225 1231 1.81
1269 1275 1280.5 2.57
920
1319.5 1325 1330 3.17
1370 1375 1379.5 3.93
1420.5 1425 1429 1.81
1471 1475 1478.5 2.57
Disable
1521.5 1525 1528 3.17
1572 1575 1577.5 3.93

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

22
 RT3613EE
Table 6. SET3 Pin Setting for Sum OCP Ratio and Undershoot Suppression
VIXR_SET3 (mV) Sum OCP Undershoot Suppression
Min. Typ. Max. Ratio PS0(index) PS1(index)
6.5 50 91.5 Disable Disable
108.5 150 189.5 Disable 175
210.5 250 287.5 200 125
312.5 350 385.5 200 150
160%
414.5 450 483.5 200 175
516.5 550 581.5 250 125
618.5 650 679.5 250 150
720.5 750 777.5 250 175
822.5 850 875.5 Disable Disable
924.5 950 973.5 Disable 175
1026.5 1050 1071.5 200 125
1128.5 1150 1169.5 200 150
130%
1230.5 1250 1267.5 200 175
1332.5 1350 1365.5 250 125
1434.5 1450 1463.5 250 150
1536.5 1550 1590 250 175

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

23
RT3613EE
Table 7. TSEN Pin Setting for Advanced Ramp Magnitude in PS1, Advanced Ramp Magnitude in PS0, Zero
LL and DVID_LIFT
VTSEN (mV) Advanced ramp Advanced ramp magnitude
Zero LL DVID_LIFT
Min. Typ. Max. magnitude in PS1(index) in PS0(index)
6.5 50 92.5 Disable
Disable
107.5 150 191.5 5uA
125
208.5 250 290.5 Disable
Enable
309.5 350 389.5 5uA
410.5 450 488.5 Disable
Disable
511.5 550 587.5 5uA
175
612.5 650 686.5 Disable
Enable
713.5 750 785.5 5uA
125
814.5 850 884.5 Disable
Disable
915.5 950 983.5 5uA
225
1016.5 1050 1082.5 Disable
Enable
1117.5 1150 1181.5 5uA
1218.5 1250 1280.5 Disable
Disable
1319.5 1350 1379.5 5uA
Disable
1420.5 1450 1478.5 Disable
Enable
1521.5 1550 1577.5 5uA
1622.5 1650 1676.5 Disable
Disable
1723.5 1750 1775.5 5uA
125
1824.5 1850 1874.5 Disable
Enable
1925.5 1950 1973.5 5uA
2026.5 2050 2072.5 Disable
Disable
2127.5 2150 2171.5 5uA
175
2228.5 2250 2270.5 Disable
Enable
2329.5 2350 2369.5 5uA
175
2430.5 2450 2468.5 Disable
Disable
2531.5 2550 2567.5 5uA
225
2632.5 2650 2666.5 Disable
Enable
2733.5 2750 2765.5 5uA
2834.5 2850 2864.5 Disable
Disable
2935.5 2950 2963.5 5uA
Disable
3036.5 3050 3062.5 Disable
Enable
3137.5 3150 3161.5 5uA

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

24
 RT3613EE
ILx VCORE
Per Phase Current Sense
LX DCR
To achieve higher efficiency, the RT3613EE adopts
inductor DCR current sensing to get each phase current RX1
CX
signal, as illustrated in Figure 6. An external low-pass
+ VCSIN -
filter RX1 and CX reconstruct the current signal. The low- RX2
ISENxP
pass filter time constant RX1 x CX should match time Gm
+
- RCSx=680ohm Option
LX ISENxN
constant DCR of Inductance and DCR. It's fine to fine IMONx
ICBx ICS,PERx
tune RX1 and CX for transient performance and current IZDx
IOCx
reporting. if RC network time constant matches inductor
LX
time constant DCR , an ideal load transient waveform can Figure 6. Inductor DCR Current Sensing Method

be designed. If RC network time constant is larger than

LX
inductor time constant DCR , VCORE waveform has a
sluggish droop during load transient. Lx
VCORE
Rx  Cx = IOUT x RLL
LX DCRx
If RC network is smaller than inductor time constant DCR ,

VCORE waveform sags to create an undershooting to fail

IOUT
the specification and mis-trigger over current protections VIMON
(sum OCP and per phase OCP). Figure 7 shows the output Ideal load transient waveform
waveforms according to the RC network time constant.
The resistance of RCSx is restricted to 680Ω and the
accuracy is within 1%. RX1 is highly recommended as
VCORE Lx
two 0603 size resistors in series to enhance the Iout Rx  Cx < IOUT x RLL
DCRx
reporting accuracy. X7R type capacitor is suggested for
CX in the application.
IOUT
VCSIN ILx  DCR
ICS,PERx   VIMON
680 680
Undershoot created in VCORE
RX2 is optional for prevent VCSIN exceeding current sense
amplifier input range. The time constant of (RX1//RX2) x C
LX
should match .
DCR VCORE Lx
Rx  Cx > IOUT x RLL
V I  DCR R X2 DCRx
ICS,PERx  CSIN  Lx 
680 680 (R X1+R X2 )
IOUT
The current signal ICS,PERx is mirrored for loadline control/
VIMON
current reporting, current balance, zero current detection Sluggish droop
and over current protection. The mirrored current to IMON
Figure 7. All Kinds of RC Network Time Constant
pin is one time of ICS,PER.

IIMON  AMIRROR  ICS,PERx , AMIRROR  1

The current sense lines must be routed as differential pair
from the inductor to the controller on the same layer.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

25
RT3613EE
Total Current Sense/ICCMAX Setting/Current IL1 VCORE

L
Monitoring DCR

C
To compensate DCR positive temperature coefficient, R
ISEN1P
conventional current sense method needs an NTC resistor VIMON +
Gm
IMON - ISEN1N RCS1=680ohm
for per phase current loop. The RT3613EE adopts a
IIMON1 ICS,PER1
patented total current sense method that requires only IL2
L DCR
one NTC resistor for thermal compensation. The NTC
C
resistor is designed within IMON resistor network on IMON R

ISEN2P
pin. It is suggested to be placed near the inductor of the RNTC +
Gm
- RCS2=680ohm
ISEN2N
first phase. Figure 8 shows the configuration. All phase
IIMON2 ICS,PER2
current signals are gathered to IMON pin and converted IL3
VREF06 L DCR
to a voltage signal VIMON by RIMON,EQ based on VREF06
C
pin. VREF06 pin provides 0.6V voltage source (as VVREF06 R

ISEN3P
presented as VVREF06) while normal operation. The +
Gm
- ISEN3N RCS3=680ohm
relationship between VIMON and inductor current ILx is :
IIMON3 ICS,PER3

VIMON  VVREF06  IL1 +IL2 +IL3   DCR  R IMON,EQ +

0.6V
R CSx -

VIMON − VVREF06 is proportional to output current. VIMON −

Figure 8. Total Current Sense Method
VVREF06 is used for output current reporting and loadline
loop-control. VIMON − VVREF06 is averaged by analog low-
pass filter and then transferred to 8-bit ADC. The digitized
reporting value is scaled such that FFh=ICCMAX. RIMON,EQ
should be designed that VIMON − VVREF06 = 1.6V while
(IL1+IL2+IL3) = ICCMAX. Additionally, sets the desired
ICCMAX by ICCMAX[3:0] of PIN-SETTING table. The PIN-
SETTING value determines intel ICCMAX register (21h)
value. The Alert# is asserted while output current exceeds
ICCMAX (VIMON − VVREF06 > 1.6V). The behavior is masked
during DVID. For loadline loop-control, VIMON − VVREF06 is
scaled by a percentage of Ai, that can be selected by
PIN-SETTING of Ai[1:0]. The detailed application is
described in the loadline setting section.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

26
 RT3613EE
Loadline Setting (RLL) VCORE

An output voltage loadline (Adaptive Voltage Positioning)

are specified in CPU VR for power saving and output VID

capacitance reduction. The characteristic of loadline is Loadline=-RLL

RLL x ICCMAX
that the output voltage decreases by an amount proportional
to the increasing loading current, i.e. the slope between
output voltage and loading current (RLL) is shown in Figure
9. Figure 10 shows how the voltage and current loop Loading
Current
parameters of RT3613EE achieve loadline. The detailed ICCMAX

equation is described as below : Figure 9. Load-Line (Droop)

Current Loop Gain DCR Ai

RLL    RIMON,EQ  3 Table 8. PIN-SETTING of Ai[1:0]
Voltage Loop Gain RCSx REA2 4
REA1 Ai[1:0] Current Gain Setting

Ai is current gain. REA2 / REA1 is defined as ERROR AMP 00 0.125

gain. In order to have better transient performance, the 01 0.25
ERROR AMP gain is suggested to be within 2.2 to 3.6 10 0.375
when ICCMAX >= 45A and within 2.2 to 5 when ICCMAX 11 0.5
< 45A. RLL can be programmed by Ai and REA2 / REA1. Ai
can be selected by PIN-SETTING of Ai [1:0] as listed in
Table 8.

Voltage Loop
VCORE

REA2 PWM
- CMP TON
REA1 +
+ GEN/
ERROR - Driver
VID Interface
AMP
IL1,2,3

DCR Lx

Rx Ai x 2.5
+

-
Cx 1:1
ISENxP
+ Gm RIMON,EQ
-
RCSx=680Ω ISENxN IMON VREF06
RNTC

ICS,PERx
(ICS,PER1 + ICS,PER2
+ ICS,PER3 )
Current Loop

Figure 10. Voltage Loop and Current Loop for Load Line

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

27
RT3613EE
Dynamic VID (DVID) Compensation adjusted. Compensating magnitude can also be adjusted
During DVID transition, an extra current is required to by REA1. For IMVP9 specification, output voltage should
charge output capacitance for increasing voltage. The be within target TOB at 3μs after Alert# assertion. While
charging current approximates to the product of the DVID DAC just arrives target (Alert issue timing), inductor current
slew rate and output capacitance. For droop system, the is still high and needs a time to settle down to the DC
extra charging current induces extra voltage droop so that loading current. In the settling time, the falling down current
the output voltage cannot reach target within the specified keeps to charge output capacitance (The magnitude is
time. The extra voltage drop approximates to DVID Slew related with inductor, capacitance and VID). Thus DVID
Rate x Output Capacitance x RLL (RLL is the loadline slope, compensation can be less than DVID Slew Rate x Output
Ω). This phenomenon is called droop effect. How charging Capacitance (Capacitance degeneration should be
current affects loop is illustrated in Figure 11. The considered). While output capacitance is so large that
RT3613EE provides one DVID compensation function as DVID compensation cannot cover, adding resistor and
shown in Figure 12. An internal current IDVID_LIFT is sinking capacitance from FB to GND also can provide similar
internally from FB pin to generate DVID compensation function. ERROR AMP compensation (resistance and
IDVID_LIFT x REA1. IDVID_LIFT for 50mV/μs DVID SR can be capacitance network among VSEN, FB and COMP) also
set from TSEN PIN-SETTING of DVID_LIFT, disabled or affects DVID behavior. The final setting should be based
5uA. For different scale of DVID SR, IDVID_LIFT is internally on actual measurement.

Charging
Inductor Current Current
for DVID

Droop Effect

VSEN
VID

Figure 11. Droop Effect in VID Transition

DCR Lx
VIN
Q1 Cx Rx CO1 CO2
Q2
Gate
Driver RESR
Charging
Inductor Current Current
Current for DVID
Sense C2

REA2 C1

TON Improved VSEN

GEN/ -
-
- REA1+ VID
Driver + EA DVID Compensation
Interface PWM +
CMP VID IDVID_LIFT

Optional for extra large

ouput capacitance
Figure 12. DVID Compensation
Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

28
 RT3613EE
Compensator Design Switching Frequency Setting
The compensator of the RT3613EE doesn't need a The RT3613EE topology G-NAVPTM (Green Native AVP)
complex type II or type III compensator to optimize control is one kind of current-mode constant on-time control. It
loop performance. It can adopt a simple type I generates an adaptive TON (PWM) with input voltage (VIN)
compensator (one pole, one zero) in the G-NAVPTM for better line regulation. The TON is also adaptive to VID
topology to fine tune ACLL performance. The one pole voltage. For VID < 1.8V, the adaptive TON is based on
and one zero compensator is shown in Figure 13. For constant current ripple concept for better output voltage
IMVP9 ACLL specification, it is recommended to adjust ripple size control. For VID ≥ 1.8V, the adaptive TON is
compensator according to load transient ring back level. based on constant frequency concept for better efficiency
Default compensator values are referred to design tool. performance. Figure 15 is the conceptual chart showing
the relationships between switching frequency vs. VID and
C2
current ripple vs. VID. The RT3613EE provides a parameter
REA2 C1 setting of kTON to design TON width. kTON is set by PIN-
REA1 SETTING of TONSET[3:0]. The related setting table is
- VSEN listed in Table 9.
COMP EA FB
+
The equations of TON are listed as below (kTON should be
VID referred to Table 9) :
Figure 13. Type I Compensator

VID  1.8V
Differential Remote Sense Setting VID
TON  2.206   15ns
The VR provides differential remote-sense inputs to k TON   VIN  1.8V 
eliminate the effects of voltage drops along the PC board
traces, CPU internal power routes and socket contacts. 0.3V  VDAC < 1.8V
The CPU contains on-die sense pins, VCC_SENSE and TON(PWM)  3.971  1  15ns
VSS_SENSE. The related connection is shown in Figure 14. k TON   VIN  VDAC 
The VID voltage (DAC) is referred to RGND to provide
accurate voltage at remote CPU side. While CPU is not VDAC < 0.3V
mounted on the system, two resistors of typical 100Ω TON(PWM)  3.971  1  15ns
are required to provide output voltage feedback. k TON   VIN  0.3 

C1 VSEN

FB REA1 100
-
EA CPU VCC_SENSE
+
COUT
+
CPU
VID -
RGND CPU VSS_SENSE
100

Figure 14. Remote Sensing Circuit

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

29
RT3613EE
Table 9. PIN-SETTING of TONSET Although TON is designed for constant frequency target
TONSET[3:0] KTON while VID ≥ 1.8, the actual frequency is still impacted by
0000 0.64 main power stage's loss and driver dead time. The
0001 0.73 switching frequency rises as loading current increases.
0010 0.82 Recommend to design the switching frequency based on
0011 0.91 the optimized efficiency and thermal performance at thermal
0100 1 design current (ICCTDC). For example, at ICC = ICCTDC, VID
0101 1.09 = 1.8V and VIN = 19V, the switching frequency is 850kHz.
0110 1.18 Then substitute these values into equations to get TON
0111 1.27 and relative kTON.
1000 1.36
Richtek provides a Microsoft Excel-based design tool to
1001 1.45
help design RTON and kTON setting for the desired switching
1010 1.64
frequency at TDC.
1011 1.82
1100 2.09 Frequency

1101 2.36
VIN=19V Controller internally control
1110 2.55 VIN=12V TON adaptive to variable VIN

1111 2.91

The switching frequency can be derived from TON as shown

VID
below. The losses in the main power stage and driver
1.8
characteristics are considered.
Current
Ripple
I  RONLS,max 
VID  CC   DCR   N  RLL  VIN=19V
N  nLS 
Freq  VIN=12V
 ICC  RONLS,max RONHS,max   ICC RONLS,max
 VIN        TON  TD  TONVAR     TD
 N  nLS nHS   N nLS

VID : VID voltage

VIN : input voltage
VID
ICC : loading current
1.8

N : total phase number Figure 15. Switching Frequency and Current with
RONLS,max : maximum equivalent low-side RDS(ON) Different VID

nHS : number of high-side MOSFETs

RONHS,max : maximum equivalent high-side RDS(ON)
nLS : number of low-side MOSFETs.
TD : summation of the high-side MOSFET delay time and
rising time
TONVAR : TON variation value
DCR : inductor DCR
RLL : loadline setting (Ω).

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

30
 RT3613EE
Adaptive Quick Response (AQR) Table 10. PIN-SETTING of AQR_TH
The RT3613EE features adaptive quick response (AQR) AQR Starting Trigger
AQR_TH[2:0]
function to optimize transient response. The mechanism Threshold(mV)
concept is illustrated in Figure 16. Controller detects 000 440
output voltage drop slew rate. While the slew rate exceeds 001 520
the AQR threshold, all PWMs turn on until output voltage 010 600
slew rate significantly slows down. The output voltage slew 011 680
100 760
rate transition also indicates that inductor current almost
101 840
reaches the loading current. Under such mechanism, AQR
110 920
PWM width is adaptive to variable loading step. The
111 Disable
RT3613EE provides various AQR threshold through PIN-
SETTING of AQR_TH[2:0]. The following equation can
Anti-overshoot (ANTI-OVS)
initially decide the AQR starting trigger threshold. Smaller
The RT3613EE provides Anti-overshoot Function to
threshold indicates larger AQR PWM. Note that the
depress output voltage overshoot. Controller detects
threshold should be larger than steady-state output voltage
overshoot by signals relating to output voltage. The
ripple falling slew rate and also the overshoot falling slew
overshoot trigger level can be adjusted by PIN-SETTING
rate to avoid miss triggering AQR.
as listed in Table 11. The main detecting signal comes
AQR starting trigger threshold = -200k  20p  dVSEN from COMP. However, COMP varies with compensation.
dt Initial trigger level setting can be based on the following
equation :
VBIAS Vdiff
Output PWM_
R
voltage AQR COMP  4  VSEN  EA2  4
3 REA1 3
AQR
Threshold  Antiovershoot Threshold of ANTIOVS_TH[2:0]

VBIAS The final setting should be according to actual Error AMP

compensator design and measurement.
Output
voltage While overshoot exceeds the setting trigger level, all
PWMs keep in tri-state until the zero current is detected.
Io Turning off LGs forces positive current flow through body
diode to cause diode forward voltage. The extra forward
voltage can speed up inductor current discharge and
AQR
Vdiff Threshold decrease overshoot.

PWM Table 11. PIN-SETTING of Anti-Overshoot Threshold

_AQR Anti-Overshoot Threshold
ANTIOVS_TH[2:0]
(mV)
Figure 16. Adaptive Quick Response Mechanism
000 90
001 120
010 150
011 180
100 210
101 240
110 270
111 Disable

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

31
RT3613EE
Dual Ramp Mechanism
Normal controllers easily suffer jitter and stability issues
under low equivalent series resistance (ESR) of capacitor
application and large loop delay condition. The large Loop
delay often comes from PCB parasitic inductance. Figure
17 illustrates how PCB parasitic inductance impact on
the load transient response. The PCB parasitic inductance
delays energy delivering and causes VSEN to keep falling.
The dropping VSEN induces several successive PWM
pulses and then VSEN ring-back occurs. While load
current release at the ring back region, it will generate
larger overshoot. Thus more capacitors will use for the
overshoot reduction.

Loading Current ΔIcc

VSEN

PWM1

PWM2

PWM3

Figure 17. Load Transient Response with PCB Parasitic Inductance

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

32
 RT3613EE
RT3613EE provides a new generation of dual ramp
mechanism to enhance performance. Except original ramp
to minimize jitter, additional Advanced Ramp is developed
to solve loop natural lag due to PCB parasitic inductance
and prevent adjacent PWM turn-on. That has current signal
meaning and prediction. The transient ring-back can be
effectively suppressed. Figure 18 and Figure 19 show the
apparent difference between single ramp and dual ramp
with PCB parasitic inductance condition.

Loading Current ΔIcc

Output Voltage

Ramp

Comp

Figure 18. Single Ramp Behavior with PCB Parasitic Inductance Condition

Loading Current ΔIcc

Output Voltage

Ramp

Comp

Figure 19. Dual Ramp Behavior with PCB Parasitic Inductance Condition

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

33
RT3613EE
Through PIN-SETTING, RT3613EE provides advanced ACLL Performance Enhancement
ramp magnitude tuning. FLRAMP_PS0[1:0] and RT3613EE provides another optional function to improve
FLRAMP_PS1 are for PS0 and PS1, respectively. undershoot by applying a positive offset at loading edge.
According to different application conditions, the setting Controller detects COMP signal and compared it with
of parameters are listed in Table 12 and Table 13. The steady state. While VCOMP variation exceeds a threshold,
larger magnitude indicates larger parasitic inductance an additional positive offset will apply to the output voltage.
suppression. However, larger magnitude also affects loop The threshold can be set through PIN-SETTING and
response speed and reduce PWM output frequency at separately for PS0 and PS1, as listed in Table 14. The
loading edge. For normal PCB layout, FLRAMP_PS0[1:0] smaller index indicates the easier detection being
= 00 or FLRAMP_PS0[1:0]=11 are recommended. The triggered. The positive offset is related to the compensation.
final setting must be based on actual measurement.  REA2 
It can approximate to 60mV/  R  . In PS0, the slew
 EA1 
rate of VRAMP would increase when the VCOMP intersect
Table 12. PIN-SETTING of Advanced Ramp the positive offset. In order to send out another on-time
Magnitude in PS0 earlier to improve undershoot. In PS1, besides the positive
offset, an additional 10mV is applied to the DAC and one
FLRAMP_PS0 Internal Advanced
[1:0] Ramp Magnitude (index) pulse of PWM is also forced turn on while the function is
triggered. The positive offset and the 10mV DAC offset is
00 125
released gradually with about hundred microsecond. Figure
01 175
20 and Figure 21 show undershoot suppression behavior
10 225
in PS0 and PS1. For different platform, the optimized
11 Disable setting is different. The final setting must be based on
actual measurement.
Table 13. PIN-SETTING of Advanced Ramp
Magnitude in PS1 Table 14. PIN-SETTING of Undershoot Suppression

Internal Advanced Ramp UDS[2:0] PS0 (index) PS1 (index)

FLRAMP_PS1
Magnitude (index)
000 Disable Disable
0 125
001 Disable 175
1 175
010 200 125
011 200 150
100 200 175
101 250 125
110 250 150
111 250 175

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

34
 RT3613EE

VRAMP

Positive offset

VCOMP

PWM

Load

Figure 20. Undershoot Suppression Behavior in PS0

VRAMP

Positive offset

VCOMP

PWM

Load

Figure 21. Undershoot Suppression Behavior in PS1

High Frequency ACLL Voltage Compensation Table 15. PIN-SETTING of High Frequency ACLL
RT3613EE provides positive offset to enhance performance Voltage Compensation in PS1
that only applies to high frequency ACLL. The positive HFACLL_LIFT_PS1 High frequency ACLL voltage
offset can be set through PIN-SETTING in PS1. The related [1:0] compensation in PS1 (index)
setting table is listed in Table 15. HFACLL_LIFT_PS1[1:0]
00 60
is the related settings. The default set of
01 80
HFACLL_LIFT_PS1[1:0] = 00. Note that smaller setting
10 100
value represents higher positive offset. The final setting
must be based on actual measurement. 11 Disable

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

35
RT3613EE
Thermal Monitoring and Indicator
80µA
TSEN pin processes two functions of PIN-SETTING PIN-SETTING Mode
(function setting) and thermal monitoring as shown in VREF06
= 3.2V
R3
Figure 22. The timing chart and related signals are shown PIN-SETTING
Register
in Figure 23. After power on, TSEN has three operation RNTC R1
Pre-Thermal TSEN
modes: PIN-SETTING, Pre-Thermal Sense and Thermal Register ADC

Sense Mode. The corresponding function blocks of the R2

Thermal Register
three modes are shown in Figure 22. In PIN-SETTING VDDIO

Mode, TSEN pin voltage = 3.2V x R2/(R1 + R2) with

-
VREF06 = 3.2V and is coded by ADC and stored in PIN- +
VR_HOT#
1.092V
SETTING register. In Pre-Thermal Sense Mode, TSEN pin Thermal Sense Mode
voltage = 0.6V x R2/(R1 + R2) with VREF06 = 0.6V and
is coded and stored in Pre-Thermal Register. This part
helps Thermal Sense Mode calculation. In Thermal Sense
Mode, TSEN pin voltage = 0.6V x R2/(R1 + R2) + 80μA x Pre-Thermal 80µA
[(R1//R2) + R3] with VREF06 = 0.6V and is coded. Pre- Sense Mode
VREF06
Thermal Register code is subtracted from the result and = 0.6V
R3
the value is stored in Thermal Register (The corresponding PIN-SETTING
Register
TSEN voltage = 80μA x [(R1//R2) + R3] that's defined as RNTC R1
Pre-Thermal TSEN
Thermal Voltage. R3 is the NTC thermistor network to Register ADC

sense temperature.) NTC thermistor is recommended to R2

Thermal Register
be placed near the MOSFET, the hottest area in the PCB. VDDIO

Higher temperature causes smaller R3 and lower TSEN.

-
According to NTC thermistor temperature curve, design VR_HOT#
+
1.092V
Thermal Voltage v.s Temperature with proper Rx network Thermal Sense Mode
to meet Table 16. 100°C Thermal Voltage = 80μA x [(R1/
/R2) + R3, 100°C] = 1.092V must be met. Controller
processes TSEN pin voltage to report temperature zone
80µA
register (12h). While TSEN pin voltage is less than 1.092V, Thermal Sense Mode
VR_HOT# is pulled low to indicate thermal alert. The VREF06
= 0.6V
VR_HOT# signal is an open-drain signal. Thermal Register R3
PIN-SETTING
data is updated every 100μs and averaged every 800μs. Register
RNTC R1
The resistance accuracy of TSEN network is recommended Pre-Thermal
ADC
TSEN
Register
to be less than 1% error.
R2
Thermal Register
VDDIO

-
VR_HOT#
+
1.092V
Thermal Sense Mode

Figure 22. Multi-Function Pin Setting Mechanism for

TSEN

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

36
 RT3613EE

EN
VR Internal
Setting 1.8V
VSEN
(VBOOT=1.8V) 0V

3.2V

VREF06 0.6V

80uA
80uA Switch of
0uA
TSEN
TSEN Operation PIN-SETTING Pre-Thermal
Thermal Sense Mode
Mode Mode Sense Mode

3.2 x R2/(R1+R2)
0.6 x R2/(R1+R2) + 80uA x [(R1//R2)+R3]
TSEN Higher
Thermal Voltage: temperature, lower
PIN-SETTING
Pre-Thermal 80uA x [(R1//R2)+R3] V(TSEN)
Register
Register
Thermal
Register
Temperature 25 Celsius

Figure 23. Timing Chart for Thermal Monitoring

Ω , Beta = 4485K
Table 16. Thermal Zone and Detection Encoding with RNTC = 100kΩ
Thermal Voltage Temperature Zone Register
Temperature
80A x [(R1//R2) + R3] (12h)
100℃ 1.092V FFh
97℃ 1.132V 7Fh
94℃ 1.176V 3Fh
91℃ 1.226V 1Fh
88℃ 1.283V 0Fh
85℃ 1.346V 07h
82℃ 1.418V 03h
75℃ 1.624V 01h

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

37
RT3613EE
PWM Tri-state Quick Control Pulse efficiency. The RT3613EE provides a tri-state quick control
The RT3613EE can operate in Diode Emulation Mode pulse to solve it. In order to shorten the rising time of tri-
(DEM) to enhance light load efficiency in PS2 and PS3. state, RT3613EE would force PWM signal level close to
In DEM operation, controller monitors inductor current by tri-state level but only keep 200ns. That can push discrete
per phase current sense and zero current detection blocks. driver or Dr. MOS to recognize tri-state earlier and turn off
While inductor current reaches zero, both PWM pull-high low-side power MOSFET immediately. However, different
and pull-low switches are disabled to let PWM in tri-state. vendors of discrete driver or Dr.MOS have different PWM
Then the PWM voltage are controlled by discrete driver's tri-state window. The RT3613EE tri-state window is 1.6V
or Dr.MOS's divider. After discrete driver or Dr.MOS to 2.2V. The control block diagram and concept are
identifies tri-state PWM, they turn off low-side power illustrated in Figure 24 and Figure 25, respectively.
MOSFET. The identifying time usually takes long and
causes low-side power MOSFET delay turn off and impact

VCC
Dr.MOS
Or VDD
PWM_INT
RPWM_SRC<29ohm Driver
PWM_TRI‐STATE
PWMx PWM

PWM_INT
RPWM_SNK<19ohm
PWM_TRI‐STATE

VCC

775ohm

PWM_TRI‐STATE_PULSE=1

475ohm

Figure 24. Block Diagram for PWM Tri-state

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

38
 RT3613EE

PWMx

PWM_TRI-STATE

PWM_TRI-STATE_PULSE
(Help quickly enter highZ state) 200ns 200ns

PWMx

Controlled by Controlled by Dr.MOS

RT3613EE or Discrete driver

UGATE

LGATE

Figure 25. Timing Chart for PWM Tri-state

System Input Power Monitoring (PSYS) Zero Loadline

The RT3613EE provides PSYS function to monitor total The RT3613EE also can support zero loadline function. It
platform system power and report to the CPU via SVID can be enabled by PIN-SETTING of Zero LL_EN = 1. When
interface. The PSYS function can be illustrated as in Figure zero loadline function is enabled, the output voltage is
26. PSYS meter measures system input current and determined only by VID and does not vary with the loading
outputs a proportional current signal IPSYS. RPSYS is current like loadline system behavior. RT3613EE adopts
designed for the PSYS voltage = 1.6V with maximum a new feature, i.e. AC-droop, to effectively suppress load
IPSYS for 100% system input power. 1.6V is a full-scale transient ring back and to controll overshoot well for zero
analog signal for FFh digitized code. loadline application. Figure 27 shows the condition without
AC-droop control. The output voltage without AC-droop
control has extra ring back ΔV2 due to C area charge.
Input Power
PSYS "Meter" Figure 22 shows the condition with AC-droop control. While
Source
loading occurs, controller temporarily changes VID target
Analog Current Signal
IPSYS (Indicates system total
to short-term voltage target. Short-term voltage target is
RT3613EE power) related to transient loading current ΔICC and can be
CPU SVID PSYS VPSYS represented as the following :
RPSYS Short_Term_Voltage_Target = VID − ΔICC x RLL

Figure 26. PSYS Function Block Diagram The setting method of RLL is the same as loadline system.
The short-term voltage target reverts to VID target slowly
after a period of time. The short-term voltage target can
help inductor current not to exceed loading current too
much and then the ring back can be suppressed. The
overshoot amplitude is reduced to only ΔV3.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

39
RT3613EE

B C
Inductor
A current

Loading Current ΔIcc

D

ΔV3

ΔV2
Output Voltage

VID Target
ΔV1

Figure 27. Zero Loadline without AC-droop Control

Inductor
current

Inductor
A current
Loading Current ΔIcc
D

Load

Output Voltage ΔV3

ΔV1 VID Target

Short-term voltage target

Figure 28. Zero Loadline with AC-droop Control

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

40
 RT3613EE
Acoustic Noise Suppression
VIMONICCMAX
RT3613EE support acoustic noise suppression function
 ICCMAX  DCR  RIMON,EQ
for reducing acoustic noise induced by Piezoelectric Effect RCSx
from MLCC. As output voltage transition, especially in VIMONICCMAX  1.6V
dynamic VID, the vibrating MLCC produces acoustic noise
And KSOCP = 1.3 and 1.6. It is set by Pin Setting Function
if the vibrating frequency falling into audible band and the
of SET3.
noise level is related to the output voltage transition
amplitude ΔV. Therefore, RT3613EE adapts acoustic noise Sum OCP threshold can be simplified as ISUM_OC,PS0 =
suppression function which is enabled by PIN-SETTING KSOCP x ICCMAX and ISUM_OC,PS1 = 0.5 x KSOCP x ICCMAX
of ANS_EN= 1 and Pin 31 pull to VCC. Table 17 is Acoustic when ICCMAX >= 45A. and ISUM_OC,PS0 = ISUM_OC,PS1 =
Noise Suppression function setting. KSOCP x ICCMAX when ICCMAX < 45A . While inductor
current above sum OCP threshold lasts 40μs, controller
de-asserts VR_READY and latches PWM in tri-state to
Table 17. Acoustic Noise Suppression Function turn off high-side and low-side power MOSFETs.
Setting
Acoustic Noise Per Phase OCP
SET2 Acoustic Pin 31
Suppression
Noise Suppression (ANS_EN) Per phase OCP is mainly for short circuit protection. Per
Function
Disable High Disable phase OCP threshold is directly linked with ICCMAX. The
Disable Low Disable relations between per phase OCP threshold, I _Max
Enable High Enable register setting and total phase numbers N are listed in
Enable Low Disable Table 18. While inductor current exceeds per phase OCP
threshold, PWMs high pulse are blanked until the inductor
current is pulled below per phase OCP threshold. If the
Over Current Protection (OCP)
POCP indicator keeps high for 40μs (with 10μs deglitch
The RT3613EE has two OCP mechanisms, sum OCP
), the controller de-asserts VR_READY and latches PWM
and per phase OCP.
in tri-state to turns off both the high-side and low-side
MOSFETs. OCP_SUM is masked during DVID period and
Sum OCP
80μs after VID settles. All of the OCP protections are
The threshold of sum OCP for PS0 is defined as
illustrated in Figure 29 and Figure 30.
ISUM _ OC,PS0
RCSx 1
 K SOCP  VIMONICCMAX  
DCR RIMON,EQ

PS1/2/3 sum OCP is defined as

ISUM _ OC,PS1
RCSx 1
 0.5  K SOCP  VIMONICCMAX  
DCR RIMON,EQ

While RIMON,EQ is designed exactly for

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

41
RT3613EE
Table 18. Per Phase OC Threshold
While RIMON,EQ design meets the following
conditions
ICCMAX (A)
Per phase OCP TH (A)
N
1.6V  ICCMAX  DCR  RIMON,EQ
RCSx

2.25  1.6V  RCSx  1 2.25  ICCMAX

31
N DCR RIMON,EQ N

2.625  1.6V  RCSx  1 2.625  ICCMAX

23 - 30
N DCR RIMON,EQ N

3.9375  1.6V  RCSx  1 3.9375  ICCMAX

18 - 22
N DCR RIMON,EQ N

5.25  1.6V  RCSx  1 5.25  ICCMAX

17
N DCR RIMON,EQ N

Mask sum OCP

VID 80us

Sum OCP threshold

Inductor Current

Inductor current>Sum OCP threshold

40us 40us
Sum OCP trigger
VR_READY

Figure 29. Sum OC Protection Mechanism

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

42
 RT3613EE

POCP_TH

Inductor
Current

POCP CMP <10us <10us

PWM

POCP Shuts Down Threshold

(POCP Counter=40us)
POCP Counter

VR_READY

Figure 30. (a). <10μs, the POCP Counter No Reset

POCP_TH

Inductor
Current

10us 10us
POCP CMP

PWM

POCP Shuts Down Threshold

(POCP Counter=40us)
POCP Counter

VR_READY

Figure 30. (b). >10μs, the POCP Counter Reset

Figure 30. Per Phase OC Limit Mechanism
Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

43
RT3613EE
Over Voltage Protection (OVP) The OV protection mechanism is illustrated in Figure 32.
The OVP threshold is linked with VID. The classification When OVP is triggered with 0.5us filter time, controller
table and waveform are illustrated in Table 19 and Figure de-asserts VR_READY and forces all PWMs low to turn
31. While VID = 0V in case of VR internal setting mode or on low-side power MOSFETs. After 60us from OVP
DACOFF or PS4, OVP is masked. When VID ramps up trigger, VID starts to ramp down to 0V with slow slew
from VID = 0V till the first PWM after VID settles, OVP rate. During the period, PWMx is not allowed to turn on.
threshold is 2.45V to allow not-fully-discharged VSEN.
Otherwise, the OVP threshold is relative to VID and equals
to VID+350mV with minimum limit = 2.23V. While
VID<1.88V, the OVP threshold is limited at 2.23V.

Table 19. Summary of Over Voltage Protection

Protection
VID Condition OVP Threshold Example Protection Action
Reset
VID = 0
(VRON = L or VR
OVP is masked
internal setting mode
or DACOFF or PS4)
DVID up period from
0V to 1st PWM pulse 2.45V VR_READY latched
after VID settles VCC/EN
low.
DVID period from VID+350mV VID = 2V, OVP
non-zero VID minimum threshold = 2.23V threshold = 2.35V
VID+350mV VID = 1.2V, OVP
VID≠0 threshold = 2.23V
minimum threshold = 2.23V

PWM

VID settle OVP threshold transition at 1st PWM after

VID settles

OVP Threshold

DVID UP from VID=0V 350mV

Minimum OVP= 2.23V

NO OVP
VID

0V

Figure 31. Timing Chart for Over Voltage Threshold

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

44
 RT3613EE
OVP Threshold

350mV +- 50mV

VSEN

0V

VR_READY

VID Down (Slow Slew rate)

60µs
Indicator

PWM

Figure 32. Over Voltage protection mechanism

Under Voltage Protection

All protections are reset only by VCC/EN toggle. UVP
When the output voltage is lower than VID-660mV with and OCP protections are listed in Table 20.
3us filter time, UVP is triggered and PWMx are in tri-
state to turn off high-side and low-side power MOSFETs.
UVP is masked during DVID period and 80μs after VID
settles. The mechanism is illustrated in Figure 33.

VSEN
VID
660mV
UVP Threshold

PWM

VR_READY

Figure 33. Under Voltage Mechanism

Table 20. Summary of UVP and OCP Protection
Protection Protection DVID Mask Protection
Protection Threshold
Type Action Time Reset
ISUM _ OC,PS0
Sum OC for
R 1
PS0  K SOCP  VIMONICCMAX  CSx 
DCR RIMON,EQ PWM tri-state,
VCC/EN
ISUM _ OC,PS1 VR_READY DVID+80us
Sum OC for non Toggle
R 1 latched low
PS0  0.5  K SOCP  VIMONICCMAX  CSx 
DCR RIMON,EQ
UV VID - 660mV

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

45
RT3613EE
4.0
Thermal Considerations Four-Layer PCB

Maximum Power Dissipation (W)1

3.6
The junction temperature should never exceed the
3.2
absolute maximum junction temperature TJ(MAX), listed
2.8
under Absolute Maximum Ratings, to avoid permanent
2.4
damage to the device. The maximum allowable power
2.0
dissipation depends on the thermal resistance of the IC
1.6
package, the PCB layout, the rate of surrounding airflow,
1.2
and the difference between the junction and ambient
0.8
temperatures. The maximum power dissipation can be
0.4
calculated using the following formula :
0.0
PD(MAX) = (TJ(MAX) − TA) / θJA 0 25 50 75 100 125
Ambient Temperature (°C)
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient Figure 34. Derating Curve of Maximum Power
thermal resistance. Dissipation

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WQFN-32L 4x4 package, the thermal resistance, θJA, is
27.8°C/W on a standard JEDEC 51-7 high effective-thermal-
conductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (27.8°C/W) = 3.59W for a
WQFN-32L 4x4 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 34 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

www.richtek.com DS3613EE-03 April 2020

46
 RT3613EE
Outline Dimension

1 1

2 2

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 3.900 4.100 0.154 0.161
D2 2.650 2.750 0.104 0.108
E 3.900 4.100 0.154 0.161
E2 2.650 2.750 0.104 0.108
e 0.400 0.016
L 0.300 0.400 0.012 0.016

W-Type 32L QFN 4x4 Package

Copyright © 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

DS3613EE-03 April 2020 www.richtek.com

47
RT3613EE
Footprint Information

Number of Footprint Dimension (mm)

Package Tolerance
Pin P Ax Ay Bx By C*32 C1*8 D Sx Sy
V/W/U/XQFN4*4-32 32 0.40 4.80 4.80 3.20 3.20 0.80 0.75 0.20 2.80 2.80 ±0.05

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

www.richtek.com DS3613EE-03 April 2020

48