NLS) UNIT- 2 nr BineaTIONAL Mos Logic circuits. [iy Static CMOS DESIGHN hy Bubble pushing ha, Compound goles deta edperk le Trpek OvcleAL ny 4 Atay rman c Ge he: Skouad gots 1.6 PN Aadsvc0s. a cettarpla Haestol vote TSH PSEUDO n-mMas. 713 RATIOED CIRCU) m & CM Tay cvse - Castode yoleage sub ich Logie , y\o- o Ean, BY Cs] DoOMWwo Logic 5.) Keepers Bo. Muwef output alone Logte 5.3, Np aomtho Logfe AL RAIL DOMINO Loic AMIC CiRciTs. (ej) Dv ANSISTOR Logie Cet) (ay Pass TR N GATES cTe) ce TRANS MIas(O) Co CPL - COMPLEMENTARY PAss “TRANSISTOR Piety. Dew pag. = DIFFERENTIAL ie ne «© Vol A SWwitcHt WITH Pass pnisisTOR Loate . Ser ee ~~DPL — Dovece [2 “cireviT PITFALLS 023 PoweR 132. STATIC PoweR 12.2 Dynamic POoweER 12.2. BHORT CrROWIT POWER 12.4, LEAK AGE PoweR, Igu5. Low POWER ARCHITECTURE . Comat TtoNet Mes Logic Circuits. one Re pret bol CRAB ee Lanai? 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Us pouryr emonk Str Pek to ett eae Bee ae he polle Jor Long time Can athiens. aoe pour AULTG. 5S TJols bekuen- cheps Coun Consume. power lie to he Louge capactttre lewd number of Chips R6 OU promursing Appnra bo redue Hhe power — Consemptas l> the voltoge ets ee rete | to veclrrr power LUM PEFON_aSir_eo_ rad ute Py Yeclture d_ a4 the VoLEaxge gs crecduady this neeoltobe dmpersatad| dor ureh- porate and Jor prpeliring, | |CPL — Compl ELTARY PASS TRANSISTOR . Logic. 2 Mentasy pars travnseor Logfe Coed leitadetental. paws Gramnder logrc fsmore transistors, add more area and capacitance, and has more possibility of error. ———— apcaclee S~ eaerentenen EO aity OL Crror Static CMOS is the most robust circuit family. Certain circuit pitfalls that can cause chips as sop to fail include oy Ve Vop- 5 30°F Threshold Dro \\p VE B N 3 DP FO) 8s Piet eae When an NMOS transistor gate terminal is connected to Vpp and the source terminal is connected to V_,,, the voltage at drai{terminal is Vpp— Vin. This effect is called s threshold drop. Pass transistors are good at pulling in a preferred direction, but only swing ta.within V, of the rail in the other direction. To overcome this, pass transistors must be replaced by full transmission gates or may use weak pMOS feedback transistors + to pull the output to VDD. — fore Ht rsd “sae Leakage meee > i 3 Leakage is caused by sub-threshold conduction, tunnelling and reverse-biased diode leakage. Multiple threshold voltages are used to improve performance in critical paths" and reduce leakage in other paths of the circuit. Sub-threshold leakage is worst for wide NOR structures at high temperature (especially during burn-in). Keepers must be sized appropriately to compensate for leakage.oe Noe we Chargesharing YOY! i & ee subject to problems with ¢ sharing. It is most serious when s lightly loaded and the internal capacitance is large. If the charge-sharing the output may flip and turn off the keeper, leading to, incorrect results, canbe overcome by precharging some or all of the internal nodes with the output i noise is large, Charge sharing | listing: ‘ secondary precharge transisto aA pow? | ee Power supply noise a / or A ; Vpp and Gyp are not constant across a. large chip. Both are subject to power supply noise caused by IR (DC voltage) drops and d/d noise. IR drops occur across the Tesistance R of the power supply grid between the supply pins anda block drawinga current I. d/d_noise occurs across the power supply inductance L as the current rapidly changes. Power supply noise hurts performance and can degrade noise margins. The Sey, mes Foe sy ihe rom nd cn dea te noise margin issues can be managed by placing sensitive circuits near each other and having them share acommon low-resistance power wire, pata) Hot spots eye bee GF ‘Transistor performance degrades with temperature, so care must be taken to avoid excessively hot spoje These can be caused by non-uniform Power dissipationéven when the overall power consumption is within budget. The non-uniform temperature distribution | leads to variation in delay between. gates across the chip. } se TS. Minority carrier injection a ee wv We can drive a signal momentaril: i ils) ei } ly Qutside the rails) either thr i coupling or through inductive eat ringing on /O drivers. In sucha case, the junctions betwee? | drain and body may momentarily become forward-biased, causing current to flow int the subsiggis- This effect is called minority carrier injection. Minoiity earsien saa problems are avoided by keeping injection sources away from sensitive ne UTR. ek Dynamic gates driving mini eet & gi € ; back-gate coupling effect. Back-gate coupling is lieaicnss gat a ae Susceptible to the therail. by driving the input closerto Back-Gate Coupling ES)Process Sensitivity a2 « iia 2 owe Fon parc On’, vr nner, Marginal circuits can operate under nominal process conditions, but ee in certain process corners or when the circuit is migrated to another process. Novel circuits should be simulated in all process corners and carefully scrutinized for any process sensitivities. They should also be verified to work at all voltages and temperatures, including the ee elevated voltages and temperatures used during burn-in and the lower voltage that might be used for ouppower versions of a part. _SoftErrors = Alpha particles and cosmic rays can disturb dynamic nodes. The probability of failure is reduced through large node capacitance and strong keepers.eee 2 TOR GRID Pass canine (A)a O GS Arow.ou0er apes bowcuvns cor ii | Prperfeck) bade pouring & 1 is See ee RS tine VB we aay PES Pa 5 foomautret te eget ee " branntstsx adeas * A pmes put degrade posing ererG | aval pmes FF ued nmMas Lae Be Oe pas ae. how s pm perses & >) bears v7 Cei)s Et 5 ue9=0,Gb=I(ore) owe oe at os 7A gL, gEeO oO SATS g=1, Sb=O e b a= gb-0 a ——— A 7 HAE | Fe? toa meson. goke By Corb ining am nmmos ancl Pmes tramnetsr || Se povedtel, we ebtarnr a Auftth thet. turns ON , her 0 ancl | fe appre Te “gl, me wren o's and~(s ane (parce tga a acepeable jashusn. i