Industrial Policy Committee - THAG

ON-BOARD COMPUTERS, DATA HANDLING SYSTEMS

AND MICROELECTRONICS
Roadmap Issue 5 rev. 2

Olivier Mourra, Agustin Fernandez-Leon

ESA UNCLASSIFIED - For ESA Official Use Only REFERENCE: ESA-TECH-HO-022386 1

Technologies Covered (1)

Every modern Spacecraft (satellite platforms, instruments and launchers) is equipped with On–Board Computers
& Data Handling Systems (OBCDHS). Microelectronic devices are present in all Satellites electrical systems.

The technologies covered in the OBCDHSM Technical Dossier are utilized in all ESA missions and beyond.

Combining three technology dossiers and maintain an easy to understand logic, has been very challenging.

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 2
Technologies Covered (2)

The dossier covers platform and payload data

handling including Microelectronics
technologies.

There are a number of synergies between Data

Handling Systems and Microelectronics.
However, Microelectronics also cover other
application areas.

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 3
Technologies Covered (3)

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 4
Technologies Covered (4)

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Key Issues
• Advanced Data Handling Architecture (ADHA) based on interchangeable and interoperable standardized
modules.
• Higher integration of OBC facilitated by multi-core SoCs and processors.
• Reduced and standardized interfaces of I/O modules for PF (RIU/RTU) and INS (ICU).
• Instrument Advanced Computing & Processing Modules (ICU) incl. AI/ML applications.
• Availability of European rad hard: ASIC tech platforms (DSM & UDSM), FPGAs, Microprocessors and
Microcontrollers, ASSPs (converters, front ends, HSSL), Digital and Analogue IP Cores.
• Advanced microelectronics high integration solutions (custom SiP, 2.5/3D, "chiplets")
• Evaluation & Mitigation techniques for reliable use of high performance COTS and rad tolerant Microelectronic
devices
• European Non-Dependence

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 6
State of Art in Europe (1)
This dossier covers too many products and European players for a comprehensive overview in this presentation.
A brief overview is presented here.
Product Companies

On-Board Computers ADS, TAS, RUAG, QS PNEXT, etc.

Solid State Mass Memories depending on COTS memories to reach ADS, TAS, DSI Aerospace Technology,
high storage capacity/high bandwidth required by state-of-the-art Teledyne E2V (rad tolerant memory),
instruments. 3D plus (memory modules), Syderal
Visual Monitoring Cameras Creotech, Crystal Space, Micro Camera
and Space Electronics, Neptec, OIP,
SSTL, TEMIS, TSD, 3D+, etc.
Modules in Data Handling Instrument Units (ICU/DCU) ADS, TAS, RUAG, Jena Optronik,
TERMA
ASIC / FPGA / IP design > 460 companies and institutions in
ICMdb
ASSP / processors / FPGA product & IP vendors ST, MCHP, TE2V, TI, Cobham, NX, 3D+,
IMEC, etc., etc.
ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 7
State of Art in Europe (2)
Capability and Gaps:
No major product gap are observed to cover current OBC and Data Handling needs. However, there are some
areas requiring attention in the microelectronics area to support High Speed Serial Links, Memory management,
higher integration, modularity and performance.

Key new technologies requiring increased focus concern:

• Development of the Advanced Data Handling Architecture and associated modules.
• Further development and increased utilization of the European latest generation (65-28nm)devices: BRAVE
FPGA product family, processors (GR740) and ASSPs
• Push for further development of European Ultra Deep Submicron Technologies and next generation devices
(22-7nm) to increase competiveness and non dependence of European Industry

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Competitiveness and Benchmarking (1)
OBCDHS
To remain competitive Data Handling Systems shall become more integrated and more standardized to meet the
needs of future markets.

The combination of new microelectronic technologies and the need of standardization will result in a disruptive
approach that ADHA is proposing.

OBCDHS shall be based on highly integrated modules, that can be interchangeable from different manufacturers,
and standardized to be re-used for several missions.

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Competitiveness and Benchmarking (2)
European space (rad hard) microprocessors, microcontrollers and FPGAs are well positioned w.r.t. non-European
counterparts, but challenge never stops.

Investment in US for UDSM technology for new space devices is much higher (linked to security and military).

Future generation European UDSM devices rely on international supply chains, wafer fabs in Asia (or USA) and
with critical European contributions in the supply chain: IC design and IP, assembly, packaging and test.

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 10
Mission Needs and Market Perspectives (1)
Identified program needs challenging the Data Handling Systems and Microelectronics, closely coupled to ESA
technology Targets

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Mission Needs and Market Perspectives (2)

Application Mission requirement Solution

EOP Increased platform synergy, Novel Advanced Data Handling Architecture

reduced development time, (standardisation, reduced development time and
instruments with high data cost reduction)
throughputs, possibility of real • Increased integrated functionality on OBC
time services, security and • Development of HSSL protocols, HW
autonomy. • Introduction of on-board processing including AI
in support of real time services
• High fidelity lower power processing HW.
• Increased on-board data storage
• Introduction of Security in DHS
• High capacity and high throughput SSMMs
• Multicore processors and high performance
FPGAs, high speed ADC/DAC solutions.

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Mission Needs and Market Perspectives (3)

Application Mission requirement Solution

SCI/EXP Exp: Strongly collaborative with Novel Advanced Data Handling Architecture resulting in
NASA. Reliable DHS and reduced development time and cost saving.
Communication solutions. Miniaturisation for rover type applications.
Resource reduction. Strengthening of TTEthernet (utilised also by NASA) for the
SCI: High performance and often Gateway.
specific instrument data Development of specific ASICs for SCI instruments.
processing solutions. Utilisation of European HighRel FPGAs in SCI/EXP
missions.
Higher platform functional Focus on instrument control units and high capacity
integration. SSMMs.
Availability of DHS for critical
application.

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Mission Needs and Market Perspectives (4)

Application Mission requirement Solution

TIA Flexibility and re-configurability Focus on Ultra deep Submicron technology foundation for
Generic satellites to be re- High performance ASICs and digital processors (enabling
purposed for evolving user needs. beam forming capability).
High speed serial link HW,
BRAVE FPGA family portfolio expansion including BRAVE
RF
Reduced data handling system cost and development time.

NAV Flexibility for signal in space Focus on UDSM ASICs and FPGAs in articular expansion
generation, antenna pattern of BRAVE FPGA portfolio including security and BRAVE
programmability power allocation RF.
flexibility, and security. Reduced data handling system cost and development time.

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 14
Mission Needs and Market Perspectives (5)
Market perspective by Euroconsult.
Four satellite products were considered for the market analysis.
• On-Board Computer (OBC) with RTU/RIU
• Solid State Mass Memory (SSMM)
• Visual Monitoring Cameras (VMC)
• Data Handling Instrument Units (DHIU)
A total of 11800 satellites are forecasted for launch in the next ten years. However, not all embark OBDHM products. The
table below quantify the number of satellites per year by product type (i.e. the satellites addressable by the products).

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Mission Needs and Market Perspectives (6)
Four products were considered for the two European launch vehicles market analysis.

Average of 50 units/year estimated to be required for the 2 launchers in the next 10 years:

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Mission Needs and Market Perspectives (7)

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 17
European Strategic Interest
In terms of Data Handling Systems, our industrial partners have reacted very positively to the Advanced Data
Handling concept (covers Architecture and modules). Important technology strides have been made with backing
of a significant portion of the industrial segment. Challenges remain but it is crucial to maintain momentum for a
successful outcome.

What concerns Microelectronics,

• The UDSM initiative is supported by our industrial partners. The will to collaborate on this important issue is
important with the potential to enable a highly competitive European Industry in particular in the
Telecommunication domain. UDSM is also considered significant also for NAV and EOP applications.
• The European FPGA is gaining traction but requires continuous support to the development, qualification and
utilization to achieve expected goals.

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 18
Previous Roadmap Implementation Status
Data Systems and On-Board
Computers - 2016 Roadmap

9 ESA activities of the 2016 Roadmap

have been approved (“Partially Funded”
or “Fully Funded”) for a budget of about
3.4 M€ (3,336 k€).

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 19
Previous Roadmap Implementation Status
On-Board Payload Data Processing -
2016 Roadmap

3 ESA activities of the 2016 Roadmap have

been approved (“Partially Funded” or “Fully
Funded”) for a budget of about 1.1 M€
(1,100 k€).

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 20
Previous Roadmap Implementation Status
Microelectronics – ASIC & FPGA -
2016 Roadmap

8 ESA activities of the 2016 Roadmap

have been approved (“Partially Funded”
or “Fully Funded”) for a budget of about
8.7 M€ (8,741 k€).

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 21
Additional activities

• 37 additional activities for an overall amount of 10.6 M€ in the Data Systems and On-Board Computers domain,
plus

• 29 additional activities for an overall amount of 10.7 M€ in the Microelectronics – ASIC & FPGA domain …

… that were not included in the respective 2016 roadmaps, but were approved and started / completed between
2016 and 2020.

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 22
Reference for Prioritisation
Adding all the ESA activities implemented from the previous 3 related roadmaps and the additional activities
implemented between 2016 and 2020, there is a total of 86 ESA activities amounting for a total budget of 34,5 M€
there is no reference budget for prioritisation.

The yearly reference is equal to the sum of the budget of all relevant activities approved since the previous
Roadmap (34.5 M€) divided by the number of years since then (4 years):

On-Board Computers, Data Handling Systems And

Microelectronics Yearly Reference Budget: 8.7 M€

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 23
Recap of Mapping Meeting
•Appraisal from all participants on the good quality and comprehensiveness of the dossier, and recognition of the
big effort by ESA in combining the 3 previous Avionics Hardware related dossiers;
•Large consensus on main technology key issues and product needs for the next years:
o ADHA (Advanced Data Handling Architecture) and Module-based systems
o Higher system integration, higher data processing and data storage capabilities, re-configurability in Payload and Platform
modules
o Investigating and introducing Artificial Intelligence / Machine Learning / Neural Networks processing
o Reducing costs and boosting data processing power by using COTS (and mitigation as needed) in "New Space" missions
o Consolidating European reconfigurable / reprogrammable multi-core components and tool ecosystem (BRAVE FPGA
family, LEON/ARM/RISC-V microprocessors, microcontrollers), promote its use, work in next generations (Ultra Deep
Submicron)
o Support existing and new developments of European Application Specific Standard Products (mixed-signal ASICs) such
as converters, detector front ends, high speed communication interfaces and transceivers for optical communications,
power control and conditioning IC, etc.
o Multi-die System-in-Package solutions for space for higher integration levels
o European non-dependence
ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 24
Proposed Development Approach
The combined total AIMs from the previous Dossiers amounted to 20. With the merge of topics, an effort was
made to reduce the number of AIMs to the following 10:

AIM A Define and adopt unified OBCDH architectures based on modules

AIM B Design, develop, manufacture and qualify buses, network and communication technologies
AIM C Design, develop, manufacture and qualify OBCDH modules (including AI and ML)
AIM D Develop Building Blocks to support OBCDH module(s) development(s)
AIM E Develop EGSE to support the test and integration of OBCDH units/modules
AIM F Enhance characteristics/functions of current ASIC Platforms and develop USDM ASIC Platforms
AIM G Improve and expand the European rad-hard FPGA family
AIM H Improve and expand the European rad-hard Microprocessors, Microcontrollers and DSPs
AIM I Improve and expand the European rad-hard ASSP family
AIM J Improve and expand the European IP Cores catalogue and respective Design Methods and Tools

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 25
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Curr. Targ. Start End Prog. another
(kEuro)
Ref. RM
Activity
Define and adopt unified OBCDH
AIM A architectures based on modules
ADHA-2 activity called Standardisation of ADHA Modules, follow up of the OBC, SSMM, Power Modules procurement.
ADHA CONSOLIDATION, Design and Test of the first ADHA EM unit.
STANDARDISATION, AND
PRODUCT SUITE DEVELOPMENT
with consortia one Other ESA Programmes Discovery or Preparation
A01 F 1000(OEP) TAS 2 6 2021 2023
ADHA-2 activity called Standardisation of ADHA Modules, follow up of the OBC, SSMM, Power Modules procurement.
ADHA CONSOLIDATION, Design and Test of the first ADHA EM unit.
STANDARDISATION, AND
PRODUCT SUITE DEVELOPMENT
with consortia two
A02 F 1000EOEP ADS consortium 2 6 2021 2023
ADHA unit qualification Continuity of the ADHA_2 activity to qualify the first ADHA unit containing EQM ADHA modules.
Parallel activities with several integrators to be envisaged. OBC/SSMM/PWR EQM modules
A03 procurement to be considered as a minimum. N M H 15000GSTP 6 8 2023 2025 A01, A02
ADHA Standards and Hand Book Provision of a draft ADHA standard and handbook, based on outputs from ADHA activities,
A04 compliant to ECSS format. N H M 50TDE TRL not applicable 2 6 2022 2023
OBC DHS electrical OBCDHS It is proposed to run an activity for identifying an OCBDHS Architecture meeting high reliability
architectures study for high requirements (incl. double failure requirements). Such missions are sample return, LOPG/Lunar,
reliability missions types. HSF. The challenge of this activity is to find a suitable architecture re-using existing modules (ADHA
included) to be compliant to the 2FT req. This is linked to ESA missions
A05 High availability (or high dependability at large) should be also addressed in this activity. N H H 1000GSTP classification. 3 5 2021 2024
Study of OBCDHS architectures The objective of this activity will be to assess, define and elaborate in detail on the use cases for
based on microcontrollers rad-tolerant/rad-hard mixed-signal microcontrollers in different space mission scenarios, and the
implications on the avionics/OBDH system level architectures.

Different space application scenarios and configurations using microcontrollers can also be
demonstrated, using COTS hardware. This is linked to ESA missions
A09 N H L 700TDE classification. 3 4 2022 2024
Standardisation of backplane Institutional National
A10 connector for nanosatellites Pin allocation and standardisation of the backplane connector PC104. N M M Programmes (INP) FR

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 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify buses, network and
AIM B communication technologies
WP2016 SpaceWire Network Development of a deterministic SpaceWire routing switch. Similar in function to deterministic Ethernet AIM B - Group 1: Established
Management Service Suite switches, this routing switch adds realtime capabilities to SpaceWire networks by implementing store- low/medium speed buses and
Definition and Validation (PTRP) and-forward, egress queues and different traffic shapers (Teletel, RUAG, Airbus, TAS-F) networks (MIL-Bus, CAN,
SpaceWire)
T701-
B01 R 450TDE GR Teletel (GR) 3 4 2020 2022501ED
EXPRO: SpaceWire Repeater The objective of this small TRP activity is to develop a small SpW repeater with Flight HW receivers such AIM B - Group 1: Established
Development the repeater can be used on a PFM or FM satellite/instrument for IF compatibility assessment. low/medium speed buses and
networks (MIL-Bus, CAN,
SpaceWire)
TSS20-
B02 R 47TDE AT SKYTECH (AT) 2 4 2020 202106ED
SpaceWire Time Synchronization Based on the previous development of time distribution and synchronisation capability for asynchronous AIM B - Group 1: Established
Protocol SpaceWire (SpW-TSP) and previous development of Deterministic SpaceWire (WP2016), develop time low/medium speed buses and
distribution and synchronisation capabilities for Deterministic SpaceWire (synchronous) networks (MIL-Bus, CAN,
B03 N H H 300TDE SpaceWire) 2 4 2022 2024
SpaceWire Network Management Based on the previous development of network management capability for asynchronous SpaceWire AIM B - Group 1: Established
(SpW N-Mass) and previous development of Deterministic SpaceWire (WP2016), develop network low/medium speed buses and
management capabilities for Deterministic SpaceWire (FDIR, Spacecraft mode related reconfiguration, networks (MIL-Bus, CAN,
B04 etc.) N H M 400TDE SpaceWire) 2 4 2022 2024
Galvanically Isolated SpW Physical Develop three solutions providing galvanically isolated SpW Physical Layer:
Layer 1) a solution backwards compatible with ECSS-E-ST-50-12C-Rev.1 (only the cable assembly is modified
and any electronics or optronics embedded in the cable assembly would have to be powered by external
means) | use-case = full legacy, e.g. for flight hardware
2) a solution allowing modification of ECSS-E-ST-50-12C-Rev.1 at PHY Level only (any electronics or
optronics embedded in the cable assembly, if required, could be powered through the new or modified
SpW connector) | use-case = new SpW Networks (new Node units and new Switch units) AIM B - Group 1: Established
3) a solution allowing modification of ECSS-E-ST-50-12C-Rev.1 at Signalling Level only (the connector is low/medium speed buses and
compliant to ECSS-E-ST-50-12C-Rev.1 but the signal in the cable assembly must be galvanically isolated networks (MIL-Bus, CAN,
B05 from the SpW CODEC) | use-case = legacy Node units connected through newly developed Switch units N M M 450TDE SpaceWire) 2 4 2023 2025
Elements of TTEthernet based This is the development of the Switch and End-System boards and the generic Avionics Hosting Unit that AIM B - Group 2: Ethernet and
Avionics : TTEthernet Switch , will be used in the Lunar Orbital Platform - Gateway avionics (not only the European side but across the Ethernet-based determinsitic
TTEthernet End System and whole space station). Outcome is qualified products, EMs apt for Avionics Test Bench and GSE. protocols (TTE, TSN)
TTEthernet Avionics Hosting Unit - GT17-
B06 Phase 1 R 1500GSTP AT TTTECH COMPUTERTECHNIK (AT) 4 5 2020 2021193ED
Elements of TTEthernet based This is the development of the Switch and End-System boards and the generic Avionics Hosting Unit that
Avionics : TTEthernet Switch , will be used in the Lunar Orbital Platform - Gateway avionics (not only the European side but across the
TTEthernet End System and whole space station). Outcome is qualified products, EMs apt for Avionics Test Bench and GSE. AIM B - Group 2: Ethernet and
TTEthernet Avionics Hosting Unit - Ethernet-based determinsitic
B07 Phase 2 N H M 1500GSTP protocols (TTE, TSN) 57 2021 2022 B06

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 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify buses, network and
AIM B communication technologies
De-risk assessment: TTE memory Aims to de-risk the development of the building blocks for the critical and non-critical mass memory units AIM B - Group 2: Ethernet and
Cpcimm for IHAB and ESPRIT avionics. In particular, the interface of the high capacity memory modules to TTE End- Ethernet-based determinsitic G617-
B08 System cards and the high capacity NAND-Flash dice. F 195GSTP protocols (TTE, TSN) 2 4 2021 2022241TAge
SpaceTSN Definition and The Time Sensitive Networking (TSN) is IEEE-standardized deterministic Ethernet solution. This standard is
Demonstration common to a wide range of high speed link technology with heavy support from major components
manufacturers. It has all of the Quality-of-Service features needed to implements reliable and robust mixed-
criticality networks needed by on-board communication in many ESA missions.
This activity encompasses the following tasks:
- Analysis, tailoring,selection and specification of TSN features, including Switch and communication nodes
in ADHA modules.
- Breadboarding and validation of TSN network based on COTS IPs for End-to-End communication System AIM B - Group 2: Ethernet and
and Switch compatible with cPCI-Serial-Space. Ethernet-based determinsitic T701-
B09 - Validation and demonstration of the SpaceTSN technology within a cPCI-Serial-Space rack. F 500TDE protocols (TTE, TSN) 2 4 2021 2022704ED
Ethernet4NGSpace Evaluation of avionics impact and benefits of Time-Triggered Ethernet (TTE) and Time-Sensitive Networks Polish Incentive Scheme
(TSN) for next generation spacecraft, with a focus on TSN. AIM B - Group 2: Ethernet and
Ethernet-based determinsitic
protocols (TTE, TSN)

B10 R 200TDE PL ITTI (PL) 2 4 2019 2021PL_218

Characterisation of passive General characterisation of inductors, connectors, cables for Ethernet so we have some knowledge in this AIM B - Group 2: Ethernet and
Ethernet components area. Investigation on the need of delta-qualification and commercial upscreening procedures will be Ethernet-based determinsitic Launchers, Human Spaceflight,
B11 invesitagated. Integrated solutions for connector+magnetics need to be assessed. N H H 400GSTP protocols (TTE, TSN) NewSpace 4 6 2022 2023
Characterisation of TSN-enabled The goal of the activity is to characterise possible COTS solutions that could implement TSN. COTS
COTS devices candidates would be coming from automotive market and could be an enabler for technological AIM B - Group 2: Ethernet and
demonstrators of TSN. Some components could already be identified (Microchip SAMV71-RT, KSZ8565 Ethernet-based determinsitic Launchers, Human Spaceflight,
B12 Switch), others could be evaluated (like switche from NXP ) N H L 200TDE protocols (TTE, TSN) NewSpace 2 4 2022 2024
Analysis and validation of TSN in The goal of this activity would be to analyse the standards in terms of determinism/timings/failure tolerance NPI/PhD
context of SAVOIR (NPI/PHD) etc., and also to validate/characterise TSN features with regard to SAVOIR Standard for Future Networks. Other ESA AIM B - Group 2: Ethernet and
Programme Ethernet-based determinsitic Launchers, Human Spaceflight,
B13 N H M 60s (OEP) protocols (TTE, TSN) NewSpace n/a n/a 2022 2025
Demonstration of functionality and Since number of TSN enabled devices are available in TEC-ED lab (incl. outcomes from various activities), the Small TRP-TAS
intercompatibility of TSN goal of this activity is to demonstrate interoperability of TSN devices coming from different manufacturers. AIM B - Group 2: Ethernet and
The outcome of thi activity would be small demonstrator. (Available devices/IPs: testbeds from SoC-e, Ethernet-based determinsitic Launchers, Human Spaceflight,
B14 hardware based on NetTimeLogic, Microchip SAMV71, hardware based on SevenSolutionTSN IP) N H M 50TDE protocols (TTE, TSN) NewSpace n/a n/a 2022 2022
WP2015 - Space-Fibre Interface Development of the RTL design of a SpaceFibre interface chip that bridges up to 12 SpaceWire ports, an AIM B - Group 3: High speed serial
Chip (PTRP) Ethernet port, a high-speed LVDS parallel port and several peripherals (GPIO, SPI, I2C, SMAP Xilinx link protocols (WizardLink,
Configuration) to a redundant 6.25 Gbps SpaceFibre port with SERDES. Including hardware validation on SpaceFibre, SRIO etc.)
FPGA. (STAR-Dundee, RUAG, Airbus, ISD) T101-
B15 R 600TDE UK STAR-DUNDEE (UK) 2 4 2017 2021401ED

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 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify buses, network and
AIM B communication technologies
RTG4 SerDes Irradiation Test Heavy-ion testing of on-chip SERDES of RTG4 including SpaceFibre IP core (Cobham Gaisler) AIM B - Group 3: High speed serial
Campaign for SpaceFibre link protocols (WizardLink,
Applications SpaceFibre, SRIO etc.)
TSS19-
B16 R 25TDE SE COBHAM GAISLER (SE) n/a n/a 2020 202102ED
2018 TRP SS Network Discovery andThe goal of this activity is to issue recommendations regarding the development of Network Management AIM B - Group 3: High speed serial
Configuration Protocol for capabilities for SpaceFibre. link protocols (WizardLink,
SpaceFibre SpaceFibre, SRIO etc.)

TRP Small Studies. 4000126

B17 R 25TDE IT INGENIARS (IT) n/a n/a 2019 2021296
Demonstration of SpaceFibre Implementation / demonstration of ESA's SpaceFibre and CCSDS image compression IP cores on RTG-4 Polish Incentive Scheme - SYDERAL
Technology Usage for Image Polska
Processing Applications Other ESA AIM B - Group 3: High speed serial
Programme link protocols (WizardLink,
B18 R 200s (OEP) PL SpaceFibre, SRIO etc.) 2 4 2019 2021PL_274
FiMan - SpaceFibre Network Development of Network Management capabilities for SpaceFibre. Polish Incentive Scheme - ITTI
Management Other ESA AIM B - Group 3: High speed serial
Programme link protocols (WizardLink,
B19 R 240s (OEP) PL SpaceFibre, SRIO etc.) 2 4 2019 2021PL_171
HSSL General: Development of a This would include the development of the required test tools such as jigs, reference backplane AIM B - Group 3: High speed serial
physical test specification for link protocols (WizardLink,
B20 SERDES-based protocols N H H 500TDE SpaceFibre, SRIO etc.) 2 4 2022 2023
HSSL General: Environmental Nothing is known about the radiation performance of on-chip SERDES on COTS and rad-tolerant FPGAs such AIM B - Group 3: High speed serial
testing of COTS SERDES and other as Xilinx UltraScale. In addition, there might be commercial HSSL devices such as repeaters and CML link protocols (WizardLink,
B21 HSSL components crosspoints with good radiation performance, which would be worth to test. N M M 200TDE SpaceFibre, SRIO etc.) 2 4 2023 2024 B20
SpaceFibre: Network Management SpaceFibre has all required building blocks to implement reliable high-speed networks. Network AIM B - Group 3: High speed serial
management aspects (time synchronization, unified configuration space) were defined in various activities link protocols (WizardLink,
B22 but are not standardized yet (e.g. could lead to revision of ECSS standard). N M M 200TDE SpaceFibre, SRIO etc.) 2 4 2023 2024
SpaceFibre: Investigation of other SpaceFibre is based on 8b/10b coding, which is compatible with WizardLink and offers best DC-freeness.
encoding schemes However, for some applications, encoding schemes with less overhead such as 64b/66b are required. This AIM B - Group 3: High speed serial
small activity could investigate possibilities to re-code the data without deep modifications of the SpFi link protocols (WizardLink,
B23 protocol stack. N M L 50TDE SpaceFibre, SRIO etc.) 2 4 2023 2023
Investigation of Radiation To build a first design of a Radiation Tolerant UWB Transceiver for interlink satellite communication and to AIM B - Group 4: Others links
tolerances and designs of Ultra test the first prototype. (Wireless, Powerlink)
Wide Band wireless solutions. T401-
B24 R 600TDE DE IHP (DE) 3 4 2021 2022601ED
WAIST-3 The purpose of the present proposal, named WAIST-3 is to be a continuation of WAIST-2, with the goal to Romanian Incentive Scheme -
industrialize the production of the Wireless T/C Node Other ESA CONTROL DATA SYSTEMS (RO)
Programme AIM B - Group 4: Others links
B25 R 205s (OEP) RO (Wireless, Powerlink) Ground segmanent in test centers. 5 6 2020 2021RO_78

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 29
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify buses, network and
AIM B communication technologies
WISAT-3 The scope of Wireless Communication Bus for SATellite Applications Phase 3 (WiSAT3) project is to develop Romanian Incentive Scheme - In low and medium speed data
a SpW to UWB wireless interface unit (WIU) engineering qualification model (EQM) designed to implement Other ESA CONTROL DATA SYSTEMS (RO) rates for intraspacecraft
intra spacecraft UWB wireless connections. Programme AIM B - Group 4: Others links communications. In addition, high
B26 R 526s (OEP) RO (Wireless, Powerlink) applicability in Launchers. 5 6 2020 2022RO_79
Follow-up: Wireless activity with Currently, the development of radiation tolerant wireless IC is being performed. Initially, the activity is
the title "Investigation of Radiation focused on the RF, analog and some digital parts of the front end IC. The next phase is to improve the design Other ESA AIM B - Group 4: Others links
Tolerances and Designs of Ultra based on the results acquired in the first attempt and to include more digital parts in the IC. Programme (Wireless, Powerlink); Potentially
B27 Wide Band Wireless Solutions" N H L 600s (OEP) under GSTP 5 6 2022 2024 B24
Development of an FPGA-based The DTN implementation shall cover the BP specification, allowing dynamic routing of traffic through
DTN+CFDP implementation different ground stations and automatic reconstruction at the MOC. The core shall aim asynchronous
optimised for high-speed file data implementation in high performance MMUs with direct access to the TM chain for data and TC routed via AIM B - Group 4: Others links
B29 downlink in CFDP Class I and Class II the OBC for return control traffic. N H M 500TDE (Wireless, Powerlink) 1 3 2022 2024
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
De-risk assessment: Computer The activity aims to increase the TRL of a low-power COTS-based hot-redundant OBC for Exploration
Module Maturation Campaign missions, which is fruit of precedent development. The Contractor will produce an engineering model able
to verify some of the key functions under target evironmental conditions, and the activity will finish with a
Test Readiness Review of such module. The developmend will focus on component selection, electronics
board re-design, thermal and mechanical analysis. Original baseline is centered in SmartFusion2 SoC, DDR3,
MRAM, NASA cFS software and custom inter-module link.
OBC Module
The awarded Contractor is Planetary Transportation Systems (PTS), who has taken on the task of developing G617-
C01 an OBC for its ALINA lunar lander and lunar rover. R 150GSTP DE PTS JENA (DE) n/a n/a 2020 2021241TAel
COTS-based highly integrated The activity is about the design and development of an OBC Processing Module based on COTS components,
computer system for mini/nano namely the Zynq UltraScale+.for high processing power and Microchip PolarFire for critical functionality. A
satellites cPCI serial space ADHA module is being developed with TRL4 target at the end of the activity.

Zynq UltraScale+ integrates very interesting features for use in space such as processor lockstepping and
ECC in memories and, in addition, has lately presented a workaround solution for its survivability under LEO
radiation environment. There is a lot of interest from both sides of the Atlantic to perform developments OBC Module
based on this component. A follow up could be towards use of upgraded components, qualification of the GT17-
C02 OBC and a flight opportunity. R 800GSTP DE EVOLEO TECHNOLOGIES (DE) 2 5 2020 2022021ED
On-board control unit for ICE Cubes The objective of the activity is to develop On-Board Control Unit that can interface a number of ESA/ESTEC
experiments internal experiments and, as a full package, will be flown on board of Ice Cube Facility. OBC Module
The outcome of the activity will include two PFM models of Control Unit - those models are planned to be GT17-
C03 used to interface experiments on-board of ISS. R 200GSTP PL N7 Space (PL) 4 6 2020 2022201ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 30
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
Single Board Computer. Phase 3 The objectives of the Single Board Computer Core - Phase 3 (SBCC-3) activity are to implement the CREOLE
ASIC, which integrates all the RM/TM/TC/OBT/PM functions and forms the core of RUAGs highly integrated
single board computer. The CREOLE ASIC will be validated in a purpose built board, SW drivers and bootcode
will be developed/updated, a power supply module will be developed, and these modules will be assembed OBC Module
into an OBC unit. Basic system level assembly, integration and validation tests will be carried out for this GT1Z-
C04 new CREOLE based OBC. R 3400GSTP SE RUAG SPACE (SE) 3 6 2016 2021503ED
Generic digital board development The objective of this activity is the development of a processing module based on the NanoXplore NG-ULTRA
for a Next Generation (NG) On- SoC FPGA. This PM will be the core of the next generation computer product line from ADS. It will be
Board-Computer targeted for use in OBC, Instrument Control Units (ICU), Mass Memory controllers and Payload Interface
Units (PLIU), taking advantage of the high processing power and the versatility provided by the NG-ULTRA
SoC FPGA. The deliverables of this activity will include an EBB of the generic PM, along with its OBC Module
demonstration SW. GT27-
C05 R 1500GSTP FR Airbus DS (FR) 2 4 2020 2022043ED
De-risk assessment: High data-rate De-risk assessment: High data-rate bus for Cubesat OBC Module
bus for Cubesat G617-
C06 R 200GSTP UK Open Cosmos (UK) n/a n/a 2020 2021241TAew
ADHA On-Board Computer Module The objective is to develop the OBC module to be used in an ADHA unit. This activity includes the delivery of T701-
C07 (AOBCM) the module EDS. F 500TDE OBC Module 2 6 2020 2022703ED
Fault-Tolerant and Commercial Off The objective is to develop a reconfigurable avionics architecture based on COTS components, such as a
The Shelf-based On Board Xilinx MPSOC (Zynq 7000) for most of OBC functions, combined with a rad-tolerant FPGA (Microchip OBC Module
C08 Computer (P0) ProASIC3) for the critical functions R 1000ARTES IT ARTES AT. SITAEL (IT) 2017 20214A.060
Reconfigurable System-on-a-Chip The objective is to develop a reconfigurable avionics architecture based on COTS components, such as a
for Future Telecom Constellations Xilinx MPSOC (Zynq 7000) for most of OBC functions, combined with a rad-tolerant FPGA (Microchip OBC Module
C09 (APSoC) ProASIC3) for the critical functions R 1000ARTES IT ARTES AT. SITAEL (IT) 3 5 2020 20224G.024
Activity supporting the Completion of the development of 2 OBC modules (N+R) based on the brave ultra. This activity includes the
development and qualification of 2 delivery of the module EDS.
ADHA OBC modules (N+R) based on EC prg
C10 the Brave Ultra. N H H 1500GSTP OBC Module 3 8 2021 2023 DAHLIA
Activity supporting the qualification Completion of the development of 2 OBC modules (N+R) based on the GR740. This activity includes the
of 2 ADHA OBC modules (N+R) delivery of the module EDS.
C11 based on the GR740. N H H 1500GSTP OBC Module 3 8 2021 2023
Reference design and basic Reference design for an OBC board based on GR740. Flight board design will be distributed as open source OBC Module
software for a single board with documentation. Breadboard manufacture and test T701-
C12 computer based on GR740 R 600TDE SE COBHAM GAISLER (SE) 2 4 2019 2022603ED
Assessment of FPGA-based RISC-V The goal of the activity is to assess (and breadbord) On-board Computer for CubeSat application based on
OBC for CubeSat FPGA and RISC-V. Potential FPGA suitable for such application is Microchip Polarfire FPGA. The main
outcome of this activity would be feasability study including trade-off with other solutions, power/mass
C14 budget and some example applications. The activity should include EM model of the board. N H M 500GSTP OBC Module 2 4 2021 2022
ADHA processing module based on The goal of this activity is to develop a processing module based on the Risc V and compatible to ADHA. This
C15 RISC V processor activity includes the delivery of the module EDS. N M H 500GSTP 1 6 2024 2025

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 31
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
OBC for Suborbital rocket Scalable and distributed on board computer for suborbital rockets and micro launchers
The OBC will provide real time telemetry, mass memory storage, guidance navigation
and data acquisition for suborbital rockets and micro launchers Due to its modularity and Institutional
scalability the computer will be adjustable to certain mission scenario s The computer will National
be compatible with different flight control systems It will also act as a service module to Programme LRN Institute of Aviation
C16 commercial or scientific payload carried on board of ILR 33 AMBER 2 K rocket. R 0s (INP) PL OBC Module internal funds of the entity 1 6 2018 2021
ANTELOPE: On-board computer The project aims at creating an innovative OBC for Nano and Microsatellites with increased resilience POIR 01
with predictive maintenance against radiation effects and equipped intelligent subsystem fault detection and isolation functionality Other 01 01
European 00 0853
Institution NCBR (The National Centre for R&D KP
Programme - EU Project) Labs
C17 R 2300s (OEIP) PL OBC Module 1 9 2020 2023Ltd
FURYO - File management based Development of a flash-based MMU with two WizardLink Inputs/Ouputs and 4 Gbps concurrent read/write Solid State Mass Memory Module
Ultraperformance mass memoRY throughput rate. Software developed by CS. GT27-
C18 for On-board R 720GSTP FR STEEL ELECTRONIQUE (FR) 4 6 2019 2021035ED
ADHA Mass Memory Module (A3M)The objective is to develop the SSMM module to be used in an ADHA unit. This activity includes the delivery T101-
C19 of the module EDS. F 500TDE Solid State Mass Memory Module 2 4 2021 2022701ED
​Memory control sub-system for ​Development of a DDR4/DDR3 memory controller implementing advanced coding schemes providing
low earth orbit applications protection against SEUs, MCUs and seamless recovery from memory component SEFIs. The activity will
target Zynq UltraScale+ and Zynq7000, making use of selected DDR4 memory components. The validation
C20 phase will include characterization of the design under radiation F 700ARTES Solid State Mass Memory Module 2022 20244G.035
De-risk assessment: Next The activity aims to analyse the current generation and capture the requirements for the next generation
Generation Remote Interface Unit Remote Interface Units, with the final objective to define a baseline architecture for the a future product
Architecture line. The development has five differentiated parts:

-1. analysis of the current generation

-2. requirements survey

-3. next generation RIU requirements definition

-4. architecture trade-off

-5. key driving parameters demonstration

The outcome will be a form of TRL3 fasibility architectural assessment, key components, technologies and
target generic IO modules. RTU/RIU Modules
G617-
C22 The awarded Contractor is RUAG Finland (ex-PATRIA). R 200GSTP FI RUAG SPACE (FI) 2 3 2020 2021241TAdp

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 32
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
picoRTU system - Detailed Design The main primary objective is to implement and validate a miniaturized intelligent distributed remote RTU/RIU Modules
and Qualifications - Phase 1 - CCN terminal system, called picoRTU, based on modular off-the-shelf units for space applications GT17-
C23 follow on de-risk R 400GSTP SI SKYLABS (SI) 5 7 2020 2021401ED
Prototype Remote Interface Unit The objective of this activity is to define, design, develop
(RIU) for SWE hosted payloads and prototype compact, versatile and modular payload control and data handling unit (PCDHU) for hosted
payloads (HPL) suitable for various Space Weather missions.

The key features of such unit are:

1 - To adapt electrical interfaces, protocols, time distribution and data buffering, processing and
packetization of various serial TM/TC interfaces implemented in HPLs to platform architecture in use.

2 - To distribute and isolate power to HPLs and their heaters

RTU/RIU Modules
3 - To offload FDIR and reconfiguration task of the HPLs from the platform GT18-
C24a R 650GSTP FI RUAG SPACE (FI) 4 6 2020 2021001ED
Prototype Remote Interface Unit ESA has, since the start of the PCDHU project, requested Power Distribution Module (PDM) development to RTU/RIU Modules
(RIU) for SWE hosted payloads be extended to EQM level to meet Lagrange mission’s expectations related to technology TRL level. The GT18-
C24b (CCN) scope includes Auxiliary DC/DC converter and Power Distribution functions. R 250GSTP FI RUAG SPACE (FI) 4 6 2021 2021001ED
ADHA Generic I/O Module The objective is to develop a generic I/O module to be used in an ADHA unit. This activity includes the
C26 delivery of the module EDS. N H H 500GSTP RTU/RIU Modules 2 4 2022 2024
ADHA I/O Propulsion Module The objective is to develop a generic HW module to be used in an ADHA unit to interface a propulsion sub-
C27 system (valves, heaters, etc.). This activity includes the delivery of the module EDS. N H M 500GSTP RTU/RIU Modules 2 4 2022 2024
ADHA I/O Module for driving AOCS The objective is to develop a generic HW module to be used in an ADHA unit to interface AOCS
sensors and actuators (as previous sensors/actuators. To be coordinated with the ADHA I/O Generic Module development (C26).
C28 RTU modules are doing) This activity includes the delivery of the module EDS. N H M 500GSTP RTU/RIU Modules 2 4 2022 2024
ADHA Motor Drive Electronic The objective is to develop a generic Motor Drive module to be used in an ADHA unit to control motors to
Modules (to be used ADHA ICU be used in instruments (scan mechanisms) or other mechanisms (Antenna pointing mechanism). This activity
C29 unit). includes the delivery of the module EDS. N H M 500GSTP RTU/RIU Modules 2 4 2022 2024
ADHA Step Motor Drive Electronic The objective is to develop a generic Step Motor Drive Electronic module to be used in an ADHA unit to RTU/RIU Modules. To be in
C30 Modules control SADM motors. This activity includes the delivery of the module EDS. N H M 500GSTP collaboration with CD4. 2 4 2022 2024
ADHA I/O Module based on Data The objective of this activity is to develop an I/O module using Data concentrator technlogies (like Power
C31 Concentrator Technologies Link) in order to minimise the number of I/O electrical IF of the module. N H H 750GSTP RTU/RIU Modules 2 4 2022 2024
High Performance Reconfigurable This activity targets a reconfigurable processing module based on the ADHA / cPCI serial space backplane
Processing Module (HiPeR-Pro) standards. The module will include reconfigruable elements that are flexible to different work-loads (EO and
Science applications). Based on RHBD components. Final delivery will be a electromechanically On-board Processing Modules - GT17-
C32 representative module using the standard backplane. F 1000GSTP DE Digital Processing Modules 3 5 2021 2022022ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 33
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
Space Qualification and reference The activity has three major objectives.
designs for Myriad Video Processor
- Architecture for In-Orbit AI - CCN1 - Continue the radiation characterization of the Myriad2 which was initiated in a predecessor activity,

- Generate a framework for improving models used in flight, perform image analysis, perform model
training

- Deliver a reference design board which based on Myriad 2.

On-board Processing Modules -
Digital Processing Modules
GT17-
C33 Expected TRL is 4 for both the board and the SW framework R 270GSTP IE Jaliko (IE) 4 7 2020 2022165ED
Improving radiation tolerance in Activity aims to increase the fault-tolerance due to radiation effects of an existing heterogenous processing On-board Processing Modules -
heterogeneous computing for data modules based on COTS FPGAs (Microsemi SmartFusion2 and PolarFire) and embedded GPUs. A combined Digital Processing Modules
processing (IMPRO-DP) HW/SW approach will be used for the FDIR approach. Two AMD GPU devices will be radiation tested (TID GT27-
C34 and SEE, protons) during the activity. The output will also be included in two IOD missions during 2021. R 250GSTP SE UNIBAP (SE) 4 6 2020 2021052ED
Dependable Avionics Processing The latest Multi-processor Systems-on-Chip (MPSoC) are providing an unprecedented level of performances
Module using COTS Reconfigurable that many space application were missing so far. These programmable devices (e.g. Xilinx Zynq family)
Systems-on-Chip provide very high levels of integration featuring multiple processing cores, digital signal processing (DSP)
elements, Field Programmable Gate Array (FPGA) fabric, large on-chip memories and various types of
communication interfaces on the same chip. These devices demonstrate promising performances for space
applications, but they exhibit susceptibility to radiation. Fault-Tolerant design mitigating these radiation
effects is needed to support these devices. To this end, the module design includes: the LUCA ASIC especially
suitable to support the MPSOC coupled to a Flash-based FPGA (e.g. Microchip PolarFire). Both chips are
used to implement critical functionality and the MPSoC supervision (e.g. Heartbeat monitoring, alarm
handling, LUCA power cycling etc.). The proposed reference avionics processing module will be suitable for On-board Processing Modules - T701-
C35 use in different mission scenarios without further handling related to the mission radiation environments. F 750TDE Digital Processing Modules 2 4 2022 2024705ED
FPGA accelerated DSP payload data The activity targets to develop a high-performance processing module for EO applications, using a modular
processor board and scalable approach. The module is based on the Xilinx Kintex Ultrascale KU060 FPGA for interfacing
(several HSSL / SpiFI and SpW on front-panel and backplane) and hyperspectral compression (CCSDS 123.0-
B-1). The module also includes 3x COTS Myriad2 processors on FMC mezzanine boards (other processors
possible as well) that are optimized for machine vision applications. The FPGA includes a TMR voting On-board Processing Modules -
mechanism for the output of the COTS processors. The board also includes a GR716 rad-hard Digital Processing Modules
microcontroller for monitoring of the FPGA and Myriad devices, as well as the scrubbing of the FPGA T101-
C36 configuration memory. R 500TDE SE COBHAM GAISLER (SE) 2 4 2019 2022501ED
Miniaturized DSP / Processor Board The activity aims to develop a miniaturised processing module / system in package for future use in On-board Processing Modules -
for Science and Robotic Exploration miniaturised instrumentation and robotics. The module is based on bare-die mounting of major elements, Digital Processing Modules
using Bare-Die-on-PCB Mounting such as FPGA and system controller. The module also includes working memory, non-volatile memory (for T201-
C37 Technology applications storage) and POL voltage regulation. R 400TDE PT ACTIVE SPACE TECHNOLOGIES (PT) 3 5 2019 2022034ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 34
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
​Adaptive compute acceleration The activity aims at assessing new types of components which includes both processors, FPGA fabrique with
platforms ​for satcom high-performance DSP elements -- as well as dedicated hardened accelerators for highly parallel loads for
applications in 5G processing and ML inference processing. Possible components include the Xilinx Versal
device families. The activity includes radiation testing of the selected components (both TID and SEE, heavy-
ions) as well as the development of a prototype board for telecom processing applications, with a demo
using ML processing on emulated telecom data (e.g. CNN processing of spectrograms for interference On-board Processing Modules -
C38 detection / signal analysis). F 800ARTES Digital Processing Modules 3 4 2022 20245C.435
Synthetic vision module based on The activity aims to develop a CoProcessor board for vision based navigation algorithms, with potential use
GR740 in rover exploration.
The activity shall raise the TRL level up to at least 6 w.r.t.:
- manufacturing processes
- BOOT SW development
- HDSW development On-board Processing Modules -
C39 N H M 700GSTP Digital Processing Modules 3 6 2022 2024
ADHA Processing Module based on The development of an ADHA compliant processing module based on a highly parallel processor, such as a
COTS Parallel Processor GPU or Kalray MPPA, to support standard open processing frameworks such as OpenCL or OpenMP for high-
performance and flexible software-based processing. The module shall include a high-capacity FPGA for
interfacing through HSSL and SpW, CAN etc. The FPGA shall also monitor the parallel processor for SEFIs
(and potentially SEL) and manage the FDIR of the module. The architecture shall ensure safe booting of the
COTS device, and keep the boot software in protected memory. Techniques for the mitigation of SEU effects On-board Processing Modules -
C40 shall also be developed. N H M 600GSTP Digital Processing Modules 3 6 2022 2023
Intelligent Space Camera The targeted product is an intelligent Space camera that integrates state-of-the-art image quality with real- Spacecraft Monitoring Module G617-
C41 time Artificial Intelligence (AI) analysis of the video stream, using COTS technology. R 300GSTP Ubotica 2 8 2021 2023241TAgt
Development of Cubesat The goal of this activity is to develop a processing module on a CubeSat-compliant form factor based on the
Processing Module based on Versal latest high-performance Versal ACAP/FPGAs that include both high-performance DSP blocks, ARM
FPGA processors, and dedicated accelerators for ML and 5G processing loads. The device has a report increase in
performance of a factor of 5x compared to previous generation, Zynq UltraScale+.

In the activity, a specific component has to be selected for the processing module, taking the size, power
and thermal constraints of CubeSats into account.

Note: the radiation testing of the Versal FPGA has been funded through ARTES AT and will take place during On-board Processing Modules -
C42 2021/2022. The CubeSat module shall be based on the radiation results in the ARTES activity. N L M 300GSTP Digital Processing Modules
ADHA Module to increase in-flight The objective is to develop an ADHA module that allows to learn more about satellite behavior in flight. This
satellite knowledge module could contain digital and anlog electronics to support for instance Solar Array in flight I/V curve
characterisation, micro-vibration measurments, etc.
Spacecraft Monitoring Module, to
support of ESA knowledge
management effort and in
C44 N H M 500GSTP collaboration with CD02 and CD4. 2 6 2022 2023

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 35
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Design, develop, manufacture and
qualify OBCDH modules (including
AI, ML and COTS with adequate
AIM C radiation mitigation techniques)
ADHA GNSS Receiver Module (if not Development of a specific EM ADHA module for GNSS receiver. This development was suggested by industry GNSS Receiver Module
integrated in the OBC) in ADHA_1. he EM should cover the full GNSS receiver implementation, including RFFE and SW/FW this activity falls within the scope of
the Onboard Radio Navigation
Receivers harmonisation roadmap,
it is traced here until the Onboard
Radio Navigation Receivers
C46 N H H 1200GSTP harmonisation will be updated 2 6 2022 2024
LION LION is a data processing unit (DPU) that allows conducting close proximity operations through vision based
relative navigation between two spacecrafts for active debris removal and in-orbit servicing activities LION
DPU is composed of high performance COTS components that satisfy processing power, high reliability and
C47 memory bandwidth demands for vision based navigation applications. N H L 250GSTP PL KP Labs Ltd. 3 4 2021 2022
ADHA Instrument Power The objective is to develop a generic Power Distribution Module to be used in an "ICU" ADHA instrument
Distribution Module (to be used in unit, to control on/off heater lines, and distribute power via protected power lines (with LCLs) to supply Instrument Module, in
C48 ADHA ICU unit). other instrument units. This activity includes the delivery of the module EDS. N H M 500GSTP collaboration with CD04 2 4 2022 2023
Live Support Interface Board for The goal of the acitviy is to develop power/data interface board to connect CubeSats hardware to standard
CubeSats ESA missions. The interface board will primarily protect the spacecraft against failures propagation from the
external CubeSats hardware. The board will be implemented with rad hard electronics and it will include
C49 power and data electrical protections and conversion if required. N L M 400GSTP CubeSat Interface Module
Activity supporting the qualification
of 2 ADHA Mass Memory Module
C50 (A3M) (N+R or N+ Ext). Activity supporting the qualification of 2 ADHA Mass Memory Module (A3M) (N+R or N+ Ext). N M H 1000GSTP continuity of C19. 4 8 2023 2025
Develop Building Blocks to support
OBCDH module(s) development(s)
AIM D
Reliable functional blocks for Implementations of critical OBC functions in reliable (RH/RT) technologies for use in COTS based OBCs. Other ESA GSTP or ARTES
critical functions in COTS based Functions may include TM,TC, Reconfiguration, Watchdogs, SEFI monitoring (SEL supervision?). Programme Activity to support OBC module
D01 OBCs Generic study on generic OBC building blocks to be used later on on OBC modules. N H M 800s (OEP) development 3 5 2022 2023
Building blocks for energy The activities here are related to missions that have for example to survive lunar night. Building blocks
constrained missions foreseen, identified in CDF studies (e.g. EL3 CPE) are ultra low power timers and ultra low power data
logging systems for logistics missions. The activity will also be linked with the current design of OBCs to Activity to support OBC module
verify waking-up strategy and to conclude on low power/energy computer for lunar night survival with the development, in collaboration
D02 least impact on other subsystems (Power, Thermal). N M M 800GSTP wioth CD04. 3 5 2023 2024
Reference designs and radiation Activity including the development building blocks based on COTS as for example memory controllers ARTES/GSTP/TDE (COTS WG)
characterisation of board based on (SDRAM, Flash). This includes design risk mitigatation, development and verification time reductions. Other ESA Activity to support OBC module
COTS components (functional Programme development, in collaboration with
D03 blocks for COTS-based computers) N H L 600s (OEP) CD01 and COTS WG2/3. 3 5 2021 2023

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 36
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Develop Building Blocks to support
AIM D OBCDH module(s) development(s)
Machine learning application This activity consists in assessing potential COTS devices (processors, VPUs, GPUs, processor array) that could Activity to support ML HW
benchmarking on COTS inference support ML applications. applications & processing GT1I-
D04a processors R 600GSTP modules 2 4 2021 2023302ED
Machine learning application This activity consists in assessing potential COTS devices (processors, VPUs, GPUs, processor array) that could Activity to support ML HW
benchmarking on COTS inference support ML applications. applications & processing GT1I-
D04b processors - Parallel contract R 600GSTP modules 2 4 2021 2023302ED
AI for non mission critical on board The proposed activity aims at investigating the use of ML-based algorithms to improve the autonomy and the Activity to support ML HW
data processing management efficiency of onboard payload data. applications & processing GT1I-
D06 Benchmark applications/algortihms/maps on target HW R 1000GSTP modules 4 6 2021 2023305ED
Robust machine learning systems The objective of the activity is to build a machine that is able to learn from its mistakes or errors in a dynamic, and Activity to support ML HW
for dependable space applications hazardous environment (launch, cruise, mission, hybernation). applications & processing GT1I-
D07 R 600GSTP modules 2 4 2021 2023306ED
Set-up of reference benchmark for Definition of a standardised Data Sets to provide later a scenarii of reference for evaluating HW ML Activity to support ML HW
evaluation of Neural Networks implementations. Priority 0. applications & processing
D08 N H H 600GSTP modules 3 6 2021 2022
Benchmark FPGA/IP to accelerate Benchmark existing FPGA/IP to accelerate ML for space applications. Priority 1. Activity to support ML HW
ML for space applications applications & processing
D09 N H M 800GSTP modules 3 5 2021 2022
Benchmark COTS HW accelerators Benchmark COTS HW accelerators to support ML for space applications. Priority 1. Activity to support ML HW
to support ML for space applications & processing
D10 applications N H M 600GSTP modules 35 2022 2023
Evaluation/Assessment of Neural Evaluation of a new implementation concept with low power consumption. P2 - investigation Activity to support ML HW
Morphic techniques (spiking applications & processing
D11 computing) N H M 400TDE modules 2 4 2022 2023
Nonlinear channel modelling and The main objective to build an adaptive receiver using artificial neural networks (ANN). The possible ANNs, can be
identification of digital real valued or complex valued networks. The main tasks are to design, manufacture, and test and evaluate an Activity to support ML HW
communications using ANN artificial neural network for adaptive channel equalization system. This can be a part of an adaptive receiver of a applications & processing
D12 communication satellite. N H M 600ARTES modules 2 4 2022 2023
Channel equalization using artificial The objective of the activity is to design, manufacture, test and evaluate an Artificial Neural Network for
neural networks implementing the Viterbi decoder. Activity to support ML HW
The main benefits are increased speed and less susceptibility to different types of noise such as white Gaussian applications & processing
D13 noise, and color noise. N H M 600ARTES modules 2 4 2022 2023

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 37
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Develop Building Blocks to support
AIM D OBCDH module(s) development(s)
Coding, decoding, and error The objective of the activity is to model a Travelling Wave Tube (TWT) using artificial neural network. To
correcting codes using artificial evaluate it by comparison with the classical techniques used and define how to be utilized in the engineering
neural networks workflow. The main tasks are:
1. Design an artificial neural network (ANN) based on the requirements of the model. These requirements
are related with the non-linear complex gain, which are split in two sets. One set is related with the
amplitude nonlinearity (or AM/AM conversion), and the second set is related with phase nonlinearity (or
AM/PM conversion).
2. Acquire and condition the data. Create 3 groups: one for tuning, one for verification and one for the
application. These data are mainly the input/output signals of the TWT.
3. Utilize the collected and processed data with the designed ANN. In other words tune the parameters of
the ANN based on the 1st group of data, then verify that the error is still in acceptable levels using the 2nd
group of data, which are the verification data. Finally, use the last group of data which are the
measurements from the TWT in order to produce the desired output. Note, that this process might be
repeated several times until the specified error levels and accuracy are achieved.
4. Compare the output of the ANN with the data acquired for the TWT.
Finally, it should be noted that this activity is related with the design phase of satellites and consequently Activity to support ML HW
D14 with the system level testing. N H M 600ARTES applications & processing modules 2 4 2022 2023
Evaluation of radiation hardened A new radiation hardened SoC with integrated GPU and ML accelerator is being released on the European
GPU and ML system-on-chip market. The activity aims to evaluate the device for use on ESA missions, including performance
benchmarking and radiation testing, as well as a study of required steps for ECSS qualification of component Activity to support ML HW
D15 and software. N H M 400GSTP applications & processing modules 2 4 2021 2023
Upscreening and qualification of This activity shall aim for the selection, upscreening and ECSS qualification of a COTS parallel processor, such
COTS parallel processor as an GPU or Kalray MPPA (other devices may be considered as well). The goal is to ensure that a highly
performant device for sofware processing can be made available for the use in future ESA missions, e.g. in
the field of Earth Observation or Exploration. The use of software-based processing will increase the Activity to support ML HW
D16 flexibility of the solution comared to currently available ECSS qualified processors. N H M 800GSTP applications & processing modules 5 7 2022 2024
CNN inference engine and This activity aims at developing an inference engine for the HPDP processor, capable of supporting the
framework for HPDP majority of commonly used CNN models. The engine shall include optimized implementation for commonly
used layer types (such as convolutions, ReLU, pooling, softwax/sigmoid, etc.). The tool shall include a
framework that can use a TF2 and/or ONNX model as input, and generate an optimized inference model Activity to support ML HW
D17 that can be executed on the HPDP. N H M 300GSTP applications & processing modules 3 5 2022 2023
Radiation testing and evaluation of In the activity a number of COTS GPU and AI accelerator devices shall be selecetd based on previous
COTS GPUs and AI accelerators performance benchmarks, product lifetime, availability of open source software, use of ECC, etc. for Activity to support ML HW
D18 radiation testing. The radiation testing shall include both TID and SEE, focusing on SEL testing. N M M 300GSTP applications & processing modules 3 5 2023 2025
Evaluation of techniques for in- In-memory-processing offers a potential for a highly power efficient method of data processing. Several
memory-processing companies are offering solutions for memories with integrated processing capabilities, but no evaluation for
the use in space has been done. This activity aims at an early evaluation of the use of in-memory-processing Activity to support ML HW
D19 for space applications. N M M 150TDE applications & processing modules 2 4 2023 2025
Acceleration of RNN for video Several activities have been done on the topic of image processing using CNN, however the real-time
processing analysis of video streams using RNN is still not been fully deveoped for space applications. The activity shall
aim at developing a concept for accelerating RNNs/LSTM in procesors/FPGAs suitable for the use in space.
The targeted applications include object detection, segmentation and classification in video streams with Activity to support ML HW
D20 medium to high frame-rates. N H L 250TDE applications & processing modules 2 4 2022 2024
ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 38
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Develop Building Blocks to support
AIM D OBCDH module(s) development(s)
OBPMark benchmarks for on-board The OBPMark benchmark suite has been developed as an openly available specification and software to
data processing benchmark the computational performance of mulitcore processors, parallel processors (such as GPUs) and
FPGAs for typical on-board image processing, radar processing, compression, encryption, machine learning
and processing building blocks. This activity aims at characterising RHBD processors and FPGAs according to
the OBPMark specification. The activity will include procuring the necessary development boards, and Activity to support ML HW
D21 porting and optimizing the software when necessary. N H M 400GSTP applications & processing modules 3 4 2022 2023
Improvement of Reliability of The goal of the acitivity is to provide guidelines for improving reliability, availability and lifetime of CubeSats.
CubeSat Design (NPI) On top of that component selection and potential reference designs should be discussed. The guidelines
should be based on documentation from heritage satellites/architectures (i.e. SAVOIR requirements for
data-handling) and lessons learned/good practices from previous activities (i.e. choosing right Other ESA NPI
communication busses, defining minimum telemetry for sufficient observability). This activity could be Programme Activity to support Cubesat
D22 carried out with OSIP/NPI framework with a demonstration on TEC-EDD FlatSat. N M M 60s (OEP) modules development
Interoperability of FlatSat with 3rd Considering that a number of developments (i.e. from GSTP activities) is available as deliverables, the goal of
Party Sub-Systems (YGT) activity is to test interoperability of different CubeSat subsystems using current FlatSat as a benchamark.
The test would assess the compatibility of 3rd part subsystem with regard to power/data/software interface Other ESA Internal activity (YGT).
verifying if integration in current Flatsat is feasible. Technical note on outcomes/lessons learned would be Programme Activity to support Cubesat
D23 prorduced. N M M 0s (OEP) modules development
Extension of FlatSat with Payload In current set-up, the FlatSat is missing typical payload (i.e. camera). The goal of this activity is to define Other ESA Internal activity (YGT).
Processing Capability (YGT) architecture of the FlatSat with a payload included, and to demonstrate nominal operation using existing Programme Activity to support Cubesat
D24 hardware (i.e. using Payload OBC for processing data, including S-Band downlink for scientific data) N M M 0s (OEP) modules development
Learned image compression End-to-end learned image compression is currently becoming the state of the art in terms of compression
performances, but it is still several orders of magnitude more complex than traditional onboard
compression approaches.
This study will investigate low complexity learned onboard compression, including learned predictive
compression.
Deep-learning predictors are capable to adjust the best to the real image statistics of each mission, thus
providing increased compression performances. The limited dimensions of the prediction context (few
samples) also allows for small-sized neural networks, which should be compatible with on-board low-
D25 complexity implementations. N H L 200TDE 2 4 2022 2024
Compression of Bayer (or other More and more missions in EO, SCI and EXP are making use of bayer sensors (RGB filter arrays) which are
CFA) filtered images not adapted to current space compression solutions.
Traditional commercial solutions require demosaicing techniques which are computationally expensive and
introduce distortion and therefore not adapted for use in our missions.
This activity will investigate low complexity methods aiming to efficiently compress bayer CFA images with
D26 current or planned space compression solutions (including existing CCSDS standards). N H M 200TDE 2 4 2022 2024
Integration of CCSDS 124.0 (HKTM ESA technology Pocket+ is becoming the CCSDS 124 standard for compression of HK telemetry. To be coordinated with TEC-ED
compression) in ADHA OBC module This activity aims to develop a qualified implementation of this function (HW or SW) for the future ADHA
(as qualified SW or IP Core) OBC modules. OBC Module

D27 N H M 250GSTP 3 5 2022 2023

General purpose video General purpose video compression extend missing functionalities from current TDE (covering HRE needs Follow-on on TDE
D28 compression only) intended for all ESA missions and future CCSDS standardization. N H L 250GSTP To be coordinated with TEC-EDM 3 5 2022 2023

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 39
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Develop Building Blocks to support
AIM D OBCDH module(s) development(s)
Reference onboard image datasets: Machine learning methods are becoming the state of the art for ground applications and a spin in for
Cloud detection onboard processing is a major trend.
However current image datasets are absolutely not representative of the data products available onboard,
and this fact is severely limiting the development of onboard techniques.
Cloud detection is probably the more urgent application to be covered, because besides being greatly useful Other ESA
for data reduction techniques, is also a pre-requisite for many other data analysis tasks such as change Programme
D29 detection. N H H 200s (OEP) GSTP, TDE or other EOP 3 6 2022 2023
Computational imagery: onboard A wide range of techniques emerging from computational imagery can become key enablers to achieve
processing for optical payload increased payload performance in our missions. In particular, multi-frame super resolution and/or co-
performance registered digital TDI is expected to be considered.
The activity will:
- Evaluate the achievable performances of state of the art approaches such as :
Interpolation-based approaches
Inverse problems approaches
AI-based super-resolution
- Evaluate computing requirements and suitability for on-board application.
- Define and implement an optimized algorithm (SW) compatible with state-of-the-art hardware (OPTION:
D30 HW architecture definition and or functional HW simulation/implementation via High Level Synthesis tools). N H M 350TDE 2 4 2022 2024
Real-time HW/SW demonstration The goal is to achieve the optimization and representative real-time implementation in space qualified
of WFE metrology algorithms for hardware (HW, SW, HW/SW) of the algorithms required for wavefront error estimation and correction in
Active optics active optics.
Ultimately, this activity should pave the way for a future development aimed to design and manufacture a
compact and autonomous AO unit (integrating both the WFE sensor and the processing unit) in order to
D31 ease the adoption of the technology. N H L 400GSTP 3 5 2022 2024
AI-based sensorless WFE Recent AI approaches have shown promising results, while also providing interesting advantages in terms of
estimation on payload data. implementation requirements (no WFE sensor, no beam splitter required or other optic elements for phase
Benchmark against traditional diversity, no iterative convergence needed).
approaches PoC - Demonstration of performances compared to traditional solutions in terms of WFE estimation but also
in terms of implementation complexity (optical system and electronics), and deliver simulation or feasibility
D32 analysis on representative hardware. N M L 150TDE 2 3 2023 2024
Analysis Ready Data: Optimized Most onboard data analysis functions require some sort of preprocessing aiming to produce higher level Other ESA
onboard image product generation image products (L1B or even L1C instead of L0), but the processing algorithms used on ground are too Programme
D33 (preprocessing for onboard ML) complex and should be further optimized to be embarked onboard our missions. N H L 200s (OEP) GSTP, TDE or other EOP 3 4 2022 2023
Low latency event detection and Full system demonstration (compatible with ADHA definition) of a low latency event detection application
delivery. Payload processing and (fire, oil spill, change detection) consisting on a data analysis part, alert generation and low latency Other ESA
data handling system transmission to the ground. Programme
D34 demonstration. N H L 250s (OEP) In collaboration with TEC-EDD 2 4 2022 2023
POT spectral preprocessing HW Data dimensionality reduction is a key factor to ease onboard data analysis of multi and hyperspectral data
implementation CCSDS 122.1. in resource constrained HW.
KLT approximation for Luckily the CCSDS 122.1 spectral preprocessing transform offers a good alternative to the KLT in terms of
dimensionality reduction (key for performance/complexity.
D35 ML applications). The goal of this activity is to achieve HW implementation of this spectral transform. N M L 250TDE 3 4 2023 2025

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 40
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Develop Building Blocks to support
AIM D OBCDH module(s) development(s)
Novel payload data compression Many kinds of payload data from our missions is still not covered with current payload data compression
techniques solutions: SAR, altimetry, polarimetric images, Lidar/point-cloud data. Other ESA
This activity will investigate adapted approaches to try to exploit the specific characteristics of those kind of Programme
D36 data. N H M 400s (OEP) GSTP, TDE or directorate programs. 2 3 2022 2024
CCSDS 125.0-B: Future SAR raw Consolidate algorithmic definition for the ESA candidate for this CCSDS standard. Develop prototype Other ESA
data compression Standard including hardware (VHDL) development/simulation and cross-verify for adoption as CCSDS 125.0-B. Programme GSTP, TDE or other EOP
D37 N H H 300s (OEP) In collaboration with TEC-EDM 3 4 2022 2024
Efficient Video Compression for The activity encompasses the following tasks:
space - Consolidate video requirements for ESA Exploration missions,
- Define & develop a HW video compression solution (VHDL IP core) as a standard subset (compliance with
standard decoders for interoperability),
- Breadboard production, verification and validation, T301-
D38 - Integrate in the ESA IP Core Portfolio. F H M 300TDE 2 4 2021 2023701EF
Develop EGSE to support the test
and integration of OBCDH
units/modules and benefit of
AIM E synergies and commonalities
Multi-protocol on-board In the frame of a large endeavour from company iTTi to develop a commercial product addressing the needs
communications network manager of laboratory EGSE capable of supporting a broad range of network protocols, interfaces, and devices (SpW,
SpFi, MIL-STD-1553, CAN, TSN, TTE) called MultiSpaceMan, this activity focusses on the development of a
prototype covering SpaceWire and SpaceFibre. The main functionality of the proposed network manager
includes Discovery of devices present in the network, their configuration, and connection topology,
Configuration of the discovered devices, and Management of different network configurations (storage and GT17-
E01 retrieval, comparison and verification). R 220GSTP FI ITTI (FI) 2020 2022200ED
ECSS-E-ST-50-15C CAN Development of a CAN bus unit tester. The tool shall cover the CAN bus timing configuration and the
E02 conformance tester CANopen functionality covered by the ECSS-E-ST-50-15C. N M H 300GSTP
EGSE to test ADHA Modules when The objective of this activity is to develop a "break-out box" to be integrated between an ADHA module and
E03 integrated in a ADHA rack the ADHA backplane to observe the signals of the ADHA module under integration and test. N H H 300GSTP 2 6 2021 2022
EGSE to test an ADHA unit The objective of this activity is to develop an EGSE to test and ADHA unit, including the necessary equipment
E04 to interface with the ADHA unit and to observe the backplane electrical signals. N H H 1000GSTP 2 6 2021 2022
Enhance characteristics/functions
of current ASIC Platforms and
AIM F develop USDM ASIC Platforms
Definition of Radiation Effects assessment of 16nm FinFETs technology for space applications, via TCAD simulations and test chip
Mitigation Techniques for Ultra- characterization under radiation. Radiation hardening techniques will be identified and design guidelines IROC(F) T523-
F01 Deep Submicron Technologies established R 500TDE FR CTB (SI008) 2 3 2019 2022601ED
High Speed and Low Power Die-to- up to 500Gbps die to die interface GlassWing IP and Test Vehicles in 16 nm and 12 nm for high-performance
Die Interconnects in a Package - processing for computing and processing modules G627-
F02 CCN1 R 720GSTP CH Kandou (CH) 3 5 2020 2022060ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 41
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Enhance characteristics/functions
of current ASIC Platforms and
AIM F develop USDM ASIC Platforms
DARE 65 - Implementation, new generic technology platform for the development of Analog, mixed, and digital ICs (including ASIC).
Evaluation, and Release of a
Radiation Hardened Mixed-Signal
Cell Library in a 65 nm CMOS G617-
F03 technology R 3300GSTP BE IMEC (BE) 3 6 2016 2022173ED
​Ultra deep submicron assessment assess 7 nm FinFET technology (or smaller due to foundry process optimisations) for its use in
F04 for on-board digital processors telecommunication digital signal processors in the space environment N 2000ARTES ARTES AT 2 4 2021 20225C.443
DARE65 analog/mixed-signal IP Development of the mixed-signal blocks for a) control, b) high-speed communication interfaces c) analogue
development for instrumentation, signal processing, d) high-speed image detector front-ends and digital processing back-ends for science,
control and interfacing applications earth-observation and avionics, e) multi-channel radiation detectors. With reference to the succesful
components developed on the 180nm CMOS node these building blocks would include (i) high-resolution
ADC and DACs, (ii) high-speed and low power ADC and DACs, (iii) low jitter and high-frequency PLLs, (iv) DDR,
(v) high-speed serial links, (vi) high-density memories, (vii) DLL, (viii) on-chip power conversion and
F05 management functions N H M 3000GSTP as a frame contract 3 5 2021 2023
analog/mixed-signal IP Development of the mixed-signal blocks for power conversion, distribution,monitoring and control
development for power conversion applications. With reference to the succesful components developed on the 350nm/180nm high-voltage
and control applications processes these building blocks would include (i) high-voltage switches, (ii) power-switches, (iii) high-voltage
drivers, (iv) high speed drivers (v) high-voltage and common-mode signal analog to digital converters (vi) as a frame contract, relevant for
F06 on-chip power conversion and management functions N H H 1000GSTP CD4 too 2 5 2022 2024
Radiation hardening of High-Speed The aim is to radiation harden current low-power high-speed die to die interfaces. The high power
Die-to-Die Interface consumption of data communication on the PCB requires the different ASIC dies to interconnect in the
package. This interface allows a) reduce power consumption, b) increase bandwidth in excess of 500Gbps, c)
glue ASIC die of different processes together inside one package, d) increase space ASIC system yield, e)
allow heritage mixed-signal designs to be reused with more advanced digital ASICs, f) combine the best of
each foundry process (high-voltage, high-speed, advanced digital) to be connected within one package at
F07 minimum power consumption. N H M 1000GSTP 3 5 2021 2023 F02
UDSM ASIC Platforms development based on the results of ongoing UDSM ASIC developments and respective rad hard ASIC libraries, design kits Other
and consolidation and their supply chain ecosystems (including the assembly, package and test technology), the goal is to European Follow-on of/ related to T523-
consolidate (further develop, test and maintain) any of the technology elements of the emerging new space Institution 601ED, G627-060ED, 5C.443,
ASIC platforms on of 28 nm or smaller nodes Programme ,EFESOS, DUROC, ARTES ASICs
F08 N H H 5000s (OEIP) activities 3 5 2022 2025 F02
EFESOS: Evaluation of a 22nm or Provide design platform for radhard ASICs and standard products
beyond ASIC process and flow The design platform will consist of Analog Design Kit ADK, CORE library, IO cell library, ADC IP, DAC IP, HSSL
IP and PLL IP, user guidelines and datasheets. Other
European space ASICs on 22nm process node (GLOBALFOUNDRY) European H2020
Space Evaluation on the basis of the ESCC test flow. Assessing the robustness of the libraries, mainly in Institution IMEC (B), ARQUIMEA (ES), RUAG
terms of radiation aspects. Programme (AT), Microtest (I)
F09 The prototype will not be a final product but a vehicle for validating the space compatibility and robustness. R 3385s (OEIP) CTB (SI009) 2 4 2020 2023EFESOS
Evaluation and Characterization of Evaluate and characterize a common harmonized flow for the design, evaluation and qualification of mixed ISD (GR), Microchip (FR), VTT (FI),
a Harmonized Mixed-Signal ASIC signal ASICs: Build an IP product portfolio for the selected technology ATMX150RHA GR, FR, Airbus, CSL T723-
F10 Flow R 590TDE FI CTB (SI023) 1 4 2015 2021305QT

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 42
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Enhance characteristics/functions
of current ASIC Platforms and
AIM F develop USDM ASIC Platforms
Development of a Deep Trench The objective is to expand the current mixed signal capability of ATMX150RHA by developing a new high
Capacitor for embedded DC-DC and density integrated capacitor, based on deep trench process option already available in 77K technology Other ESA GSTP, TDE
Power Management in a mixed which will open up to integrate power management application on chip and enabling a future disruptive Programme Microchip
F11 signal ASIC process. miniaturization of platform boards, reduction of components, and boost in power efficiency. N H M 450s (OEP) FR CTB (SI025) 2 4 2022 2024
Evaluation of LFoundry mixed- The objective is to technically evaluate and assess the basis of a potential mixed-signal ASIC technology for
signal 150nm CMOS process space based on LFoundry’s150 nm mixed-signal process. Therefore, test chip designs from Sitael (test
(LF15A) for Space Applications structures for rad-hard design) and Redcat (memory IP) are developed and used. Thales Alenia Space Italy Sitael, Lfoundry, Redcat, TAS-I, U of
will support the overall activity contributing its requirements and expertise as an experienced ASIC process Padova, IMT (IT) G617-
F12 user for space applications R 650GSTP IT CTB (SI026) 2 4 2016 2022202QT
PROMISE: Programmable Mixed Radiation hard Mixed - Signal ASIC architecture based on reconfigurable eFPGA IP and the DARE180X/XFAB Other
Signal Electronics XH018 technology European H2020
Design, manufacturing and industrialization of a Pilot Circuit. Institution TAS-E, TAS-F, MENTA (F), ISD (GR),
Space evaluation following ESCC9000 like, the emphasis is on radiation aspects. No formal Programme Inst. Tel (P), VTT (FI), IMEC (B)
F13 evaluation/qualification is expected within the frame of the project R 2875s (OEIP) CTB (SI069) 3 5 2020 2023PROMISE
Improve and expand the European
AIM G rad-hard FPGA family
Strategies for reliable on-board strategy that enables safe FPGA reconfiguration, for relevant targets KU60, RTG4, BRAVE family, reference
reconfiguration of FPGAs design, radiation test results, strategies for fault mitigation and isolation. Relevant for missions wanting to GT17-
G01 re-configure during flight - including COTs. F 750GSTP 2 4 2021 2023327ED
European FPGA with integrated Definition, design, verification, manufacturing, packaging, validation and characterization of the NG- T723-
G02 ADC and DAC ULTRA300 (28nm FD-SOI) (which has integrated ADS and DACs) and Dev Kit. R 500TDE FR NANOXPLORE (FR) 2 4 2020 2022611ED
SPRINT 2 - NG-Ultra prototypes NanoXplore BRAVE NG-Ultra FPGA manufacturing of first prototypes and bring-up tests NANOXPLORE (FR)
production & bring up GT17-
G04 R 2158GSTP FR CTB (SI087) 3 4 2020 2021405ED
Evaluation of embedded FPGA Besides classical (SoC) FPGA dominated by FPGA fabrics, eFPGA can be added to hard-wired ASICs, hence Other ESA
(eFPGA) IPs and Tools providing flexibility of reconfiguration (per project or in flight) while keeping the good performance / power Programme
G05 ratio of an ASIC. Evaluate available eFPGA technology and related design tools. N H M 100s (OEP) TDE, OSIP 1 2 2021 2024
Demonstration of embedded FPGA Implement a space use-case using eFPGA. Demonstrate on MPW. Leverage into a space ASIC platform such
G06 (eFPGA) IPs and Tools as DARE65 or DARE22. N M M 400TDE 2 5 2023 2025 G05
Evaluation of PolarFire FPGA with To evaluate suitability of the device for different space missions, propose and evaluate the need for
embeded RISC-V for space mitigation techniques, availability of software to introduce mitigation and analysis of error rates, and could be less budget if consortium
G07 applications demonstrate that mitigation works on real applications while irradiated. N H H 500TDE is small 2 5 2022 2024
Evaluation of the design mitigation Consolidation on the design mitigation techniques required for the KU060 FPGA after an exhaustive
techniques of KU060 FPGA to research of the current state of radiation results and design mitigation techniques; the goal is to define and
define a flow for ESA missions implement known techniques using commercial tools fro which we do not have yet results when applied to
KU060 . In parallel it will define and develop or update innovative R&D strategies and tools to extend the
mitigation techniques and flows. The results will be validated by radiation testing and complemented when
possible with other (e.g. fault Injection). Based on the results, the activity will provide guidelines for ESA could be less budget if consortium
G08 missions of different types. N H H 500TDE is small 2 5 2022 2024

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 43
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM G rad-hard FPGA family
Reliability Evaluation of COTS PLATiNO progam includes several complex COTS devices. Starting from the coming experience gained in that Institutional
complex IC (FGPA, u-controller, project an extended activity is proposed to reach a full evaluation of available technologies in view of future National ASI Programme
etc.) application in satellites constellations Programme PLATiNO
G09 R 500s (INP) IT CTB (SI068) 2 6 2020 2022PLATiNO
OPERA: BRAVE NG-LARGE. BRAVE FPGA NG-LARGE. Package is flip chip CCGA 1752. 1.9 M Gates Other
CCGA1752 Qualification and European H2020
validation. SW design and Institution NanoXplore (F), TAS-I, TAS-F, P di
optimization Programme Torino, ADS, ST (F)
G10 R 3000s (OEIP) CTB (SI012) 5 7 2019 2021OPERA
MARS: BRAVE NG-ULTRA, TV Produce NG-ULTRA, including the mask costs, wafer production and packaging. Institutional
Derisking, Development, Organic National CNES, DGA, Fr Gv
packaging Programme NanoXplore, …
G11 R 21600s (INP) FR CTB (SI017) 4 5 2017 2021MARS
BRAVE, NG-ULTRA family Space Space evaluation and qualification of NG-ULTRA 28 nm Family (Organic packaging)
Qualification -> Organic Package STM / Nanoxplore
G12 Qualification R 3000ARTES FR CTB (SI018) 5 7 2021 20235C.448
DAHLIA: SoC based on FDSOI28nm • To define a SoC (System on Chip) platform offering breakthrough performance to serve the largest scope
with multicore Cortex-R52 ARM of applications to future Space and Avionic equipment Other
processor • To develop a very high performance SoC based on European 28 nm FDSOI with multicore Cortex -R52 ARM European H2020
processor for real time applications and a very large eFPGA for flexibility Institution DAHLIA - ST (F), ADS (F,D), TAS (F,I),
• The DAHLIA architecture will be designed to meet the requirements of the Space applications (platform & Programme ISD (GR), NanoXplore
G13 payload) in term of computing as well as real - time performance, power and area R 4000s (OEIP) CTB (SI065) 2 4 2017 2021DAHLIA
Quality Assessment of the new Define methodology to provide quality assessment of the BRAVE Ultra Software tools, apply methodology
European Ultra BRAVE FPGA for specific use cases, report findings and upgrade tools accordingly
Software Tools GMV (ES) Technology Push. NG-ULTRA FPGA T725-
G14 (Queens3) R 400TDE ES CTB (SI067) available by Q42021. 2 4 2021 2022705QQ
European FPGA with integrated Intermediate capacity BRAVE FPGA NG-Ultra 300 development (300 kLUT’s + Low Speed DAC and ADC) Institutional
ADC and DAC (BRAVE NG ULTRA- National Joint effort of CNES and ESA
300) Programme NanoXplore (F) 500K€ is ESA TDE, 1600K€ are CNES T723-
G15 R 2100s (INP) FR CTB (SI072) and FR national funds 2 5 2016 2021611ED
Derisking Non Hermetic Flip-Chip Derisking Non Hermetic Flip-Chip for BRAVE FPGA Institutional
for BRAVE FPGA National
Programme ST, NanoXplore (F)
G16 R 650s (INP) FR CTB (SI075) CNES programme 2 4 2020 2021CNES
HERMES: Qualification of High Development and testing of ceramic hermetic package CGA 1752 Other
pErformance pRogrammable Space ESCC evaluation of the rad-hard FPGA (NG-ULTRA) European HERMES - NANOXPLORE (F), POLIT.
Microprocessor and dEvelopment Development and validation by end-users of software tools including BAMBU HLS, Xtratum hypervisor and Institution Milano (I), FENT INNOV SW (SP),
of Software ecosystem BL1 Programme TAS-F (F), STM (F), AIRBUS (F)
G17 R 3000s (OEIP) CTB (SI081) 3 5 2021 2024HERMES

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 44
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM G rad-hard FPGA family
DUROC: Design and validation of DUROC will be the first building block to develop the next generation of ultra-reprogrammable SoC, Other
Ultra-Reprogrammable SoCs following NG-ULTRA. The ULTRA 7 based on 7nm FinFET technology (TSMC) European DUROC - NANOXPLORE (F), ISD
Institution (GR), IROC (F), TAS-F (F), AIRBUS
Programme (D), AIRBUS (F)
G18 R 3000s (OEIP) CTB (SI082) 2 4 2021 2023DUROC
Hardening Techniques for COTS to develop, implement and test rad hardening tech to mitigate for enabling use of COTS FPGAs in GEO
G19 FPGA for Digital TL Payloads telecom sats F 800ARTES CTB (SI086) 2 5 2021 20235C.416
FPGA Programming Tools Improvements of NX FPGA Programming tools (BRAVE family) Institutional
National
Programme NX, funded by French Gov
G20 R 5000s (INP) FR CTB (SI115) 5 7 2021 2022SI115
Improve and expand the European
rad-hard Microprocessors,
AIM H Microcontrollers and DSPs
GR740 Next Generation Manufacturing of flight silicon, packaging and FM qualification of the GR740 quad-core LEON4-FT
Microprocessor Flight Models microprocessor. qualification MIL-QML-V and ESCC-9000 certification. G617-
H01 (NGMP Phase 3) R 950GSTP SE COBHAM GAISLER (SE) 4 7 2018 2021273ED
Digital Controller for Power The Digital Programmable Controller (DPC) embeds 4xCPU 16b OpenMSP430, 13b ADC, 12b DAC using
Management DARE180. DPC rev F aims to (i) improve the proton robustness with the replacement of the HIT with DICE
flip-flops, (ii) introduces cold-sparing for its IOs and (iii) implements DSP accelerators to increase the
H02 bandwidth for digital control applications R 5741ARTES ARTES AT. TAS (BE) 4 7 2017 20224F.065
SMT verification of the COBHAM validate solderability of the GR740 using different types of solder columns (HCM, Micross).
GR 740 device with Micross/HCM TDE Small Studies. 4000117
H03 columns R 75TDE IT TAS (IT) 3 5 2018 2021598
Development of a multi core Engineering samples of 8xLEON5, several interface improvements compared to GR740 and acceleration
LEON5FT Space grade blocks. GT27-
H04 Microprocessor GR765 F 1000GSTP SE COBHAM GAISLER (SE) 3 5 2021 2023088ED
RISC-V Microprocessor Prototype Definition, design and prototyping of a high performance European 5th Generation Space Microprocessor T701-
H05 (VGSM) based on the RISC-V open Instruction Set Architecture on UDSM ASIC technology F 450TDE 2 4 2022 2024702ED
RISC-V for space SW tool Development / porting / qualification of the SW ecosystem for RISC-V in space, covering Operating Systems
ecosystem (e.g. RTEMS, OCEOS, LeanOS), Compiler (e.g. for instruction extensions), Hypervisor (e.g. XTratum), Timing Other ESA Aim to be refined and broken down
Analysis (e.g. Rapita), Parallelization tools (e.g. OpenMP, Extrae), Libraries (Math, DSP), Simulators, Programme into manageable activities by /
H06 Debuggers N H H 600s (OEP) together with TEC-SW - TDE, GSTP 3 5 2022 2025 H05
RISC-V instruction extensions As a follow-up to GSTP G617-225ED and complement to TDE T701-702ED, tightly coupled RISC-V instruction
set extensions shall be developed, such as SIMD / Vector and bit manipulation extensions. To ensure Other ESA
compatibility with the RISC-V SW ecosystem, preferred extensions are those which are or will likely be Programme TDE, GSTP, EOP, NAVISP, can have a
H07 ratified by riscv.org. Development of SW drivers / examples and demonstration on COTS FPGA. N H M 500s (OEP) link to eFPGA activities 2 4 2022 2023 H05
RISC-V instruction set extensions this study shall evaluate the addition of embedded FPGA (eFPGA) to the RISC-V pipeline, such that a
through embeded FPGA standard RISC-V microprocessor, hard-coded in an ASIC, can be extended with new instructions, after As a follow-up to the GSTP activity
manufacturing, or even in flight. Such instructions can help various types of applications, such as SDR, GNSS, "ESA IP Core Extensions" (G617- TSS21-
H08 Crypto, IA. F 23TDE CZ 225ED), 1 3 2021 202204ED H05

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 45
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
rad-hard Microprocessors,
AIM H Microcontrollers and DSPs
VGSM (5th Generation Space After the reduced scale VGSM prototype of RISC-V in Ultra-Deep Sub-Micron (UDSM) technology
Microprocessor) RISC-V Engineering undertaken in TDE T701-702ED, this activity shall implement Engineering Models at full scale, i.e. with full
H09 Models number of CPU cores, instruction extension and full amount of on-chip memory. N M M 2000GSTP follow up of TDE T701-702ED (H05) 3 5 2023 2024 H05
VGSM (5th Generation Space Space qualification of VGSM according to ESCC/MIL-QML standards.
Microprocessor) RISC-V Flight
H10 Models N M H 1000GSTP 5 7 2024 2025 H09
GR712RC transfer of screening and GR712RC is a dual core LEON3 processor that has been commercially available to the space market since
electrical test 2013 with flight heritage, developed under own funding by Cobham Gaisler (Sweden). Manufacturing and Cobham Gaisler(SWE)
testing of the GR712RC product is spread on multiple facilities and companies. With this proposed activity, Micross (UK) or Serma/HCM(FR),
all processing after wafer manufacturing will be transferred to a single company in Europe. With the new Aeroflex RAD Europe (UK)
H12 process flow, evaluation testing and qualification test will be performed supporting its EPPL listing. N H L 300GSTP CTB (SI046) 4 9 2022 2023
MORAL: Export Free Rad-Hard 32 - bit microcontroller based on a Peaktop architecture for space applications, focused on small satellites,
Microcontroller for space flight control and payload computers
applications Integration of: rad-hard 12bit, 8-channel ADC and DAC converter, 512KB rad-hard, on-chip memory, Other
SpaceWire, European
PWM, Floating - Point Unit (FPU) and a Digital Signal Processing (DSP) unit. Institution IHP (D), REDCAT (I), SYSGO (D), TAS-
Space Evaluation with focus on radiation aspects. Programme E, ABSINT (D)
H13 Establish a new European company which will commercialize the product. R 3000s (OEIP) CTB (SI071) 2 5 2020 2023MORAL
Rad-hard ARM µP SAMRH71 Development, Evaluation and Qualification of rad-hard SAMRH71 ARM µP + Plastic package introduction Institutional
National
Programme MCHP
H14 R 1000s (INP) FR CTB (SIX07) 3 7 2018 2021
Rad-hard ARM µP SAMRH71 Reduction of the number of peripheral components on SAMRH71 PCB: Institutional
System Solution clock management circuit development and PMIC7400 power management circuit radiation assessment National
Programme MCHP
H15 R 410s (INP) FR CTB (SIX08) 3 6 2020 2021
Rad-hard Multi-core ARM µP Developement of next Rad-Hard Multi-Core A7 microprocessor - Phase 1 : Radiation assesment of Institutional
commercial ARM A7 part and Architecure definition. National
Programme MCHP
H16 R 200s (INP) FR CTB (SIX09) 4 6 2020 2021
Rad-Tol ARM µP SAM3X8E Development and space evaluation of rad-tol µP for New space market. SAM3X8E is based on ARM Cortex Institutional
M3: QualPack available since March 2020, proton test session still to be done @TRIUMF (delay due to Covid- National
19) Programme MCHP
H17 R 250s (INP) FR CTB (SIX10) 4 6 2018 2021
Rad-Tol ARM µC SAME54 Radiation assessment of SAME54 ARM Cortex M4 microcontroller Institutional
National
Programme MCHP
H18 R 125s (INP) FR CTB (SIX11) 4 6 2020 2021

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 46
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
rad-hard Microprocessors,
AIM H Microcontrollers and DSPs
Rad-Tol Quad ARM µP QLS1046- Development and space evaluation of rad-tol µP for New space market. QLS1046-4GB-Space is based on Institutional
4GB-Space Quad ARM Cortex A72 and 4GB DDR4 memory. National
Programme T-E2V
H19 R 150s (INP) FR CTB (SIX12) 3 5 2019 2022
ARM based MCU ("JAGUAR") development of a rad-hard, space grade, mixed signal microcontroller, based on the ARM Cortex-M7
architecture, and integrating Flash memory, various communication interfaces and analog functions on-chip,
such as ADC/DAC and PWM. The chip will be released in a CQFP-164 package, with plans being discussed for
a CGA/BGA-484 package as well (plastic version may follow later on). The chip will be radiation tested, and MICROCHIP TECHNOLOGY NANTES T701-
H20 validated on a hardware development board R 900TDE FR (FR) 2 4 2019 2021505ED
next Gen ARM MCU (GF 55nm) MCHP is proposing, not yet discussed at CTB/Si WG Institutional
National proposed by MCHP, introduced
Programme provisionally by ESA, not yet
H21 N H M 500s (INP) FR harmonised 2 5 2022 2024
next Gen ARM MPU (28nm) MCHP is proposing, not yet discussed at CTB/Si WG Institutional
National proposed by MCHP, introduced
Programme provisionally by ESA, not yet
H22 N H M 500s (INP) FR harmonised 2 5 2022 2024
Space mixed-signal Microcontroller Mixed-signal microcontrollers using 180nm CMOS technology (e.g. DPC, GR716 or SAMRH71), despite the
with open Instruction Set limited memory, processing power and mixed-signal signal bandwidth have demonstrated their value for
Architecture on 65 nm or below space. More advanced process nodes at 65nm and beyond allow to increase the bandwidth, speed, on-chip
memory, reduce power consumption, embedded Non-Volatile-Memory/eFlash, autonomous functions,
advanced time scheduling with zero jitter to enable predictable signal processing and control operation .
This activity aims at defining , designing and prototyping a new European microcontroler based on 65nm or
H23 smaller node including the mentioned new features and using an open ISA core (e.g. RISC-V, open SPARC) N H M 1500TDE 3 5 2022 2024 F03
Improve and expand the European
AIM I rad-hard ASSP family
Dynamic Latch-Up / latching LatchUp Protection Component, Support to COTS based high performance components T701-
I01 Current protection ASIC (LUCA) R 720TDE BE NSILITION (BE) 2 4 2016 2021316ED
Qualification of Latch-Up/latching Space qualification of the different versions of the latch-up/latching current protection ASIC for the different
I02 Current protection ASIC space markets N H H 750GSTP BE 4 9 2022 2023 I01
Development of a GNSS ADC ASIC GNSS ADC component for single board GNSS RX Saphyrion (CH) G611-
I03 R 589GSTP CH CTB (SI09) 3 6 2017 2022048EO
Development of a wideband GNSS Optimum GNSS performance is obtained with the coherent sampling of the whole GNSS bandwidth. This Other ESA
ADC ASIC development proposes to increase the bandwidth of the current low-power GNSS ADC ASIC to encompass Programme GSTP or EOEP or NAVISP
I04 efficiently the whole of the GNSS bandwidth to allow optimal digital GNSS signal processing N H M 750s (OEP) CH Saphyrion (CH) 2 4 2022 2024 I03
6 Gigabits European Space Development of a Serial-Deserialization modular IP (SERDES) with capabilities at up to 6.25 Gbps under
Serializer-Deserializer (SERDES) TSMC65 technology with DARE65 Library Arquimea GT27-
I05 under TSMC65 technology R 617GSTP ES CTB (SI091) 3 5 2021 2023086ED
High-Speed High Resolution Quad- Design, manufacture, validation, irradiation, and characterization of an integrated circuit to implement a 4- T201-
I06 ADC for Science Instruments channel 12bit analogue-to-digital converter component F 500TDE CTB (SI089) Science (LISA) 3 4 2021 2023052ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 47
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM I rad-hard ASSP family
28 Gbps optical transceivers for 28 optical transceivers for space using NRZ direct current modulation, and vertical-cavity surface-emitting 5f.011
I07 space laser (VCSEL) R 535ARTES CA Reflex Photonics 6 8 2020 2021SL9010
56 Gbps PAM4 VCSEL optical 56 Gbps optical transceivers for space using 4-level pulse amplitude modulation ( PAM4 ) vertical-cavity
I08 transceivers for space surface-emitting laser (VCSEL) F 500ARTES UK ALTER 2 4 2021 2024
53 Gbit/s/ch Chipsets for VCSEL-
based Interconnects in Space
I09 Application F 1575ARTES CH Tetra Semiconductors Ltd. 2 4 2021 2023
56 Gbps silicon photonics optical 56 Gbps optical transceivers for space using NRZ extrernal modulation and silicon photonics as laser source 5f.011
I10 transceiver for space R 1000TDE IE mBryonics 2 3 2021 2023SL9010
Space qualification of Space qualification of a 56Gbps VCSEL (vertical-cavity surface-emitting laser) based electro-optical
I11 56Gbps VCSEL based transceiver transceiver N M M 500ARTES CH 5 9 2023 2025 I09
112Gbps optical transceiver for Develop a prototype 112 Gbps electro-optical transceiver based on either 1) 4-level pulse amplitude
space modulation ( PAM4 ) vertical-cavity surface-emitting laser (VCSEL) or 2) NRZ extrernal modulation and
I12 silicon photonics as laser source N M H 1000ARTES CH or IE 2 4 2023 2025 I10
Preparation of enabling space This activity targets the development of a die consisting in a Point of Load DC/DC converter (40 V inout
technologies and building blocks: voltage, 8 A output current) to be used to provide power to low voltage/high current digital circuits. The
Prototyping and initial evaluation ofdevelopment has been brought to PDR level in a previous Contract and is to be continued with elaboration
a monolithic, rad-hard, high-power of the layout, processing through wafer run and testing of the designed die. GT17-
I13 POL converter R 450GSTP DE SpaceIC (DE), MCHP ATMX150RHA 3 5 2020 2022137TIal
Mixed Signal ASIC Controller for Development of a prototype space PWM power converter ASIC (called "MISAC") using ATMX150RHA NMP15-
DC-DC Power Converters (MISAC) - technology Other ESA Polish Incentive Scheme. 04 /
Phase B Programme AstriPolska (PL) /ISD (GR), MCHP PL_AD00
I14 R 894s (OEP) PL ATMX150RHA 3 5 2016 20224
I15 Space qualificaton of MISAC Space qualification of MISAC ASIC N H M 500GSTP 5 7 2021 2022 I14
Integrated Power Switch ASIC for GT17-
small DC/DC converters 032EP /
4000126
I16a R 600GSTP DE SpaceIC (DE), MCHP ATMX150RHA 3 5 2019 2022082
Integrated Power Switch ASIC for GT17-
small DC/DC converters - parallel 032EP /
contract 4000126
I16b R 600GSTP BE TAS (BE) 3 5 2019 2021321
​On chip integrated power design,manufacture and test an on-chip integrated power converter for high performance Field
converter for advanced field Programmable Gate Array applications to reduce size and footprint
I17 programmable gate arrays ​ F 1000ARTES 3 4 2021 20235C.440
System Basis Chip for space Micro-controllers require a data, control and monitoring, supply interface for inter and intra-connection and
supervisor. These interfaces demand high-voltage, ESD and EMC tolerance which is not compatible to the
processes usually employed to manufacture microncotrollers. In the automotive industry this functionality if
covered by the "system basis chip" (SBS). Comparible interfaces currently are realised with discrete
components design that are prone to failure and are power and area demanding. This activity proposes the
development of a prototype system basis chip for space in a high voltage process, including serial interfacing Other ESA
(CAN, SPI, SpW, ..), supply distribution and control and superviror for microcontroller and FPGA based Programme
I18 modules and equipment N H M 1000s (OEP) TDE, GSTP, CD4 interested too 2 5 2022 2024
ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 48
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM I rad-hard ASSP family
Multi Channel PWM controller This activity aims to develop a prototype multichannel buck converter for space equipment power supply Other ESA
rails with integrated power managment function Programme
I19 N H M 750s (OEP) TDE, GSTP, CD4 interested too 2 5 2022 2024
High speed and resolution image This activity aims to realise a high-speed (20MSps) and resolution (ENOB>14bit) front-end demonstrator for
detector front-end image detectors. Recent advances have made high-resolution (16bit ENOB @200ksps) and high-speed (14bit
ENOB @ 10MSps) possible. Lower feature nodes at 65nm (Bi)CMOS should enable both high-resolution and Other ESA
high-speed image detector front-ends. This activity aims to demonstrate this technology for image fronte- Programme
I20 ends for science and earth observation N H M 1000s (OEP) GSTP, CTP-SCI and EOP 2 4 2022 2024
Development and Comercialization Data converters define the performance of the interface between the digital domain and the real world. Other ESA
of state-of-the-art data converters New ADC and DAC products are required to exploit recent microelectronic technlogies and maintain Programme
I21 (ADC/DAC) competitiveness. N H M 1500s (OEP) GSTP 3 5 2022 2024
Multi Channel over-voltage and This activity aism to develop a multichannel over-voltage and over-current supply rail protection ASIC. It Other ESA
over-current protection ASIC integrates the function found common in most space equipment for the prevention of over voltage/current Programme
I22 situation that could lead to equipoment damage and failure propagation N H M 900s (OEP) GSTP, CD4 interested too 2 4 2022 2024
INTERSTELLAR: High speed Dual Develop a new generation of European component with breakthrough innovations. Performance and Other
channel DAC 12 bit, 12 GSps bandwidth beyon state-of-the-art for Space application European
Institution H2020
Programme Teledyne-e2V Next generation DAC for high data INTERSTE
I23 R 4000s (OEIP) FR CTB (SI001) rate Space telecommunication 2 6 2016 2021LLAR
Design / Development and CMOS scaling has enabled usage of DSM based technologies for RF applications. State-of the art currently Institutional
qualification of a cutting edge ADC reports achievement of 70 GHz perfromance for cutting edge ADCs and DACs. This activity would targed to National Te2V (F), post-Interstellar H2020,
(from Ka-Band), in Ultra DSM develop and qqualify a cutting edge rad hard ADC for space based on 28nm SOI CMOS. Programme CNES (500), +internal (total 10000)
I24 R 500s (INP) FR CTB (SI006) 2 7 2020 2021
Characterization eV12AS940 Institutional
National
Programme Te2V (F)
I25 F 0s (INP) FR CTB (SI083) 2021 2022
Reliability Evaluation of COTS ADC, PLATiNO program includes several complex COTS devices. Starting from the coming experience gained in Institutional
DAC that project an extended activity is proposed to reach a full evaluation of available technologies in view of National
future application in satellites constellations Programme
I26 N 500s (INP) IT CTB (SI059) New Space 2021 2023
Developement and Qualification of Development and Evaluation of rad-hard DAC. RHFDAC121 is pin to pin compatible with US one Institutional
12bit DAC (DAC121S101QML-SP) National
Programme ST
I27 R 503s (INP) FR CTB (SI106) 2018 2021
European microwave capable Development of microwave capable ADC/DAC with XSR (eXtra Short Reach) die-to-die interfaces in order to
ADC/DAC with high-speed low- enable efficient integration of ADC/DAC with European FPGAs or digital ASICs into modular and power Co-funded by CNES
power interfaces (XSR) for efficient efficient SiP (System-in-package) Te2V (F) Generic for Future Generation of
I28 SiP integration N 10000ARTES FR CTB (SIX16) Space applications 2 7 2023 2025SIX16

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 49
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM I rad-hard ASSP family
Development of a 2.5GHz, LVDS- Development of a 2.5GHz, LVDS-based serializer (European TLK2711) Entry raised by ST as a question if
based serializer (European there would be interest in such a
TLK2711) component. Microchip found it
'currently not urgent', ISD thought
that users would be there if we had
a component. We agreed to get
feedback from NanoXplore to see if
we could get s.th from their
serializer. NX plans to
commercialize their IP through a
3rd party; therefore this did not
Other ESA manifest into anything concrete so
Programme far...
I29 N 400s (OEP) CTB (SI019) 2022 2024SI019
Radiation hard VCSEL (Vertical- To develop and validate an engineering model of a VCSEL (Vertical-Cavity Surface-Emitting Laser) laser superseded by 53 Gbit/s/ch
Cavity Surface-Emitting Laser) driver and receiver chipset operating at 28Gbps Chipsets for VCSEL-based
driver and receiver chain for high Interconnects in Space Application,
speed digital optical transceivers ARTES, with Tetra Semiconductors
CH
I30 N H M 600TDE CTB (SI020) 3 5 2022 2024SI020
Evaluation and qualification of a Scope, objective and target to be provided by DLR. Would this be supported by DLR for a GSTP?
I31 GMR sensor N H M 200TDE open CTB (SI21) 3 5 2022 2024SI021
Rad-hard LVDS Driver/Receiver Low Development and Evaluation of Low voltage LVDS Driver/Receiver RHFLVDS33/24 Institutional
voltage National
Programme
I32 F 400s (INP) ST, CTB (SI113) 2020 2022SI113
Development of a next-generation Design, Manufacturing and Radiation Testing of a state of the art European ultra low
rad-hard, ultra low drop voltage Voltage drop Regulator
regulator Description: In secondary power conversion and distribution Low drop-out (LDO) voltage regulators
are widely used. They are the fundamental building blocks that can satisfy the stringent
requirements of supply voltage tolerance of digital loads. With an increasing loads power
demand and the need for more and more compact units, the efficiency of the power
distribution has become a key aspect. Reducing the voltage drop (Vdrop) of LDO from
0.4V to 0.1V would reduce by the same factor the power losses in the distribution.
Today the best European LDOs still show a Vdrop around 0.4 V, while in the US new
products present a Vdrop in the range of 0.1 to 0.2V. A state of the art, competitive
European solution is needed to meet European space system demands for current and Generic. Rad-hard low drop voltage T723-
I33 future generations. F 500TDE open, CTB (SI048) regulators are used all ESA missions 3 4 2022 2024704ED
Prototyping and characterisation of Aims at developing a radiation-hard voltage clamp integrated circuit for space applications, to be used in
a monolithic, rad-hard, Voltage next generation power conversion and distribution architectures based on Point of Load (or linear)
Clamp Integrated Circuit regulators, which require very low supply voltages of 5.6V and below. Following design, wafer
manufacturing and prototype assembly in hermetic packages, the functionality and especially T723-
I34 radiationhardness of the component shall be verified by testing. R 270TDE DE SpaceIC , CTB (SI049) 2 4 2019 2022506QT
ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 50
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM I rad-hard ASSP family
Evaluation of on chip power Concepts for integrating on chip a local DC-DC conversion would be studied. Potential solution migh involve
conversion concepts for space ASIC usage of deep-trench capacitors or MIM capacitors. Concepts shall be translating into evaluation test chips.
technologies The test chips shall be characterised for reliability an radiation. The main challenge will constitute in
I35 hardening of high voltage and Power MOSFET devices. N H L 1200TDE Open, CTB (SI050) 2 4 2022 2024SI050
Development of a monolithic, rad- ISL705 reset supervisor is currently commonly used in Europe. This development activity would consist in
hard Power Sequencing Device. demonstrating capability of a pin to pin replaceable product of the latter, and ideally with demonstration of
outperformance and new functions that could make ease the power sequencing of modern ASIC, FPGA,
I36 MPU. N H L 600TDE open, CTB (SI051) 3 5 2022 2023SI051
Evaluation and Qualification of rad- Evaluation and Qualification of rad-hard PWM Other
hard new generation PWM European
Institution
Programme
I37 R 200s (OEIP) FR ST, CTB (SI105) 2019 2022SI105
Assessment of Companion chips of Assessment of Companion chips of NX FPGAs: COTS Boot memories. Identify COTS, evaluate them new line. Pushed by the SiWG? 3D
NX FPGAs: COTS Boot memories PLUS: We are developing now SPI,
Other ESA SPI TMR, FUSIO RT, POL products
Programme with COTS components. Can
I38 N H H 800s (OEP) coordinate with ESA, CTB (SI039) 2022 2024SI039
Development of a radiation hard Recent studies has demonsrated the suitability of CBRAM for usage as TID hard products (medical). A recent
CBRAM for space applications + reliability study by NASA has confirmed the data retention specification and the usage for applications which
reliability characterisation. require less than 100 re-writes. Therfore, this technology is higly attractive for EEPROM replacement, but
particularly also as an option for embedded memories (for mixed signa ASICs). Within this activity, the Other ESA Open; 3D PLUS: We think that
commercial design shall be modified in order to harden the product agains SEE as well. A detailed reliability Programme CBRAM is not mature for space.
I39 cheracteristation would be done as well. N H L 1000s (OEP) Dates pushed by JLC, CTB (SI039) 2 4 2022 2024SI030
Assessment of Advanced Non Within the European industrial landscape, promising, novel NVM technologies are found to be currently
Volatile Memories for Space under research and development. Examples include but are not limited to solutions such as new Magneto-
resistive RAM (MRAM), memory based on Ferroelectric Transistors (FeFET), Phase-Change Memory (PCM)
and Resistive RAM’s (RRAM). Objective is to select and characterize a novel innovative European technology Engineering Minds Munich (DE),
enabling high-density and rad-hard NVM for future space applications NaMLab (DE), FHG (DE)
I40 R 300TDE DE CTB (SI060) 1 3 2021 2023SI060
MNEMOSYNE: Magnetic Non- radiation hard by design high density NVM based on 22 nm FDSOI Magnetic RAM (MRAM) technology Other
NolatileRandom-Access Memory (GLOBALFOUNDRY). European 3D+ (F), IMC (B), UNPD (I),
for SPACE with Serial Interface Design and prototype a 128Mb Magnetic NVRAM for SPACE with serial interface. Institution NanoXplore (F), RUAG (SW), TRAD
Package based on 3D stacking. Programme (F) MNEMO
I41 Reliability and radiation testing on the basis of the ESCC test flow. R 3000s (OEIP) CTB (SI070) 2020 2022SYNE
Rad-hard All-digital Frequency All Digital PLL ASIC for telecom applications
ARTES AT.
Synthesizer in 65nm CMOS
I42 R 500ARTES BE MAGICS 2 4 2021 20235C.482
TM/TC Mixed Signal ASIC development and qualification of a mixed signal ASIC to be used inside the Airbus-Crisa next generation of
Remote Terminal Units in order to drastically reduce the number of discrete parts and thus reduce mass and G627-
I43 cost of the unit. The device has been specifically designed to fit the AIrbus RTU/RIU units. R 823GSTP ES ADS CRISA 3 6 2016 2022075ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 51
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
AIM I rad-hard ASSP family
Space-Fibre Interface Chip Development of SpaceFibre Interface IP Core and HW validation/demo setup
T101-
I44 R 600TDE UK StarDundee (UK) 2 3 2017 2021401ED
Repeater, Multiplexer and Switch ICDevelopment of a CML/VML crossbar-switch for SpaceFibre and other high-speed protocols
T723-
for high speed communication
I45 R 600TDE FR NANOXPLORE (FR) 2 3 2021 2022612ED
Analysis and demonstration of In current spacecraft analogue telemetry lines are common place leading to many pin connectors on OBCs
scalable transceiver ASIC and RTUs together with substantial cable and connector mass. However these analogue telemetry lines
architectures for digital buses consist mostly of two wires and have a high degree of redundancy and low latency response. Digital buses
would provide a more scalable interface, reduce mass, power but lose redundancy and latency. The activity
will analyse the different ASIC tranceiver architectures as used in automotive that keep the advantages of Other ESA
digital buses and minimise the loss of redudancy and latency. The aim is to identify and demonstrate the Programme
I46 optimum scalable digital bus transceiver ASIC architecture for optimum reliability, latency and througput N H H 300s (OEP) TDE, ARTES, EOP 2 3 2022 2023
SpaceFibre: Development of This development has been in the pipeline for many years and would now be useful in the context of
SpaceFibre interface ASIC backplane applications such as ADHA. IP cores for both interface chip and routing switch functions are AIM B - Group 3: High speed serial
readily available and could be implemented e.g. in ST 28nm process. An external SERDES device incl. SpFi link protocols (WizardLink,
protocol engine would significantly reduce required design efforts and IP costs and improve reliability, SpaceFibre, SRIO etc.)
I47 interoperability, and fault isolation while offering much higher data rates than existing solutions (TLK2711). N H M 2500GSTP link to B23 activity. 4 6 2022 2024
Qualification of Powerlink ASIC Full qualification of Powerlink ASIC that allows data and power transmission over one command & control
link
AIM B - Group 4: Others links
I48 N H L 2000GSTP (Wireless, Powerlink) 4 6 2022 2024
Improve and expand the European
IP Cores catalogue and respective
AIM J Design Methods and Tools
ESA IP Cores Automated software tool in Python to manage the ESA IP Cores, run the design flow in an automated way (simulation, UNIV DE LAS PALMAS GRAN TSS20-
J01 Benchmarking synthesis, P&R) and generate results in different technologies R 45TDE ES CANARIA (ES) n/a n/a 2019 202103ED
ESA IP core extensions 1) flexible Floating Point Unit (FPU) for half- single- and double-precision operations, 2) SIMD-within-a- TSS20-
J02 register (SWAR) instruction extensions, 3) evaluate and develop extensions for the NOEL-V RISC-V IP-core. R 214TDE CZ 3 4 2017 202105ED
Universal VHDL Verification improved UVVM (Universtal VHDL Verification Metohdology), an FPGA (and digital ASIC) verification T701-
J03 Methodology extension environment, extending the randomization, the functional coverage and the regression testing capabilities R 350TDE NO BITVIS (NO) 2 4 2021 2021608ED
Hardware/Software co-design: Virtual Platform to perform Design Space Exploration of processing systems with models relevant to space T701-
J04 design flow demonstration (LEON2, SpW, SpF, CCSDS Compression….) VP will be made available via ESA IP Core services R 400TDE DE TERMA (DE) 2 3 2020 2022602ED
Evaluation of ESA IP Cores with Upgrade of Abeto tool used for ESA IP Cores technical maintenance, including automated procedures for
modern verification tool verification with modern tools TSS21-
J05 environments F 24TDE ES IUMA (ES) n/a n/a 2021 202203ED
Low-Power High-Resolution Rad- ADC IP Core and test chip in DARE180
Hard Analog-to-Digital Converters Other ESA
for Next Generation Space Image Programme NPI. NPI 553-
J06 Read-Out Integrated Circuits R 60s (OEP) BE CSIC (ES) 2 4 2019 20222017

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 52
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
IP Cores catalogue and respective
AIM J Design Methods and Tools
Independent validation and Blue Pearl static analysis tool will be applied to all ESA IP Cores as additional independent
optimisation of recently developed Other ESA Maint
IP Cores: [3] extend Blue Pearl Programme E21-21-
J07 static analysis to all ESA IP Cores F 25s (OEP) UK INFRA. n/a n/a 2021 202103
Independent validation and Validate SpW-DMA wrapper for LEON2FT IP with UVM platform
optimisation of recently developed
IP Cores: [1] Validate SpW-DMA Other ESA Maint
wrapper for LEON2FT IP with UVM Programme INFRA. E21-21-
J08 platform F 25s (OEP) IT IngeniArs(IT) n/a n/a 2021 202101
SpW Interface IP for BRAVE FPGAs SpW Interface IP tailored for BRAVE FPGAs, to become part of ESA IP Cores catalogue Other ESA
Programme INFRA> Maint
J09 R 40s (OEP) SI SkyLabs (Slovenia) 2 3 2021 2021E21-05
Upgrade of SHyLoC Ip Core to Issue Several upgrades of ESA IP Core SHyLoC (lossless data compression) to Issue 2 based on the CCSDS 123.0-B- Other ESA
2 of the CCSDS 123.0-B-2 standard 2 standard (released in Feb. 2019) Programme INFRA. Maint
J10 R 40s (OEP) ES IUMA(ES) 2 3 2021 2021E21-04
Independent validation and Port an ESA IP Core to BRAVE NG-Medium FPGA in order to gather useful information for the IP users and
optimisation of recently developed for the NX FPGA tool maintenance team Other ESA Maint
IP Cores: [2] Port an ESA IP Core to Programme E21-21-
J11 BRAVE FPGAs F 25s (OEP) ES SENER(ES) n/a n/a 2021 202102
Novel radiation hardened All-Digital Development of an All Digital PLL design IP as part as an ESA co-funded PhD Other ESA
Phase-Locked Loop/Clock-Data Programme NPI 610-
J12 Recovery (ADPLL) R 90s (OEP) BE NPI, University of Leuven (BE) 2 3 2019 20212018
Lossless/lossy multispectral & produce a reusable VHDL model of the IP Core implementing CCSDS 123.0-B2 Standard for the ESA IP Cores T701-
J13 hyperspectral compression IP core portfolio, including near-lossless compression F 250TDE 2 3 2021 2023701ED
IP CORE DEVELOPMENT FOR IP Core implementing High Photon Efficiency optical communication coding and synchronization as defined
CCSDS-BASED OPTICAL PAYLOAD in CCSDS 142.0-B-1 and On-Off-Keying optical communication coding and synchronization
J14 DATA TRANSMITTER F 400ARTES 2 3 2021 20223C.021
FPGA implementation of artificial The objective is to investigate how to efficiently implement convolutional neural networks (CNNs), and
neural networks on-board satellites propose a working framework, a design methodology and the analysis of the key trade-offs to generate
J15 CNNs that can be efficiently implemented on space qualified FPGAs. N H L 500TDE TDE, GSTP 2 4 2022 2024
Improving connectivity of ESA IP Current ESA IP Cores are mostly based on AHB standard bus. Nevertheless ARM based processors are based
Cores: implementation of AMBA on AXI, and have generated their IP ecosystems around it. Enabling ESA IPs to work with AXI makes it easier
AHB to AXI bridge and Direct for users to integrate them in ARM based processors such as the ones embedded in BRAVE or Xilinx. Direct
Memory Access Memory Access (DMA) capabilities are highly desirable to enable high bandwidth communication between a
processor and an external memory. The objective of this activity is to implement a Direct Memory Access
J16 (DMA) IP Core and an AHB to AXI bridge for the ESA IP Cores library. N H M 400TDE 3 5 2022 2022
New IP Cores for Space applicationsOn demand, depending on project needs, such as support to high speed interfaces (JESD204B), channel
J17 coding, LDPC (low density parity codes). N H L 400TDE place holder for misc new IP Cores 2 4 2022 2023 J05

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 53
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
IP Cores catalogue and respective
AIM J Design Methods and Tools
Validation Test Functional Coverage Functional Coverage Methodology is an established method in the digital design to ensure in simulation that
Methodology the HDL is fully tested as well as covers the requirements of the application fully. For SW instrumentation of
the code is common practice to establish on target these functional coverage statistics. Recently
development in digial design allows these days to instrument the (V)HDL for the FPGA/ASIC to determine
the hardware (validation) test coverage. This study aims to establish a methodolgy that allows the
determination during the validation testing of the functional coverage of the digital design. The generated
methodology allows to determine in orbit whether units operate in a validated tested or Other ESA
unvalidated/unverified state. This would allow the identification of potential risky (unvalidated) operation of Programme
J18 the equipment in orbit. N H L 200s (OEP) TDE, OSIP, n/a n/a 2021 2022
Supervisor for COTS FPGAs Solutions for monitoring the health of COTs FPGAs and scrubbers are needed to ensure these devices can be
used on-board. Some implementations such as GRSCRUB (Gaisler) or SEMIP (Xilinx) are already offered in
the market targeting Xilinx FPGAs. This activity aims at developing a generic solution that works for multiple
FPGA targets, and that besides scrubbing, includes more advanced supervisor functions, such as managing
reconfiguration (total or partial), monitoring events that could lead to catastrophic failures, and balancing
J19 and scheduling tasks in a multi-FPGA cluster. The solution can take the shape of an IP core or software. N H M 500TDE 3 5 2022 2024
Hardware/Software co-design: A Virtual Platform is a software based system that can fully mirror the functionality of a target System-on-
implementation of new IP models Chip or board. These virtual platforms combine high-speed processor simulators and high-level, fully
(RISC-V ISA) functional models of the hardware building blocks, to provide an abstract, executable representation of the
hardware to software developers and to system architects. The activity aims at developing new SystemC or
high level description models of RISC-V to be incorporated to the Virtual Platform we have already
developed, making it useful also for RISC-V-based architectures. A high level abstraction model of RISC-V
can be used for early software development, and to emulate SoC architectures for benchmarking and
verification, accelerating the implementation. It will also be useful to understand and debug HW/SW possible extension to a running
J20 interactions where RISC-V is involved. N H M 300TDE DE activity with TERMA 2 4 2022 2023 J04
Model Based Design for The commercial tools addressing Model based Design (MBD) for microelectronics have been maturing
Microelectronics, including considerably in the last years. CatapultC has already been successfully used for ASICs in Space for years.
"autocoding" More afforable options are also being used: Xilinx's HLS and the technology independent flow from
Mathworks including HDL Coder. Also academic tools like Bambu (from POLIMI) have evolved consierably.
This activity aims to review the different flows available and perform an evaluation. Other two important
aspects are on the management of the "autocoding" of the MBD within the microelectronics stardard; and
J21 the links of the microelectronics MBD to higher level MBDE. N H L 300TDE 2 4 2022 2023
Radiation-aware tool to optimize The KU060 FPGA from Xilinx requires the application of design mitigation techniques against radiation.
designs for COTS FPGA, intially Currently Xilinx does not provide a tool to implement TMR (like the past XTMR). There are commercial tools
addressed to KU060 FPGA available to address that implementation (from Synopsys and Mentor). Those do not take into consideration
the Placement and Routing constraints; and Xilinx has already notified that such constraint will be required.
This activity proposed to port the VERIPlace tool from POLITO that addressed this issue for previous Xilinx
technologies. It includes the development and validation though radiation tests and a test case with
J22 industry. N H M 150TDE 2 5 2021 2023
Fault Injection system for KU060 This activity aims to develop a Fault Injection system that teams developing could use in their validation
FPGAs campains of the design mitigation techniques. It can be based on an evolution of the FT-UNSHADES2 (FTU2),
J23 or a lighter version ported to commercial hardware. N H L 100TDE 3 5 2021 2023
ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 54
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
IP Cores catalogue and respective
AIM J Design Methods and Tools
Conformance Test Suits for key The MIL-1553B bus has a well defined physical and protocol SAE AS4111-5 test suite, which allows the
space data communication IP Cores effective verification of the data communication bus. Currently for the SPI, CAN, SpW, .. no such baseline
test suite exists either for simulation or testing/validation and a plethora of tests suites with varying degree
of functional coverage exists. This activity aims at developing for the the key space data communication
interface IPCores a test suite for verification (that could also be used for validation) that ensures good
J24 functional coverage N H M 250GSTP n/a n/a 2022 2023
Identification of Analog Hardware The development of mixed-signal ASICs requires the development of a model to allow the board/application
Description Language for board engineers to simulate the system before build. Different analog hardware description languages exist (spice,
level CAD tool use Verilog-A, VHDL-AMS, ...) however the level of detail, simulation speed and support varies for each language Other ESA
for the different board design CAD tools. This study aims to identify the most suitable candidate for analog Programme
J25 models for space components for the tools currently in use by the space community N H M 150s (OEP) TDE, OSIP n/a n/a 2022 2023
High throughput bus interconect IP A study of emerging new interesting options ASIX bus interconnection technologies (e.g. AXI*n) for in high Other ESA
data throughput (>100Gbps) space ASICs Programme
J26 N H M 100s (OEP) TDE, OSIP n/a n/a 2021 2022
Space foundry process Radiation This activity aims at customising the radiation tool for key space ASIC foundry processes (including UDSM) The commercial ASIC design tools lack the
TCAD customisation for high frequency and power applications incorporating with the foundry permission key process data. This capability to simulate radiation effects at
enables radiation TCAD simulation to predict accurately the radiation behaviour and allows the optimisation transistor level for digital and mixed-signal
of high-speed and high reliability transistor circuits. Optional: radiation testing of existing test vehicles for designs. In the recent years radiation TCAD
improved calibration. tools proved to be capable to simulate
these radiation effects for the foundry
process in the design with results that
match the radiation tests. It has become
practice to simulate all new transistor
potential radiation sensitive structures
during the design phase to reduce
significantly the risk of radiation
weaknesses in new ASIC design, especially
for high frequency and high reliability
power ASICs. However the customisation
of the radiation TCAD tool for optimum
accuracy requires calibration and foundry
process details, which are limited in
J27 N H M 250GSTP availability during the ASIC development. n/a n/a 2022 2023
DSP accelerator IPs for RISC-V and Development of DSP accelerators which are loosely coupled to a CPU via an on-chip bus (e.g. AXI4 / AHB) or
other microprocessors network. Can be used on SoC-FPGA, on ASIC or on eFPGA blocks inside an advanced microprocessor chip.
Development of SW drivers and demonstration together with RISC-V on COTS-FPGA. Possible DSP functions:
image/video compression, FFT, GNSS (see also AGGA-5 from EOP), Crypto, AI / ML cores (CNN - T701-
J28 Convolutional Neuronal Networks). N H M 500GSTP 1 3 2022 2023 702ED

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 55
 Proposed Roadmap – Cost tables
TRL level Date Follow-
Act. up on
Budget
Ref. Title Description Status Urg Crit. Prog Country Remark Applicable Missions Prog. another
(kEuro) Curr. Targ. Start End Ref. RM
Activity
Improve and expand the European
IP Cores catalogue and respective
AIM J Design Methods and Tools
Space Rated Microcontroller The activity validates the design of the PicoskyFT 16-bit soft core processor and develop an HW GT17-
J29 Softcore - Product development demonstrator for IOD. R 480GSTP SI SkyLabs 4 6 2018 2021121ED
Radiation characterization and activity aims at identifying a selection of COTS components that are of special interest to European space
functional verification of COTS industry/missions, develop radiation test plans and HW/SW rad test envirininment and perform rad tests
components for space applications. GT17-
J30 (RACOCO) R 1200GSTP DE Fraunhoffer 3 5 2019 2022008QE
ADHA IP Cores The objective of this activity is to develop specific IP cores to ease the development of ADHA modules in
multiple functional areas/IC building blocks :
- generic switch on/off and power status acquisition
- CFDP to support file based operations
- High Speed Interface ADHA roadmap, discussed with
J31 - CAN-bus tailored for ADHA N H M 450TDE ADS/TAS/RUAG generic missions using ADHA 3 5 2022 2025
Development of TSN IP for End- One next step in development of TSN is availability of IP for RadHard platforms. Possible way forward would AIM B - Group 2: Ethernet and
system and Switch for Rad-Hard be to use of commercially existing IP (in Europe there are 4-5 providers) and to modify those to include Ethernet-based determinsitic
FPGAs radiation mitigation techniques. Other option is the development of new TSN IP cores tailored for space protocols (TTE, TSN), relates to B09 Launchers, Human Spaceflight, T701-
J32 applications and ADHA. N H M 600GSTP and B12/B13/B14 NewSpace 4 6 2022 2024704ED
Minimal Time-Triggered Ethernet Develop, verify and validate an IP core that supports Time-Triggered End-System interface as per ECSS-E-ST-
End-System standard IP core 50-16C, with the purpose of enable a minimal implementation.
implementation The main characteristics are the following: Only Synchronisation Client, 1-3 Ethernet interfaces, 100BaseTx
and 1000BaseT, Time-Triggered and Best-Effort traffic classes only, minimal UDP/IP tailoring, AXI/AHB
interface with optional DMA, validation in NG-Large (TBC).
The main Outcomes are: HDL IP + simulation verification environment + validation campaign in the ESTEC
J33 Avionics Laboratory TTE Test-Bed. N H M 400GSTP Launchers, Exploration 3 5 2021 2022

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 56
Proposed Roadmap – Schedule

Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM A: Define and adopt unified OBCDH architectures based on modules

ADHA CONSOLIDATION, STANDARDISATION, AND PRODUCT SUITE DEVELOPMENT with consortia
A01 1000 TRL 2 OEP TRL 6
one
ADHA-2 activity called
A02 1000 TRL 2 EOEP TRL 6
ADHA CONSOLIDATION, STANDARDISATION, AND PRODUCT SUITE DEVELOPMENT with consortia
A03 ADHA unit qualification M H 15000 A01, A02 -> TRL 6 GSTP TRL 8
AIM A

A04 ADHA Standards and Hand Book H M 50 TRL 2 TDE TRL 6

A05 OBC DHS electrical OBCDHS architectures study for high reliability missions types. H H 1000 TRL 3 GSTP TRL 5
A09 Study of OBCDHS architectures based on microcontrollers H L 700 TRL 3 TDE TRL 4
A10 Standardisation of backplane connector for nanosatellites M M

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 57
Proposed Roadmap – Schedule
Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM B: Design, develop, manufacture and qualify buses, network and communication technologies
B01 WP2016 SpaceWire Network Management Service Suite Definition and Validation (PTRP) 450 T701-501ED TRL 3 TDE TRL 4
B02 EXPRO: SpaceWire Repeater Development 47 TSS20-06ED TRL 2 TDE TRL 4
B03 SpaceWire Time Synchronization Protocol H H 300 TRL 2 TDE TRL 4
B04 SpaceWire Network Management H M 400 TRL 2 TDE TRL 4
B05 Galvanically Isolated SpW Physical Layer M M 450 TRL 2 TDE TRL 4
B06 Elements of TTEthernet based Avionics : TTEthernet Switch , TTEthernet End System and TTEthernet 1500 GT17-193ED TRL 4 GSTP TRL 5
B07 Elements of TTEthernet based Avionics : TTEthernet Switch , TTEthernet End System and TTEthernet H M 1500 B06 -> TRL 5 GSTP TRL 7
B08 De-risk assessment: TTE memory Cpcimm 195 G617-241TAge TRL 2 GSTP TRL 4
B09 SpaceTSN Definition and Demonstration 500 T701-704ED TRL 2 TDE TRL 4
B10 Ethernet4NGSpace 200 PL_218 TRL 2 TDE TRL 4
B11 Characterisation of passive Ethernet components H H 400 TRL 4 GSTP TRL 6
B12 Characterisation of TSN-enabled COTS devices H L 200 TRL 2 TDE TRL 4
B13 Analysis and validation of TSN in context of SAVOIR (NPI/PHD) H M 60 TRL n/a OEP TRL n/a
B14 Demonstration of functionality and intercompatibility of TSN H M 50 TRL n/a TDE TRL n/a
AIM B

B15 WP2015 - Space-Fibre Interface Chip (PTRP) 600 T101-401ED TRL 2 TDE TRL 4
B16 RTG4 SerDes Irradiation Test Campaign for SpaceFibre Applications 25 TSS19-02ED TRL n/a TDE TRL n/a
B17 2018 TRP SS Network Discovery and Configuration Protocol for SpaceFibre 25 4000126296 TRL n/a TDE TRL n/a
B18 Demonstration of SpaceFibre Technology Usage for Image Processing Applications 200 PL_274 TRL 2 OEP TRL 4
B19 FiMan - SpaceFibre Network Management 240 PL_171 TRL 2 OEP TRL 4
B20 HSSL General: Development of a physical test specification for SERDES-based protocols H H 500 TRL 2 TDE TRL 4
B21 HSSL General: Environmental testing of COTS SERDES and other HSSL components M M 200 B20 -> TRL 2 TDE TRL 4
B22 SpaceFibre: Network Management M M 200 TRL 2 TDE TRL 4
B23 SpaceFibre: Investigation of other encoding schemes M L 50 TRL 2 TDE TRL 4
B24 Investigation of Radiation tolerances and designs of Ultra Wide Band wireless solutions. 600 T401-601ED TRL 3 TDE TRL 4
B25 WAIST-3 205 RO_78 TRL 5 OEP TRL 6
B26 WISAT-3 526 RO_79 TRL 5 OEP TRL 6
B27 Follow-up: Wireless activity with the title "Investigation of Radiation Tolerances and Designs of Ultr H L 600 B24 -> TRL 5 OEP TRL 6
B29 Development of an FPGA-based DTN+CFDP implementation optimised for high-speed file data down H M 500 TRL 1 TDE TRL 3

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 58
Proposed Roadmap – Schedule

Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM C: Design, develop, manufacture and qualify OBCDH modules (including AI, ML and COTS with adequate radiation mitigation techniques)
C01 De-risk assessment: Computer Module Maturation Campaign 150 G617-241TAel TRL n/a GSTP TRL n/a
C02 COTS-based highly integrated computer system for mini/nano satellites 800 GT17-021ED TRL 2 GSTP TRL 5
C03 On-board control unit for ICE Cubes experiments 200 GT17-201ED TRL 4 GSTP TRL 6
C04 Single Board Computer. Phase 3 3400 GT1Z-503ED TRL 3 GSTP TRL 6
C05 Generic digital board development for a Next Generation (NG) On-Board-Computer 1500 GT27-043ED TRL 2 GSTP TRL 4
C06 De-risk assessment: High data-rate bus for Cubesat 200 G617-241TAew TRL n/a GSTP TRL n/a
C07 ADHA On-Board Computer Module (AOBCM) 500 T701-703ED TRL 2 TDE TRL 6
C08 Fault-Tolerant and Commercial Off The Shelf-based On Board Computer (P0) 1000 4A.060 ARTES
C09 Reconfigurable System-on-a-Chip for Future Telecom Constellations (APSoC) 1000 4G.024 TRL 3 ARTES TRL 5
C10 Activity supporting the development and qualification of 2 ADHA OBC modules (N+R) based on the B H H 1500 EC prg DAHLIA -> TRL 3 GSTP TRL 8
C11 Activity supporting the qualification of 2 ADHA OBC modules (N+R) based on the GR740. H H 1500 TRL 3 GSTP TRL 8
C12 Reference design and basic software for a single board computer based on GR740 600 T701-603ED TRL 2 TDE TRL 4
C14 Assessment of FPGA-based RISC-V OBC for CubeSat H M 500 TRL 2 GSTP TRL 4
C15 ADHA processing module based on RISC V processor M H 500 TRL 1 GSTP TRL 6
C16 OBC for Suborbital rocket 0 TRL 1 INP [PL] TRL 6
POIR 01
C17 ANTELOPE: On-board computer with predictive maintenance 2300 TRL 1 OEIP TRL 9
01 01
C18 FURYO - File management based Ultraperformance mass memoRY for On-board 720 GT27-035ED TRL 4 GSTP TRL 6
C19 ADHA Mass Memory Module (A3M) 500 T101-701ED TRL 2 TDE TRL 4
C20 ​Memory control sub-system for low earth orbit applications 700 4G.035 ARTES
C22 De-risk assessment: Next Generation Remote Interface Unit Architecture 200 G617-241TAdp TRL 2 GSTP TRL 3
C23 picoRTU system - Detailed Design and Qualifications - Phase 1 - CCN follow on de-risk 400 GT17-401ED TRL 5 GSTP TRL 7
C24a Prototype Remote Interface Unit (RIU) for SWE hosted payloads 650 GT18-001ED TRL 4 GSTP TRL 6

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 59
Proposed Roadmap – Schedule
​

C24b Prototype Remote Interface Unit (RIU) for SWE hosted payloads (CCN) 250 GT18-001ED TRL 4 GSTP TRL 6
AIM C

C26 ADHA Generic I/O Module H H 500 TRL 2 GSTP TRL 4

C27 ADHA I/O Propulsion Module H M 500 TRL 2 GSTP TRL 4
C28 ADHA I/O Module for driving AOCS sensors and actuators (as previous RTU modules are doing) H M 500 TRL 2 GSTP TRL 4
C29 ADHA Motor Drive Electronic Modules (to be used ADHA ICU unit). H M 500 TRL 2 GSTP TRL 4
C30 ADHA Step Motor Drive Electronic Modules H M 500 TRL 2 GSTP TRL 4
C31 ADHA I/O Module based on Data Concentrator Technologies H H 750 TRL 2 GSTP TRL 4
C32 High Performance Reconfigurable Processing Module (HiPeR-Pro) 1000 GT17-022ED TRL 3 GSTP TRL 5
C33 Space Qualification and reference designs for Myriad Video Processor - Architecture for In-Orbit AI - 270 GT17-165ED TRL 4 GSTP TRL 7
C34 Improving radiation tolerance in heterogeneous computing for data processing (IMPRO-DP) 250 GT27-052ED TRL 4 GSTP TRL 6
C35 Dependable Avionics Processing Module using COTS Reconfigurable Systems-on-Chip 750 T701-705ED TRL 2 TDE TRL 4
C36 FPGA accelerated DSP payload data processor board 500 T101-501ED TRL 2 TDE TRL 4
C37 Miniaturized DSP / Processor Board for Science and Robotic Exploration using Bare-Die-on-PCB Mou 400 T201-034ED TRL 3 TDE TRL 5
C38 ​Adaptive compute acceleration platforms ​for satcom 800 5C.435 TRL 3 ARTES TRL 4
C39 Synthetic vision module based on GR740 H M 700 TRL 3 GSTP TRL 6
C40 ADHA Processing Module based on COTS Parallel Processor H M 600 TRL 3 GSTP TRL 6
C41 Intelligent Space Camera 300 G617-241TAgt TRL 2 GSTP TRL 8
C42 Development of Cubesat Processing Module based on Versal FPGA L M 300
C44 ADHA Module to increase in-flight satellite knowledge H M 500 TRL 2 GSTP TRL 6
C46 ADHA GNSS Receiver Module (if not integrated in the OBC) H H 1200 TRL 2 GSTP TRL 6
C47 LION H L 250 TRL 3 GSTP TRL 4
C48 ADHA Instrument Power Distribution Module (to be used in ADHA ICU unit). H M 500 TRL 2 GSTP TRL 4
C49 Live Support Interface Board for CubeSats L M 400
C50 Activity supporting the qualification of 2 ADHA Mass Memory Module (A3M) (N+R or N+ Ext). M H 1000 TRL 4 GSTP TRL 8

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Proposed Roadmap – Schedule

Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM D: Develop Building Blocks to support OBCDH module(s) development(s)

D01 Reliable functional blocks for critical functions in COTS based OBCs H M 800 TRL 3 OEP TRL 5
D02 Building blocks for energy constrained missions M M 800 TRL 3 GSTP TRL 5
D03 Reference designs and radiation characterisation of board based on COTS components (functional b H L 600 TRL 3 OEP TRL 5
D04a Machine learning application benchmarking on COTS inference processors 600 GT1I-302ED TRL 2 GSTP TRL 4
D04b Machine learning application benchmarking on COTS inference processors - Parallel contract 600 GT1I-302ED TRL 2 GSTP TRL 4
D06 AI for non mission critical on board data processing 1000 GT1I-305ED TRL 4 GSTP TRL 6
D07 Robust machine learning systems for dependable space applications 600 GT1I-306ED TRL 2 GSTP TRL 4
D08 Set-up of reference benchmark for evaluation of Neural Networks H H 600 TRL 3 GSTP TRL 6
D09 Benchmark FPGA/IP to accelerate ML for space applications H M 800 TRL 3 GSTP TRL 5
D10 Benchmark COTS HW accelerators to support ML for space applications H M 600 TRL 3 GSTP TRL 5
D11 Evaluation/Assessment of Neural Morphic techniques (spiking computing) H M 400 TRL 2 TDE TRL 4
D12 Nonlinear channel modelling and identification of digital communications using ANN H M 600 TRL 2 ARTES TRL 4
D13 Channel equalization using artificial neural networks H M 600 TRL 2 ARTES TRL 4
D14 Coding, decoding, and error correcting codes using artificial neural networks H M 600 TRL 2 ARTES TRL 4
D15 Evaluation of radiation hardened GPU and ML system-on-chip H M 400 TRL 2 GSTP TRL 4
D16 Upscreening and qualification of COTS parallel processor H M 800 TRL 5 GSTP TRL 7
D17 CNN inference engine and framework for HPDP H M 300 TRL 3 GSTP TRL 5
D18 Radiation testing and evaluation of COTS GPUs and AI accelerators M M 300 TRL 3 GSTP TRL 5

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Proposed Roadmap – Schedule

D19 Evaluation of techniques for in-memory-processing M M 150 TRL 2 TDE TRL 4

AIM D

D20 Acceleration of RNN for video processing H L 250 TRL 2 TDE TRL 4
D21 OBPMark benchmarks for on-board data processing H M 400 TRL 3 GSTP TRL 4
D22 Improvement of Reliability of CubeSat Design (NPI) M M 60
D23 Interoperability of FlatSat with 3rd Party Sub-Systems (YGT) M M 0
D24 Extension of FlatSat with Payload Processing Capability (YGT) M M 0
D25 Learned image compression H L 200 TRL 2 TDE TRL 4
D26 Compression of Bayer (or other CFA) filtered images H M 200 TRL 2 TDE TRL 4
D27 Integration of CCSDS 124.0 (HKTM compression) in ADHA OBC module (as qualified SW or IP Core) H M 250 TRL 3 GSTP TRL 5
D28 General purpose video compression H L 250 TRL 3 GSTP TRL 5
D29 Reference onboard image datasets: Cloud detection H H 200 TRL 3 OEP TRL 6
D30 Computational imagery: onboard processing for optical payload performance H M 350 TRL 2 TDE TRL 4
D31 Real-time HW/SW demonstration of WFE metrology algorithms for Active optics H L 400 TRL 3 GSTP TRL 5
D32 AI-based sensorless WFE estimation on payload data. Benchmark against traditional approaches M L 150 TRL 2 TDE TRL 3
D33 Analysis Ready Data: Optimized onboard image product generation (preprocessing for onboard ML) H L 200 TRL 3 OEP TRL 4
D34 Low latency event detection and delivery. Payload processing and data handling system demonstrat H L 250 TRL 2 OEP TRL 4
POT spectral preprocessing HW implementation CCSDS 122.1.
D35 M L 250 TRL 3 TDE TRL 4
KLT approximation for dimensionality reduction (key for ML applications)
D36 Novel payload data compression techniques H M 400 TRL 2 OEP TRL 3
D37 CCSDS 125.0-B: Future SAR raw data compression Standard H H 300 TRL 3 OEP TRL 4
D38 Efficient Video Compression for space H M 300 T301-701EF TRL 2 TDE TRL 4

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Proposed Roadmap – Schedule

Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM E: Develop EGSE to support the test and integration of OBCDH units/modules and benefit of synergies and commonalities
E01 Multi-protocol on-board communications network manager 220 GT17-200ED GSTP
E02 ECSS-E-ST-50-15C CAN conformance tester M H 300
AIM E

E03 EGSE to test ADHA Modules when integrated in a ADHA rack H H 300 TRL 2 GSTP TRL 6
E04 EGSE to test an ADHA unit H H 1000 TRL 2 GSTP TRL 6
AIM F: Enhance characteristics/functions of current ASIC Platforms and develop USDM ASIC Platforms
F01 Definition of Radiation Effects Mitigation Techniques for Ultra-Deep Submicron Technologies 500 T523-601ED TRL 2 TDE TRL 3
F02 High Speed and Low Power Die-to-Die Interconnects in a Package - CCN1 720 G627-060ED TRL 3 GSTP TRL 5
F03 DARE 65 - Implementation, Evaluation, and Release of a Radiation Hardened Mixed-Signal Cell Libra 3300 G617-173ED TRL 3 GSTP TRL 6
F04 ​Ultra deep submicron assessment for on-board digital processors 2000 5C.443 TRL 2 ARTES TRL 4
F05 DARE65 analog/mixed-signal IP development for instrumentation, control and interfacing applicatio H M 3000 TRL 3 GSTP TRL 5
F06 analog/mixed-signal IP development for power conversion and control applications H H 1000 TRL 2 GSTP TRL 5
AIM F

F07 Radiation hardening of High-Speed Die-to-Die Interface H M 1000 F02 -> TRL 3 GSTP TRL 5
F08 UDSM ASIC Platforms development and consolidation H H 5000 F02 -> TRL 3 OEIP TRL 5
F09 EFESOS: Evaluation of a 22nm or beyond ASIC process and flow 3385 EFESOS TRL 2 OEIP TRL 4
F10 Evaluation and Characterization of a Harmonized Mixed-Signal ASIC Flow 590 T723-305QT TRL 1 TDE TRL 4
F11 Development of a Deep Trench Capacitor for embedded DC-DC and Power Management in a mixed H M 450 TRL 2 OEP TRL 4
F12 Evaluation of LFoundry mixed-signal 150nm CMOS process (LF15A) for Space Applications 650 G617-202QT TRL 2 GSTP TRL 4
F13 PROMISE: Programmable Mixed Signal Electronics 2875 PROMISE TRL 3 OEIP TRL 5

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Proposed Roadmap – Schedule

Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM G: Improve and expand the European rad-hard FPGA family

G01 Strategies for reliable on-board reconfiguration of FPGAs 750 GT17-327ED TRL 2 GSTP TRL 4
G02 European FPGA with integrated ADC and DAC 500 T723-611ED TRL 2 TDE TRL 4
G04 SPRINT 2 - NG-Ultra prototypes production & bring up 2158 GT17-405ED TRL 3 GSTP TRL 4
G05 Evaluation of embedded FPGA (eFPGA) IPs and Tools H M 100 TRL 1 OEP TRL 2
G06 Demonstration of embedded FPGA (eFPGA) IPs and Tools M M 400 G05 -> TRL 2 TDE TRL 5
G07 Evaluation of PolarFire FPGA with embeded RISC-V for space applications H H 500 TRL 2 TDE TRL 5
G08 Evaluation of the design mitigation techniques of KU060 FPGA to define a flow for ESA missions H H 500 TRL 2 TDE TRL 5
G09 Reliability Evaluation of COTS complex IC (FGPA, u-controller, etc.) 500 PLATiNO TRL 2 INP [IT] TRL 6
G10 OPERA: BRAVE NG-LARGE. CCGA1752 Qualification and validation. SW design and optimization 3000 OPERA TRL 5 OEIP TRL 7
AIM G

G11 MARS: BRAVE NG-ULTRA, TV Derisking, Development, Organic packaging 21600 MARS TRL 4 INP [FR] TRL 5
G12 BRAVE, NG-ULTRA family Space Qualification -> Organic Package Qualification 3000 5C.448 TRL 5 ARTES TRL 7
G13 DAHLIA: SoC based on FDSOI28nm with multicore Cortex-R52 ARM processor 4000 DAHLIA TRL 2 OEIP TRL 4
Quality Assessment of the new European Ultra BRAVE FPGA Software Tools
G14 400 T725-705QQ TRL 2 TDE TRL 4
(Queens3)
G15 European FPGA with integrated ADC and DAC (BRAVE NG ULTRA-300) 2100 T723-611ED TRL 2 INP [FR] TRL 5
G16 Derisking Non Hermetic Flip-Chip for BRAVE FPGA 650 CNES TRL 2 INP [FR] TRL 4
G17 HERMES: Qualification of High pErformance pRogrammable Microprocessor and dEvelopment of So 3000 HERMES TRL 3 OEIP TRL 5
G18 DUROC: Design and validation of Ultra-Reprogrammable SoCs 3000 DUROC TRL 2 OEIP TRL 4
G19 Hardening Techniques for COTS FPGA for Digital TL Payloads 800 5C.416 TRL 2 ARTES TRL 5
G20 FPGA Programming Tools 5000 SI115 TRL 5 INP [FR] TRL 7

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Proposed Roadmap – Schedule
Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM H: Improve and expand the European rad-hard Microprocessors, Microcontrollers and DSPs
H01 GR740 Next Generation Microprocessor Flight Models (NGMP Phase 3) 950 G617-273ED TRL 4 GSTP TRL 7
H02 Digital Controller for Power Management 5741 4F.065 TRL 4 ARTES TRL 7
H03 SMT verification of the COBHAM GR 740 device with Micross/HCM columns 75 4000117598 TRL 3 TDE TRL 5
H04 Development of a multi core LEON5FT Space grade Microprocessor GR765 1000 GT27-088ED TRL 3 GSTP TRL 5
H05 RISC-V Microprocessor Prototype 450 T701-702ED TRL 2 TDE TRL 4
H06 RISC-V for space SW tool ecosystem H H 600 H05 -> TRL 3 OEP TRL 5
H07 RISC-V instruction extensions H M 500 H05 -> TRL 2 OEP TRL 4
H08 RISC-V instruction set extensions through embeded FPGA 23 TSS21-04ED H05 -> TRL 1 TDE TRL 3
H09 VGSM (5th Generation Space Microprocessor) RISC-V Engineering Models M M 2000 H05 -> TRL 3 GSTP TRL 5
H10 VGSM (5th Generation Space Microprocessor) RISC-V Flight Models M H 1000 H09 -> TRL 5 GSTP TRL 7
H12 GR712RC transfer of screening and electrical test H L 300 TRL 4 GSTP TRL 9
AIM H

H13 MORAL: Export Free Rad-Hard Microcontroller for space applications 3000 MORAL TRL 2 OEIP TRL 5
H14 Rad-hard ARM µP SAMRH71 1000 TRL 3 INP [FR] TRL 7
H15 Rad-hard ARM µP SAMRH71 System Solution 410 TRL 3 INP [FR] TRL 6
H16 Rad-hard Multi-core ARM µP 200 TRL 4 INP [FR] TRL 6
H17 Rad-Tol ARM µP SAM3X8E 250 TRL 4 INP [FR] TRL 6
H18 Rad-Tol ARM µC SAME54 125 TRL 4 INP [FR] TRL 6
H19 Rad-Tol Quad ARM µP QLS1046-4GB-Space 150 TRL 3 INP [FR] TRL 5
H20 ARM based MCU ("JAGUAR") 900 T701-505ED TRL 2 TDE TRL 4
H21 next Gen ARM MCU (GF 55nm) H M 500 TRL 2 INP [FR] TRL 5
H22 next Gen ARM MPU (28nm) H M 500 TRL 2 INP [FR] TRL 5
H23 Space mixed-signal Microcontroller with open Instruction Set Architecture on 65 nm or below H M 1500 F03 -> TRL 3 TDE TRL 5

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Proposed Roadmap – Schedule
Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM I: Improve and expand the European rad-hard ASSP family

I01 Dynamic Latch-Up / latching Current protection ASIC (LUCA) 720 T701-316ED TRL 2 TDE TRL 4
I02 Qualification of Latch-Up/latching Current protection ASIC H H 750 I01 -> TRL 4 GSTP TRL 9
I03 Development of a GNSS ADC ASIC 589 G611-048EO TRL 3 GSTP TRL 6
I04 Development of a wideband GNSS ADC ASIC H M 750 I03 -> TRL 2 OEP TRL 4
I05 6 Gigabits European Space Serializer-Deserializer (SERDES) under TSMC65 technology 617 GT27-086ED TRL 3 GSTP TRL 5
I06 High-Speed High Resolution Quad-ADC for Science Instruments 500 T201-052ED TRL 3 TDE TRL 4
I07 28 Gbps optical transceivers for space 535 5f.011 SL9010 TRL 6 ARTES TRL 8
I08 56 Gbps PAM4 VCSEL optical transceivers for space 500 TRL 2 ARTES TRL 4
I09 53 Gbit/s/ch Chipsets for VCSEL-based Interconnects in Space Application 1575 TRL 2 ARTES TRL 4
I10 56 Gbps silicon photonics optical transceiver for space 1000 5f.011 SL9010 TRL 2 TDE TRL 3
I11 Space qualification of 56Gbps VCSEL based transceiver M M 500 I09 -> TRL 5 ARTES TRL 9
I12 112Gbps optical transceiver for space M H 1000 I10 -> TRL 2 ARTES TRL 4
I13 Preparation of enabling space technologies and building blocks: Prototyping and initial evaluation o 450 GT17-137TIal TRL 3 GSTP TRL 5
I14 Mixed Signal ASIC Controller for DC-DC Power Converters (MISAC) - Phase B 894 P15-04 / PL_AD TRL 3 OEP TRL 5
I15 Space qualificaton of MISAC H M 500 I14 -> TRL 5 GSTP TRL 7
I16a Integrated Power Switch ASIC for small DC/DC converters 600 032EP / 400012 TRL 3 GSTP TRL 5
GT17-032EP /
I16b Integrated Power Switch ASIC for small DC/DC converters - parallel contract 600 TRL 3 GSTP TRL 5
4000126321
I17 ​On chip integrated power converter for advanced field programmable gate arrays ​ 1000 5C.440 TRL 3 ARTES TRL 4
I18 System Basis Chip for space H M 1000 TRL 2 OEP TRL 5
I19 Multi Channel PWM controller H M 750 TRL 2 OEP TRL 5
I20 High speed and resolution image detector front-end H M 1000 TRL 2 OEP TRL 4
I21 Development and Comercialization of state-of-the-art data converters (ADC/DAC) H M 1500 TRL 3 OEP TRL 5
I22 Multi Channel over-voltage and over-current protection ASIC H M 900 TRL 2 OEP TRL 4
I23 INTERSTELLAR: High speed Dual channel DAC 12 bit, 12 GSps 4000 INTERSTELLAR TRL 2 OEIP TRL 6

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Proposed Roadmap – Schedule
AIM I

I24 Design / Development and qualification of a cutting edge ADC (from Ka-Band), in Ultra DSM 500 TRL 2 INP [FR] TRL 7
I25 Characterization eV12AS940 0 INP [FR]
I26 Reliability Evaluation of COTS ADC, DAC 500 INP [IT]
I27 Developement and Qualification of 12bit DAC 503 INP [FR]
I28 European microwave capable ADC/DAC with high-speed low-power interfaces (XSR) for efficient SiP 10000 SIX16 TRL 2 ARTES TRL 7
I29 Development of a 2.5GHz, LVDS-based serializer (European TLK2711) 400 SI019 OEP
I30 Radiation hard VCSEL (Vertical-Cavity Surface-Emitting Laser) driver and receiver chain for high spee H M 600 SI020 TRL 3 TDE TRL 5
I31 Evaluation and qualification of a GMR sensor H M 200 SI021 TRL 3 TDE TRL 5
I32 Rad-hard LVDS Driver/Receiver Low voltage 400 SI113 INP []
I33 Development of a next-generation rad-hard, ultra low drop voltage regulator 500 T723-704ED TRL 3 TDE TRL 4
I34 Prototyping and characterisation of a monolithic, rad-hard, Voltage Clamp Integrated Circuit 270 T723-506QT TRL 2 TDE TRL 4
I35 Evaluation of on chip power conversion concepts for space ASIC technologies H L 1200 SI050 TRL 2 TDE TRL 4
I36 Development of a monolithic, rad-hard Power Sequencing Device. H L 600 SI051 TRL 3 TDE TRL 5
I37 Evaluation and Qualification of rad-hard new generation PWM 200 SI105 OEIP
I38 Assessment of Companion chips of NX FPGAs: COTS Boot memories H H 800 SI039 OEP
I39 Development of a radiation hard CBRAM for space applications + reliability characterisation. H L 1000 SI030 TRL 2 OEP TRL 4
I40 Assessment of Advanced Non Volatile Memories for Space 300 SI060 TRL 1 TDE TRL 3
I41 MNEMOSYNE: Magnetic Non-NolatileRandom-Access Memory for SPACE with Serial Interface 3000 MNEMOSYNE OEIP
I42 Rad-hard All-digital Frequency Synthesizer in 65nm CMOS 500 5C.482 TRL 2 ARTES TRL 4
I43 TM/TC Mixed Signal ASIC 823 G627-075ED TRL 3 GSTP TRL 6
I44 Space-Fibre Interface Chip 600 T101-401ED TRL 2 TDE TRL 3
I45 Repeater, Multiplexer and Switch IC for high speed communication 600 T723-612ED TRL 2 TDE TRL 3
I46 Analysis and demonstration of scalable transceiver ASIC architectures for digital buses H H 300 TRL 2 OEP TRL 3
I47 SpaceFibre: Development of SpaceFibre interface ASIC H M 2500 TRL 4 GSTP TRL 6
I48 Qualification of Powerlink ASIC H L 2000 TRL 4 GSTP TRL 6

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Proposed Roadmap – Schedule

Act. Prog.
Urg. Crit. Budget (k€) 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025
Ref.

AIM J: Improve and expand the European IP Cores catalogue and respective Design Methods and Tools
J01 ESA IP Cores Automated Benchmarking 45 TSS20-03ED TRL n/a TDE TRL n/a
J02 ESA IP core extensions 214 TSS20-05ED TRL 3 TDE TRL 4
J03 Universal VHDL Verification Methodology extension 350 T701-608ED TRL 2 TDE TRL 4
J04 Hardware/Software co-design: design flow demonstration 400 T701-602ED TRL 2 TDE TRL 3
J05 Evaluation of ESA IP Cores with modern verification tool environments 24 TSS21-03ED TRL n/a TDE TRL n/a
J06 Low-Power High-Resolution Rad-Hard Analog-to-Digital Converters for Next Generation Space Imag 60 NPI 553-2017 TRL 2 OEP TRL 4
J07 Independent validation and optimisation of recently developed IP Cores: [3] extend Blue Pearl static 25 Maint E21-21-03 TRL n/a OEP TRL n/a
J08 Independent validation and optimisation of recently developed IP Cores: [1] Validate SpW-DMA wr 25 Maint E21-21-01 TRL n/a OEP TRL n/a
J09 SpW Interface IP for BRAVE FPGAs 40 Maint E21-05 TRL 2 OEP TRL 3
J10 Upgrade of SHyLoC Ip Core to Issue 2 of the CCSDS 123.0-B-2 standard 40 Maint E21-04 TRL 2 OEP TRL 3
J11 Independent validation and optimisation of recently developed IP Cores: [2] Port an ESA IP Core to B 25 Maint E21-21-02 TRL n/a OEP TRL n/a
J12 Novel radiation hardened All-Digital Phase-Locked Loop/Clock-Data Recovery (ADPLL) 90 NPI 610-2018 TRL 2 OEP TRL 3
J13 Lossless/lossy multispectral & hyperspectral compression IP core 250 T701-701ED TRL 2 TDE TRL 3
J14 IP CORE DEVELOPMENT FOR CCSDS-BASED OPTICAL PAYLOAD DATA TRANSMITTER 400 3C.021 TRL 2 ARTES TRL 3
J15 FPGA implementation of artificial neural networks on-board satellites H L 500 TRL 2 TDE TRL 4
J16 Improving connectivity of ESA IP Cores: implementation of AMBA AHB to AXI bridge and Direct Mem H M 400 TRL 3 TDE TRL 5

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Proposed Roadmap – Schedule
AIM J

J17 New IP Cores for Space applications H L 400 J05 -> TRL 2 TDE TRL 4
J18 Validation Test Functional Coverage Methodology H L 200 TRL n/a OEP TRL n/a
J19 Supervisor for COTS FPGAs H M 500 TRL 3 TDE TRL 5
J20 Hardware/Software co-design: implementation of new IP models (RISC-V ISA) H M 300 J04 -> TRL 2 TDE TRL 4
J21 Model Based Design for Microelectronics, including "autocoding" H L 300 TRL 2 TDE TRL 4
J22 Radiation-aware tool to optimize designs for COTS FPGA, intially addressed to KU060 FPGA H M 150 TRL 2 TDE TRL 5
J23 Fault Injection system for KU060 FPGAs H L 100 TRL 3 TDE TRL 5
J24 Conformance Test Suits for key space data communication IP Cores H M 250 TRL n/a GSTP TRL n/a
J25 Identification of Analog Hardware Description Language for board level CAD tool use H M 150 TRL n/a OEP TRL n/a
J26 High throughput bus interconect IP H M 100 TRL n/a OEP TRL n/a
J27 Space foundry process Radiation TCAD customisation H M 250 TRL n/a GSTP TRL n/a
J28 DSP accelerator IPs for RISC-V and other microprocessors H M 500 T701-702ED -> TRL 1 GSTP TRL 3
J29 Space Rated Microcontroller Softcore - Product development 480 GT17-121ED TRL 4 GSTP TRL 6
J30 Radiation characterization and functional verification of COTS components for space applications. (R 1200 GT17-008QE TRL 3 GSTP TRL 5
J31 ADHA IP Cores H M 450 TRL 3 TDE TRL 5
J32 Development of TSN IP for End-system and Switch for Rad-Hard FPGAs H M 600 T701-704ED TRL 4 GSTP TRL 6
J33 Minimal Time-Triggered Ethernet End-System standard IP core implementation H M 400 TRL 3 GSTP TRL 5

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Proposed Roadmap – Overview
Breakdown per programme Appr. (k€) Prop. (k€)
TDE 15,208 14,150
GSTP 29,892 54,150
ARTES 17,551 15,300
CTP 0 0
ETP 0 0
E3P 0 0
NAVISP 0 0
EGEP 0 0
EOEP 1,000 0
FLPP 0 0
Other ESA Programmes (OEP) 3,370 13,970
TOTAL ESA Programmes 67,021 97,570
Institutional National Programmes (INP) 33,388 1,500
Commercial Programmes (CP) 0 0
Other European Institution Programmes (OEIP) 31,760 5,000
Other National Programmes (ONP) 0 0
TOTAL NON-ESA Programmes 65,148 6,500
Programme Not Identified (PNI) 0 0
Other 0 0

TOTAL 132,169 104,070

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Proposed Roadmap – Overview

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Proposed Roadmap – Overview

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Proposed Roadmap – Overview

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Proposed Roadmap – Overview

ESA UNCLASSIFIED - For ESA Official Use Only ESA | 19/11/2021 | Slide 74
Conclusions (1)

The On-Board Computers, Data Handling Systems & Microelectronics (OBCDHSM) dossier covers a large field
potentially too large for one dossier.

In 2020 large efforts were spent vis-à-vis programs and industrial partners to identify application needs.

This information has, as far as possible, been translated into OBCDHSM Technical Dossier and was utilised to
develop the ensuing draft roadmap.

Efforts were also spent coordinating with the Avionics Dossier.

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Conclusions (2)
To meet ESA technology targets, program needs and support a strong European Space Industry the following
high-level technologies are addressed:

• Advanced Data Handling Architecture plus associated modules – applicable to a large number of mission
applications providing standardization, reduced development time, resources and cost.
• End-to-end high speed on-board communication solutions (protocols and HW)
• Automation, security, On-board processing, etc. (including AI for various applications)
• Ultra Deep Submicron Technology foundation for future European devices
• Expansion of European space critical components like BRAVE FPGAs, microprocessors and ASSPs
• Continuous development of multi-core / multi-die processing solutions and higher and heterogeneous
integration levels of digital and analogue

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