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VLSI Assignment

The document contains a VLSI assignment with code samples and questions related to data types, memory assignments, and testing methodologies in System Verilog. It includes specific questions about the range of values for variables, hexadecimal and decimal conversions, and evaluates various memory assignments. Additionally, it discusses the advantages and disadvantages of block-level and system-level testing, directed testing, and constrained random testing in System Verilog.

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Jack Stephen.G
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3 views

VLSI Assignment

The document contains a VLSI assignment with code samples and questions related to data types, memory assignments, and testing methodologies in System Verilog. It includes specific questions about the range of values for variables, hexadecimal and decimal conversions, and evaluates various memory assignments. Additionally, it discusses the advantages and disadvantages of block-level and system-level testing, directed testing, and constrained random testing in System Verilog.

Uploaded by

Jack Stephen.G
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VLSI Assignment-1

1. Given the following code sample:


byte my_byte;
integer my_integer;
int my_int;
bit [15:0] my_bit;
shortint my_short_int1;
shortint my_short_int2;
my_integer = 32’b 0000 1111 xxxx zzzz;
my_int = my_integer;
my_bit = 16’h 8000;
my_short_int1 = my_bit;
my_short_int2 = my_short_int1-1;

a. What is the range of values my_byte can take?


b. What is the value of my_int in Hexadecimal?
c. What is the value of my_bit in Decimal?
d. What is the value of my_short_int1 in Decimal?
e. What is the value of my_short_int2 in Decimal?

2. Given the following code sample:


bit [7:0] my_mem[3];
logic [3:0] my_logicmem[4];
logic [3:0] my_logic;
my_mem = ‘{default: 8h’ 45};
my_logicmem = ‘{0,1,2,3};
my_logic = 4’h F;

Evaluate the following statements in order and give the result for each assignment:
a. my_mem [2] = my_logicmem [4];
b. my_logic = my_logicmem [4];
c. my_logicmem [3] = my_mem [3];
d. my_mem [3] = my_logic;
e. my_logic = my_logicmem[1];
f. my_logic = my_mem[1];
g. my_logic = my_logicmem[my_logicmem[4]];

3. What are the Advantages and Disadvantages to Testing at the Block-level? Why?
4. What are the Advantages and Disadvantages to Testing at the System-level? Why?
5. Give the Advantages and Disadvantages of Directed-Testing in System Verilog(SV)?
6. List out and also Elaborate the Advantages and Disadvantages of Constrained
Random Testing(CRT)?
7. Explain in-detail the Data-types in System Verilog?
8. Explain the CRT(Constrained Random Testing) in-detail with-respect-to SV?

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