LECTURE NOTES

on
OPERATING SYSTEM
(ICS-401)

2023– 2024

B. Tech IIIrd Sem e s t e r

Mr. Deepanshu Singh Yadav, Assistant Profes so r
Ms. Diksha Sharma, Assistant Profes so r

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
 Sitapur Road, Lucknow
Uttar Pradesh
India
Pin Code :226021

INSTITUTE OF ENGINEERING
&TECHNOLOGY

Department of Computer Science and Engineering

REFERENCES :
1. Silberschatz, Galvin and Gagne, “Operating Systems Concepts”, Wiley
2. Harvey M Dietel, “ An Introduction to Operating System”, Pearson Education
3. William Stallings, “Operating Systems: Internals and Design Principles ”, 6th Edition, Pearson
Education
4. D M Dhamdhere, “Operating Systems : A Concept based Approach”, 2nd Edition
5. Sibsankar Halder and Alex A Aravind, “Operating Systems”, Pearson Education
6. Rajiv Chopra, “ Operating System a Practical approach”, S.Chand
7. I.A.Dhotre, “Operating System”,Technical Publications.
8. codeforwin.org/
9. https://www.prepbytes.com
10. Unstop.com

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
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individual knowledge. The information provided in this e-content is developed from authentic references, to
the best of my knowledge.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
Introduction:
Paging and Segmentation both are techniques of memory management in the operating system. Now, In order to
understand the difference between paging and segmentation, first, it is necessary to know the basics of memory
management. So let’s quickly discuss it.
Memory is the storage space in our computer systems. It is divided into a large number of small parts called cells or
bytes. Each byte has its own address. In our computers, we have 2 types of memory: Secondary memory and Primary
memory aka RAM. As we all know, all of our programs get stored in secondary memory, and in order to execute
them, we need a CPU (Central Processing Unit). Now, the CPU is not directly connected to secondary memory
because of the speed constraints. The CPU is connected to primary memory. That is why to run any program it must
be present in Primary memory (or RAM) But the processing speed of the CPU is very fast. And, to use the CPU
efficiently, it is necessary to store more and more programs in the RAM. As we all know, the size of RAM is quite
less in our systems since it’s an expensive memory. Due to the smaller size, it’s very important to manage the memory
efficiently.
What do we mean by managing memory?
When programs come into the RAM, they must be allocated memory in such a way that more and more programs
could get stored. In memory management, we make partitions in the memory such that we can fit more and more
programs into it and we also make partitions in the program to store it in the memory. Here memory refers to the main
memory i,e, RAM.

We have two types of memory management techniques:

1. Contiguous Memory Allocation
2. Non-contiguous Memory Allocation
In Contiguous memory allocation, all the partitions of a program are allocated contiguous memory in the main
memory. In contiguous allocation, we have two types of partitioning: Fixed partitioning and Variable partitioning. As
the name suggests, In fixed partitioning, we divide the memory into fixed-size slots. Each partition will be of the same
size. On the other hand, In variable size partitioning, the partition size will depend on the size of the program and it
will be allocated dynamically. Whenever the program comes into the RAM only then we will allocate the space to
them. If the program is of 5 MB, then a partition of 5 MB in the memory will be allocated. Irrespective of the type of
partitioning, the whole program will always be allocated contiguous memory only. Spanning of a program is not
allowed here.
In Non-contiguous memory allocation, it is not necessary to store all the partitions of a program contiguously. We
can store different partitions of a program at different memory allocations. Paging and Segmentation both are non-
contiguous memory management techniques.
What is Paging?
In the Paging memory management technique, we divide the program into fixed equally sized pages and we divide the
primary memory(RAM) into fixed equally sized frames. The size of each page will always be equal to the size of each
frame. And due to this, one page of a process will fit exactly in the frame. When a program arrives in the system to be
executed by the CPU, its size is examined which is expressed in the number of pages. Each page of the process needs
one frame to get stored. Thus, if the program is divided into n pages, then at least n free frames must be available in
the main memory. If n frames are available, they are allocated to the pages of this new arriving process. The first page
of the program is loaded into one of the allocated frames, and the frame number is added to the page table for this
process. The next page is loaded into another frame, its frame number is added to the page table, and so on.
Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW
Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
In contiguous memory allocation, we had the problem of External fragmentation. Now external fragmentation is a
condition when we have enough space in the memory to fulfill a request but that free space is scattered here and there,
i.e, it is not contiguous. Free space is fragmented into a large number of small holes. Since Paging is a non-contiguous
memory allocation technique, it solves the problem of external fragmentation. But along with external fragmentation,
it also solves the overhead of compaction. Compaction: combining all the empty spaces together using reallocation.

Advantages of Paging:
 Paging avoids external fragmentation and compaction.
 In paging, allocation of memory is easy and cheap.
 In this technique, swapping processes is easy between equal-sized pages and frames.
 Paging also solves the problem of fitting memory chunks of varying sizes onto the backing store.
 The page which is just swapped out is least likely to be used again.
 It allows demand paging and prepaging.
Disadvantages of Paging:
Frames are allocated as units and because of this, they may have some internal fragmentation. If the memory
requirements of a program do not happen to coincide with page boundaries, the last frame allocated may not be
completely filled and will have some free space.
For e.g, Suppose the page/frame size is 8MB and the process is 14 MB. In this case, 2 frames will be allocated but the
last frame will have 2 MB of free space.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
In the worst case, a process would need n pages plus 1 byte extra. It would be allocated n + 1 frames, resulting in the
internal fragmentation of almost an entire frame.
For e.g, Consider a process of 9MB where the page size is 8MB. In this case, it will be allocated 2 frames. The second
frame will have only 1 byte occupied.

Page tables and frame tables are used to keep the details of free and allocated space. They consume additional memory
to get stored. Every process will have its own page table in the memory.

Translation of logical Address into physical Address:

As a CPU always generates a logical address and we need a physical address for accessing the main memory. This
mapping is done by the MMU (memory management Unit) with the help of the page table . Lets first understand
some of the basic terms then we will see how this translation is done.
Logical Address: The logical address consists of two parts page number and page offset.
1. Page Number: It tells the exact page of the process which the CPU wants to access.
2. Page Offset: It tells the exact word on that page which the CPU wants to read.
Logical Address = Page Number + Page Offset
Physical Address: The physical address consists of two parts frame number and page offset.
1. Frame Number: It tells the exact frame where the page is stored in physical memory.
2. Page Offset: It tells the exact word on that page which the CPU wants to read. It requires no translation as the
page size is the same as the frame size so the place of the word which CPU wants access will not change.
Physical Address = Frame Number + Page Offset
Page table: A page stable contains the frame number corresponding to the page number of some specific process.
So, each process will have its own page table. A register called Page Table Base Register(PTBR) which holds the
base value of the page table.
Now, let's see how the translation is done.
How is the translation done?
The CPU generates the logical address which contains the page number and the page offset . The PTBR register
Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW
Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
contains the address of the page table. Now, the page table helps in determining the frame number corresponding
to the page number. Now, with the help of frame number and the page offset the physical address is determined and
the page is accessed in the main memory.

In paging, we were blindly diving the process into pages of fixed sizes but in segmentation, we divide the process
into modules for better visualization of the process. Here each segment or module consists of the same type of
functions. For example, the main function is included in one segment, library function is kept in other segments,
and so on. As the size of segments may vary, so memory is divided into variable size parts.
Translation of logical Address into physical Address
As a CPU always generates a logical address and we need a physical address for accessing the main memory. This
mapping is done by the MMU(memory management Unit) with the help of the segment table .
Lets first understand some of the basic terms then we will see how this translation is done.
Logical Address: The logical address consists of two parts segment number and page offset.
1. Segment Number: It tells the specific segment of the process from which the CPU wants to read the data.
2. Segment Offset: It tells the exact word in that segment which the CPU wants to read.
Logical Address = Segment Number + Segment Offset
Physical Address: The physical address is obtained by adding the base address of the segment to the segment
offset.
Segment table: A segment table stores the base address of each segment in the main memory. It has two parts
i.e. Base and Limit . Here, base indicates the base address or starting address of the segment in the main
memory. Limit tells the size of that segment. A register called Segment Table Base Register(STBR) which holds
the base value of the segment table. The segment table is also stored in the main memory itself.
How is the translation done?
The CPU generates the logical address which contains the segment number and the segment offset . STBR register
contains the address of the segment table. Now, the segment table helps in determining the base address of the
segment corresponding to the page number. Now, the segment offset is compared with the limit corresponding to
the Base. If the segment offset is greater than the limit then it is an invalid address. This is because the CPU is
trying to access a word in the segment and this value is greater than the size of the segment itself which is not
possible. If the segment offset is less than or equal to the limit then only the request is accepted. The physical
address is generated by adding the base address of the segment to the segment offset.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
Explain with Example
P1 requires 3 MB of space to load in the main memory. We have two holes of 2MB and 1MB, respectively, available
at different locations in the main memory. And still, Process 1 can load successfully. It is because of non-contiguous
memory allocation.

Concept of Paging
In which processes are organized in equal size blocks called pages, and the main memory is organized in equal-sized
blocks called frames.

Pages in secondary memory and main memory frames are the same size as the CPU and do not generate absolute
addresses. But it generates the logical address.
However, the actual data required for the CPU is present in the main memory. A physical address is required to access
actual data in the main memory. For this purpose, the system uses the MMU. MMU further uses the Page table. Every
process has its own page table.
Entries of page table of each process = total no of pages of that process
Paging is a technique in which the main memory is organized in blocks of equal size. These blocks are also known as
pages. In this technique, the address of occupied pages of physical memory is stored in a table known as a page table.
Through Paging, OS can get the physical memory location without specifying the lengthy memory address in the
instruction. In this technique, the virtual address is used to map the physical address of the data. The length of the
virtual address is specified in the instruction and is smaller than the physical address of the data. It consists of two
different numbers; the first is the page’s address, known as a virtual page in the page table. The second number is the
offset value of the actual data on the page. Let’s explain with a diagram.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
Let’s Explain with an example.

In an operating system, memory management refers to dividing the memory among the various processes. The
fundamental goal of memory management is to make optimal use of memory by minimizing internal and external
fragmentation. One such algorithm for memory management techniques is paging.
Operating systems utilize paging as a memory management strategy to manage memory and assign memory to
programs, so it eliminates the requirement for contiguous physical memory allocation. Paging is the procedure of
transferring operations in the form of pages from the secondary storage into the primary memory. Memory is split
into fixed-size units called pages in paging, and processes are given memory allotments based on these pages. Paging
is a logical idea that is utilized to provide quicker access to data.

What is Paging?
Paging is a static memory allocation method that allows a process's physical address space to be of a non-contiguous
type. It's a memory management scheme or storage mechanism that lets the operating system fetch processes from
secondary memory in the form of pages and place them in the main memory. The paging hardware and operating
system are integrated to implement the paging process.
A page is a logical memory unit in a program. Logical memory is organized into equal-sized pages or equal-sized
blocks. A frame is a type of physical memory unit. In the concept of paging, physical memory (main memory) is

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
organized into frames, which are equally sized memory blocks. The memory size of a new process is determined
when it arrives. If a process has n pages in local memory, there must be n frames available in the system.
To get maximum utilization of the main memory and minimize external fragmentation, the size of a frame should be
the same as the size of a page. Paging is mostly used to store non-contiguous portions of a single process. To make
the paging method easier, the operating system decides:
The program's total page count.
Finds a sufficient number of empty page frames to assist.
All pages must be contiguous to be loaded into memory.
Characteristics of Paging in OS
Paging in OS has five key characteristics:
External fragmentation is not present.
By procedure, any frame may be employed.
Only on the last page of a process, internal fragmentation may occur.
A process's physical memory is no longer contiguous.
A process' logical memory is still contiguous.
Example of Paging
Here is an example. Let’s say the main memory size is 64B and the frame size is 4B then, the number of frames
would be 64/4 = 16. There are 4 processes. The size of each process is 16B and the page size is also 4B then, the
number of pages in each process = 16/4 = 4. These pages may be stored in the main memory frames in a non-
contiguous form, depending on their availability.

Paging in OS: Page Table

If we speak of paging in the operating system, the logical and physical memory addresses are separated. As a result,
an address translation mechanism is required to convert the logical address into a physical address. The physical
address is the actual address of the frame where each page will be placed, whereas the logical address space is the
address created by the CPU for each page.
The CPU generates a logical address that is made up of two parts-
Page Number (p): Determines which page of the process the CPU wishes to read the data from.
Page Offset (d): Defines which word on the page the CPU wants to read.
When the CPU generates a page number, the page table displays the relevant frame number (frame base address) for
each page in the main memory.
The required physical address is formed by multiplying the frame number by the page offset. The frame number
identifies the frame in which the required page is stored. Page Offset provides the precise word from that page that
must be read.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
Every new process creates a separate page table (stored in physical memory). A page table entry contains a variety of
page-related information. The information contained in the page table item differs from one operating system to
another. PTE has the following information:
Frame Number: It is the most crucial piece of information in a page table entry. The frame number identifies the
memory frames in the paging in which the page is stored. The size of the frame number is determined by the number
of frames in the main memory.
The number of bits for frame = Size of Physical memory/Frame size.
Present/Absent Bit: This is also referred to as the valid/invalid bit. This bit indicates whether or not the page is in
the main memory space. This bit is set to 0 if the page is not available in the main memory; otherwise, it is set to 1.
Protection bit: This bit is also known as the 'Read / Write bit.' This bit is about page security. It determines whether
or not the user has permission to read and write to the page. This bit is set to 0 if only read operations are allowed
and no writing operations are allowed. If both read and write operations are permitted, this bit will be set to 1.
Reference bit: The reference bit indicates whether or not the page was referred to in the previous clock cycle. If the
page has recently been referenced, this bit is set to 1, otherwise, it is set to 0.
Caching Enabled/Disabled: The reference bit indicates whether or not the page was referred to in the previous
clock cycle. If the page has recently been referenced, this bit is set to 1, otherwise, it is set to 0.
Dirty bit: This bit is also known as the "Modified bit." This bit indicates whether or not the page has been changed.
This bit is set to 1 if the page has been updated; otherwise, it is set to 0.

Page Table Types

Following are the two most used Page Table types:
1. Single Level Page Table
Only single-page tables are used in this procedure. Page tables are made up of a linear array of page table entries
(PTEs). Each PTE holds information on the page, such as its physical page number and status bits, such as whether
the page is valid or not, as well as any other bits.
Every memory reference will have its address translated. The size of the page table might vary greatly depending on
the page size. The loading of larger page tables takes longer.
Drawback: The main downside of this strategy is that managing these big page tables as a single entity is
problematic. Because of the additional memory reference for the page table, mapping from virtual to physical
address is delayed.
2. Multi-Level Page Table
A multilevel page table is split into two or more levels. Page tables are stored in multi-level tables, which have a
tree-like structure.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
The level-0 page table's entries are pointers to a level-1 page table.
The level-1 page table's entries are pointers to a level-2 page table.
Actual page information will be stored in the entries of the final level page table.
When paging is implemented on the page table in multilevel paging, the base address of the first-level page entry
will be the base address of the second-level page table entry, and the second-level page table entry will be the base
address of the third-level page table entry, and so on.
The frame number of actual pages will be displayed in the final level page table item. In multilevel paging,
regardless of the level of paging, all the PT will be stored in the main memory and all PT entries carry simply the
frame number.
Drawback: All of the page tables are kept in memory. As a result, getting the physical address of the page frame
needs more than one memory access, one for each level required. Extra memory references to access address
translation can slow down a program in memory by a factor of two or more, which is a considerable drawback.

Paging with TLB (Translation Look-aside Buffer)

To access a byte in paging, the first-page table item must be visited, followed by the bytes.
As a result, two memory accesses will be required. Memory access is slowed by a factor of two as a result. In most
cases, this delay would be intolerable.
The above issue can be remedied by employing a fast-searching hardware cache called a translation look-aside
buffer. The TLB is a type of associative fast memory.
Every table entry is broken into two parts: one is the key, and the other is the value. When an object is introduced to
the associative memory, it is compared to all keys at the same time. If there is a match, the value field for that match
is returned.
Despite the high cost of the technology, the search mechanism that is enabled in this way is extremely quick. TLB
typically stores a limited amount of entries, usually between 64 and 1024.

Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW

Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW
Mr. Deepanshu Singh Yadav , Assistant Professor ,IET,LUCKNOW
Ms.Diksha Sharma, Assistant Professor ,IET,LUCKNOW