RK3128 Technical Reference Manual Rev 1.

Chapter 26 USB OTG 2.0

26.1 Overview

USB OTG 2.0 is a Dual-Role Device controller, which supports both device and
host functions and is fully compliant with OTG Supplement to USB2.0
specification, and support high-speed (480Mbps), full-speed (12Mbps),
low-speed (1.5Mbps) transfer.
USB OTG 2.0 is optimized for portable electronic devices, point-to-point
applications (no hub, direct connection to device) and multi-point applications
to devices. USB OTG 2.0 interface supports both device and host functions and
is fully compliant with OTG Supplement to USB2.0 specification, and support
high-speed (480Mbps), full-speed (12Mbps), low-speed (1.5Mbps) transfer. It
is optimized for portable electronic device, point-to-point applications (no hub,
direct connection to device) and multi-point applications to devices.
26.1.1 Features

 Compliant with the OTG Supplement to the USB2.0 Specification

 Operates in High-Speed and Full-Speed mode
 Support 9 channels in host mode
 9 Device mode endpoints in addition to control endpoint 0, 4 in, 3 out and
2 IN/OUT
 Built-in one 1024x35 bits FIFO
 Internal DMA with scatter/gather function
 Supports packet-based, dynamic FIFO memory allocation for endpoints for
flexible, efficient use of RAM
 Support dynamic FIFO sizing

26.2 Block Diagram

USB OTG
USB BUS USB OTG
UTMI 2.0 AHB
2.0 PHY
CONTROLLER

Fig. 26-1 USB OTG 2.0 Architecture

Fig.26-1 shows the architecture of USB OTG 2.0. It is broken up into two
separate units: USB OTG 2.0 controller and USB OTG 2.0 PHY. The two units are
interconnected with UTMI interface.
26.2.1 USB OTG 2.0 Controller Function

The USB OTG 2.0 Controller controls SIE (Serial Interface Engine) logic, the
endpoint logic, the channel logic and the internal DMA logic.
The SIE logic contains the USB PID and address recognition logic, and other
sequencing and state machine logic to handle USB packets and transactions.

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Generally the SIE Logic is required for any USB implementation while the
number and types of endpoints will vary as function of application and
performance requirements.
The endpoint logic contains the endpoint specific logic: endpoint number
recognition, FIFOs and FIFO control, etc.
The channel Logic contains the channel tasks schedule, FIFOs and FIFO control,
etc.
The internal DMA logic controls data transaction between system memory and
USB FIFOs.
26.2.2 USB OTG 2.0 PHY Function

The USB OTG 2.0 PHY handles the low level USB protocol and signaling. This
includes features such as; data serialization and deserialization, bit stuffing and
clock recovery and synchronization. The primary focus of this block is to shift
the clock domain of the data from the USB 2.0 rate to the frequency of UTMI
clock which is 30MHz.
26.2.3 UTMI Interface

 Transmit
Transmit must be asserted to enable any transmissions.
The USB OTG2.0 CONTROLLER asserts TXValid to begin a transmission and
negates TXValid to end a transmission. After the USB OTG2.0 CONTROLLER
asserts TXValid it can assume that the transmission has started when it detects
TXReady asserted.
The USB OTG2.0 CONTROLLER assumes that the USB OTG2.0 PHY has
consumed a data byte if TXReady and TXValid are asserted.
The USB OTG2.0 CONTROLLER must have valid packet information (PID)
asserted on the Data In bus coincident with the assertion of TXValid. Depending
on the USB OTG2.0 PHY implementation, TXReady may be asserted by the
Transmit State Machine as soon as one CLK after the assertion of TXValid.
TXValid and TXReady are sampled on the rising edge of CLK.
The Transmit State Machine does NOT automatically generate Packet ID's (PIDs)
or CRC. When transmitting, the USB OTG2.0 CONTROLLER is always expected
to present a PID as the first byte of the data stream and if appropriate, CRC as
the last bytes of the data stream.
The USB OTG2.0 CONTROLLER must use LineState to verify a Bus Idle condition
before asserting TXValid in the TX Wait state.
The state of TXReady in the TX Wait and Send SYNC states is undefined. An MTU
implementation may prepare for the next transmission immediately after the
Send EOP state and assert TXReady in the TX Wait state. An MTU
implementation may also assert TXReady in the Send SYNC state. The first
assertion of TXReady is Macrocell implementation dependent. The USB OTG2.0
CONTROLLER must prepare DataIn for the first byte to be transmitted before
asserting TXValid.

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Fig. 26-2 UTMI interface – Transmit timing for a data packet

 Receive
RXActive and RXValid are sampled on the rising edge of CLK.
In the RX Wait state the receiver is always looking for SYNC.
The USB OTG 2.0 PHY asserts RXActive when SYNC is detected (Strip SYNC
state).
The USB OTG 2.0 PHY negates RXActive when an EOP is detected (Strip EOP
state).
When RxActive is asserted, RXValid will be asserted if the RX Holding Register is
full.
RXValid will be negated if the RX Holding Register was not loaded during the
previous byte time.
This will occur if 8 stuffed bits have been accumulated.
The USB OTG2.0 Controller must be ready to consume a data byte if RXActive
and RXValid are asserted (RX Data state).
In FS mode, if a bit stuff error is detected then the Receive State Machine will
negate RXActive and RXValid, and return to the RX Wait state.

Fig. 26-3 UTMI interface – Receive timing for a data packet

26.3 USB OTG2.0 Controller

Fig.26-4 shows the main components and flow of the USB OTG 2.0 controller

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system.

Fig. 26-4 USB OTG2.0 Controller Architecture

1). AHB Slave Bus Interface Unit (BIUS)
The AHB Slave interface unit converts AHB cycles to CSR write/read,
Data-FIFO read/write, and DFIFO push/pop signals.
2) Control and Status Registers (CSR)
The CSR block resides in the AHB clock domain, and contains all registers except
the Power and Clock Gating Control Register (PCGCCTL) and bits 31:29 of the
Core Interrupt register (GINTSTS).
3) Application Interface Unit (AIU)

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The application Interface Unit (AIU) consists of the following interfaces:

 AHB Master
 AHB Slave
 Packet FIFO Controller
 Control and Status registers
4). DMA Scheduler (DSCH)
This block is used only in DMA mode. It controls the transfer of data packets
between the system memory and the USB OTG 2.0 Controller for both Internal
and External DMA.
5). Packet FIFO Controller (PFC)
Several FIFOs are used in Device and Host modes to store data inside the core
before transmitting it on either the AHB or the USB. PFC connect the Data FIFO
interface to an industry-standard, single-port synchronous SRAM. Address,
write data, and control outputs are driven late by the USB OTG 2.0 Controller,
but in time to meet the SRAM setup requirements. Input read data is expected
late from the SPRAM and registered inside the core before being used.

USB OTG 2.0

Controller

Fig. 26-5 DFIFO single-port synchronous SRAM interface

6).Media Access Controller (MAC)
The Media Access Controller (MAC) module handles USB transactions, and
device, host, and OTG protocols.
7) PHY Interface Unit (PIU)
The core uses 16-bit UTMI+ Interface.
8) Wakeup and Power Controller (WPC)
When the USB is suspended or the session is not valid, the PHY is driven into
Suspend mode and the PHY clock is stopped to reduce PHY and the core power
consumption. To reduce power consumption further, the core also supports AHB
clock gating and partial power-down.
26.3.1 Host Architecture

The host uses one transmit FIFO for all non-periodic OUT transactions and one
transmit FIFO for all periodic OUT transactions. These transmit FIFOs are used
as transmit buffers to hold the data (payload of the transmit packet) to be
transmitted over USB.

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The host pipes the USB transactions through Request queues (one for periodic
and one for non-periodic). Each entry in the Request - queue holds the IN or
OUT channel number along with other information to perform a transaction on
the USB. The order in which the requests are written into the queue determines
the sequence of transactions on the USB. The host processes the periodic
Request queue first, followed by the non-periodic Request queue, at the
beginning of each (micro) frame.
The host uses one Receive-FIFO for all periodic and non-periodic transactions.
The FIFO is used as a Receive-buffer to hold the received data (payload of the
received packet) from the USB until it is transferred to the system memory. The
status of each packet received also goes into the FIFO. The status entry holds
the IN channel number along with other information, such as received byte
count and validity status, to perform a transaction on the AHB.

26.3.2 Device Architecture

The core uses Dedicated Transmit FIFO Operation. In this mode, there are
individual transmit FIFOs for each IN endpoint.
The OTG device uses a single receive FIFO to receive the data for all the OUT
endpoints. The receive FIFO holds the status of the received data packet, such
as byte count, data PID and the validity of the received data. The DMA or the
application reads the data out of the receive FIFO as it is received.

26.3.3 FIFO Mapping

 Fig.26-6 shows FIFO mapping in Host mode.

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Fig. 26-6 USB OTG 2.0 Controller host mode FIFO address mapping
Note: When the device is operating in Internal DMA mode, the last locations of the SPRAM are
used to store the DMAADDR values for each channel.

 Fig.26-7 shows FIFO mapping in Device mode.

When the device is operating in non-Descriptor Internal DMA mode, the last
locations of the SPRAM are used to store the DMAADDR values for each channel.
When the device is operating in Descriptor mode, then the last locations of the
SPRAM store the Base Descriptor address, Current Descriptor address, Current
Buffer address, and status quad let information for each endpoint direction.

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Fig. 26-7 USB OTG 2.0 Controller device mode FIFO address mapping
Note: When the device is operating in non-Scatter Gather Internal DMA mode, the last
locations of the SPRAM are used to store the DMAADDR values for each Endpoint (1 location
per endpoint). When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address, Current Buffer
address, and status quadlet information for each endpoint direction (4 locations per
Endpoint). If an Endpoint is bidirectional, then 4 locations will be used for IN, and another 4
for OUT).

26.4 USB OTG2.0 PHY

USB PHY supports dual OTG ports’ functions and is fully compliant with USB2.0
specification, and support High-speed (480Mbps), full-speed (12Mbps),
low-speed (1.5Mbps) transfer. It provides a complete on-chip transceiver
physical solution with ESD protection. A minimum number of external
components are needed, which include a 45 ohm resistor for resistance
calibration purpose. Its feature contains:
• provide dual UTMI ports
• OTG0 Support UART Bypass Function
• Fully compliant with USB specifications Rev 2.0, 1.1 HOST/Device and OTG
V1.2.
• Supports 480Mbps (HS), 12Mbps (FS) & 1.5Mbps(LS) serial data transmission
• Supports low latency hub mode with 40 bit time round trip delay
• 8 bit or 16 bit UTMI interface compliant with UTMI+ specification level 3 Rev 1.
• Loop back BIST mode supported
• Built-in I/O and ESD structure

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• On-die self-calibrated HS/FS/LS termination

• 12MHz crystal oscillator with integrated phase-locked loop (PLL) oscillator
• Manufactured in SMIC 65/55nm LL process
• Dual 3.3V / 1.2V supply

26.4.1 Block Diagram

Fig. 26-8 usb phy architecture

HS AFE
The HS AFE contains the low-level analog circuitry, and also the HS differential
data transmitter and receiver, to perform HS transmission envelope detection
and host disconnection detection. It works in HS mode only.
HS Transmit driver
The HS transmit driver is active only when transmit is asserted. In HS
transceiver enabled mode and the transmit state machine has data to send, the
XCVR selects input. Data from transmit data path will be driven onto the DP/DM
signal lines when enabled.
HS Differential Receiver

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When enabled, received HS data will be multiplexed through the receive data
path to the receive shift and hold registers. It is active only in HS mode.
transmission envelope detector (Squelch detector)
When the amplitude of the differential signal at a receiver’s inputs falls below
the squelch threshold, the envelope detector will indicate the invalid data. It
must indicate squelch when the signal drops below 100mV differential
amplitude, and also, it must indicate that the line is not in the squelch state
when the signal exceeds 150mV differential amplitude.
Disconnection envelope detector
In host mode, this envelope detector is active to detect the high speed
disconnect state on the line. Disconnection must be indicated when the
amplitude of the differential signal at the downstream facing driver’s connector
is more than 625 mV, and it must not be indicated when the signal amplitude is
less than525 mV.
FS/LS AFE
In FS or LS mode, the FS/LS AFE is active to send and receive the FS or LS data
on the USB bus. Also it supports the reset, suspend and resume detection
through the data line single ended receivers.
FS/LS Transmitter
The FS/LHS transmitter is active only when transmit is asserted. In FS or LS
transceiver enabled mode and the transmit state machine has data to send, the
XCVR selects input. Data from transmit data path will be driven onto the DP/DM
signal lines when enabled.
FS/LS Differential Receiver
When enabled, received FS or LS data will be multiplexed through the receive
data path to the receive shift and hold registers. It is active only in FS or LS
modes.
Single ended receivers
The single ended receivers are used for low-speed and full-speed signaling
detection.
Digital Core TX Path
The digital core TX path has some blocks responsible for SYNC and EOP
generation, data encoding, bit stuffing and data serialization. And meanwhile,
also a TX state machine is involved to manage the communication with the
controller.
TX Shift/Hold Register
The TX shift/Hold register module consists of an 8-bit primary shift register for
parallel/serial conversion and 8-bit hold register used to buffer the next data to
serialize. This module is responsible for reading parallel data from the parallel
application bus interface upon command and serializing for transmission over
USB.
Bit stuffer
To ensure adequate signal transitions, when sending a packet on USB, a bit
stuffer is employed by the transmitter. A ‘0’ has to be inserted after every six
consecutive ones in the data stream before the data in NRZI encoded, to force
a transition in the NRZI data stream.

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NRZI Encoder
The High speed, Full speed or low speed serial transmitted data are encoded by
The NRZI encoder. As a state transition, a ‘0’ is encoded, and as no state
transition, a ‘1’ is encoded.
Transmit state machine
The communication between the controller and the PHY in TX path is controlled
by the transmit state machine, which synchronizes the Data with the Sync and
the EOP, and also supports the LS, FS and HS Modes.
Digital Core RX Path
The digital core RX path includes blocks responsible for SYNC and EOP detection
and stripping, data decoding, bit un-stuffing and data de-serialization. Also a RX
state machine is involved to manage the communication with the controller.
FS/LS data and clock is recovered in this section.
Elasticity buffer
To compensate for differences between transmitting and receiving clocks, the
Elasticity Buffer is used to synchronize the HS extracted data with the PLL
internal clock.
Mux
The Mux block allows the data from the HS or FS/LS receivers to be routed to the
shared receive logic. The state of the Mux is determined by the Xcvr Select
input.
NRZI Decoder
The NRZI is responsible for decoding the High speed or Full speed received NRZI
encoded data. A change in level is decoded as ‘0’ and no change in level is
decoded as ‘1’.
Bit Un-stuffer
The Bit Un-stuffer not only recognizes the stuffed bits from the data stream, but
also discards them. Also it detects bit stuff error, which is interpreted as HS EOP.
RX Shift/Hold Register
This module de-serializes received data and transmits 8-bit parallel data to the
application bus interface. It consists of an 8-bit primary shit register for serial to
parallel conversion and an 8-bit hold register for buffering the last de-serialized
data byte.
Receiver state machine
The receiver state machine controls the communication between the controller
and the PHY in the RX path, strips the SYNC and the EOP from the Data and
supports the LS, FS and HS Modes.
PLL Clock Multiplier
This module is composed of the off-chip crystal and the on-chip clock multiplier.
It generates the appropriate internal clocks for the UTM and the CLK output
signal. All data transfer signals are synchronized with the CLK signal.
External Crystal
The external crystal is composed of a precise resonance frequency crystal and a
crystal oscillator. It is optional to have this crystal oscillator integrated on-chip

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or have it off-chip. This crystal/crystal oscillator provides a very precise clock of

12 MHz with deviation of ±100 ppm. The oscillator is not a part of the PHY, but
external.
Clock Multiplier
The UTM interface is described as an un-directional/bi-directional 8-bit/16-bit
parallel interface and the CLK signal is a 60/30 MHz signal. All data transfer
signals should be synchronized with the CLK signal. CLK usable signal is
internally implemented which blocks any transitions of CLK until it is usable.
Meanwhile, the clock multiplier provides another three clocks in addition to the
CLK signal. That is a480 MHz and 7.5 MHz clock signals.
Clock MUX
The Clock Multiplexer supplies both the transmitter and receiver paths with the
adequate bit clock depending on the XcvrSelect signal and to ensure smooth
clock switching. It also includes clock gating and power-down features.
Control Logic Block
This block is responsible for controlling, enabling and disabling the different
blocks in the system.
OTG Circuitry （optional）
With the OTG circuitry, the system has the capability to dynamically switch
between host and peripheral, enable dual role device behavior and
point-to-point communication. The OTG circuitry functions as VBUS generation
and detection. Both ID detection and terminations control are implemented in it.
ID Detector （optional）
To provide the ID signal that is used to indicate the state of the ID pin on the
USB mini receptacle. This pin makes it able to determine which kind of plug is
connected and to confirm if the device default state is A device or B device.
VBUS Detector and termination control
The VBUS detector is a set of comparators, functions to monitor and sense the
voltage on USB bus power line. For VBUS signaling and discharging, VBUS pull
up and pull-down resistors are also implemented.
Automatic Test Functions
• Loop-back test to address all IP components.
In loop-back test mode, all transmitted data packets are received back in an
internal loop to check IP functional integrity. There are some digital components
that cannot be tested with the scan technique due to the high-speed nature of
the digital part. To be regarded as a good idea, Loop-back allows testing full
design paths at speed. It should complement the testing suite for digital core to
achieve the highest coverage possible. According to the UTMI specification
Section 5.18, version 1.05 Page 34, the 8 bits un-directional data bus can be
implemented as 8 bits bi-directional one. This implementation will hinder the
loop-back test functionality.

26.5 UART BYPASS FUNCITON

When in UART bypass mode,UART2 is connect to USB interface; Otherwise,

UART2 use normal UART interface。

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Signal CONNECT I/O Description

BYPASSDMDATA0 uart2_sout I Data for DM0 Transmitter Digital
Bypass
BYPASSDMEN0 uoc0_con0[8] I DM0 Transmitter Digital Bypass
Enable
BYPASSSEL0 uoc0_con0[9] I Transmitter Digital Bypass mode
Enable
FSVPLUS0 uart2_sin O Single-Ended D- Indicator
The controller signal indicates the
state of the DP during normal
operation or UART data reception
OTGDISABLE0 uoc0_con0[4] I 1’b1: OTG0 disable;
1’b0: OTG0 normal mode
COMMONONN uoc0_con0[0] I Common Block Power-Down Control
This signal controls the power-down
signals in PLL blocks when the USB
PHY is in Suspend Mode.
1: PLL blocks are powered down.
0: PLL blocks remain powered
This signal is a strapping option that
must be set prior to a power-on
reset and remain static during
normal operation.

Note: USB OTG2.0 PHY support UART Bypass Function.

Fig. 26-9 UART Application

Fig. 26-10 UART Timing Sequence

To use UART and Auto resume functions:
1. Disable the OTG block by setting OTGDISABLE0 to 1’b1.
2. Disable the pull-up resistance on the D+ line by setting OPMODE0[1:0] to
2’b01.

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3. To ensure that the XO, Bias, and PLL blocks are powered down in Suspend
mode, set COMMONONN to 1’b1.
4. Place the USB PHY in Suspend mode by setting SUSPENDM0 to 1’b0.
5. Set BYPASSSEL0 to 1’b1.
6. To transmit data, controls BYPASSDMEN0, and BYPASSDMDATA0.
To receive data, monitor FSVPLUS0.

To return to normal operating mode:

1. Ensure that there is no activity on the USB.
2. Set BYPASSSEL0 to 1'b0.
3. Set SUSPENDM0 to 1’b1.Resume the USB PHY.
4. Set COMMONONN to 1’b0.
5. set OTGDISABLE0 to 1'b0.

26.6 Register Description

26.6.1 Register Summary

Reset
Name Offset Size Description
Value
USBOTG_GOTGCTL 0x0000 W 0x00000000 Control and Status Register
USBOTG_GOTGINT 0x0004 W 0x00000000 Interrupt Register
USBOTG_GAHBCFG 0x0008 W 0x00000000 AHB Configuration Register
USBOTG_GUSBCFG 0x000c W 0x00001400 USB Configuration Register
USBOTG_GRSTCTL 0x0010 W 0x80000000 Reset Register
USBOTG_GINTSTS 0x0014 W 0x00000000 Interrupt Register
USBOTG_GINTMSK 0x0018 W 0x00000000 Interrupt Mask Register
Receive Status Debug Read
USBOTG_GRXSTSR 0x001c W 0x00000000
Register
Receive Status Read and Pop
USBOTG_GRXSTSP 0x0020 W 0x00000000
Register
USBOTG_GRXFSIZ 0x0024 W 0x00000000 Receive FIFO Size Register
Non-Periodic Transmit FIFO
USBOTG_GNPTXFSIZ 0x0028 W 0x00000000
Size Register
Non-Periodic Transmit
USBOTG_GNPTXSTS 0x002c W 0x00000000
FIFO/Queue Status Register
USBOTG_GI2CCTL 0x0030 W 0x11000000 I2C Address Register
USBOTG_GPVNDCTL 0x0034 W 0x00000000 PHY Vendor Control Register
General Purpose Input /
USBOTG_GGPIO 0x0038 W 0x00000000
Output Register
USBOTG_GUID 0x003c W 0x00000000 User ID Register
USBOTG_GSNPSID 0x0040 W 0x00004f54 Core ID Register
USBOTG_GHWCFG1 0x0044 W 0x00000000 User HW Config1 Register
USBOTG_GHWCFG2 0x0048 W 0x00000000 User HW Config2 Register
USBOTG_GHWCFG3 0x004c W 0x00000000 User HW Config3 Register
USBOTG_GHWCFG4 0x0050 W 0x00000000 User HW Config4 Register

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Reset
Name Offset Size Description
Value
Core LPM Configuration
USBOTG_GLPMCFG 0x0054 W 0x00000000
Register
USBOTG_GPWRDN 0x0058 W 0x00000000 Global Power Down Register
USBOTG_GDFIFOCF Global DFIFO Software
0x005c W 0x00000000
G Configuration Register
ADP Timer, Control and
USBOTG_GADPCTL 0x0060 W 0x00000000
Status Register
Host Periodic Transmit FIFO
USBOTG_HPTXFSIZ 0x0100 W 0x00000000
Size Register
0x0104 Device Periodic Transmit
USBOTG_DIEPTXFn +4*(n- W 0x00000000 FIFO-n Size Register
1) n = 1 - 15
USBOTG_HCFG 0x0400 W 0x00000000 Host Configuration Register
USBOTG_HFIR 0x0404 W 0x00000000 Host Frame Interval Register
Host Frame Number/Frame
USBOTG_HFNUM 0x0408 W 0x0000ffff
Time Remaining Register
Host Periodic Transmit
USBOTG_HPTXSTS 0x0410 W 0x00000000
FIFO/Queue Status Register
Host All Channels Interrupt
USBOTG_HAINT 0x0414 W 0x00000000
Register
Host All Channels Interrupt
USBOTG_HAINTMSK 0x0418 W 0x00000000
Mask Register
Host Port Control and Status
USBOTG_HPRT 0x0440 W 0x00000000
Register
0x0500 Host Channel-n
USBOTG_HCCHARn +0x20 W 0x00000000 Characteristics Register
*n n = 0 - 15
0x0504 Host Channel-n Split Control
USBOTG_HCSPLTn +0x20 W 0x00000000 Register
*n n = 0 - 15
0x0508 Host Channel-n Interrupt
USBOTG_HCINTn +0x20 W 0x00000000 Register
*n n = 0 - 15
0x050c Host Channel-n Interrupt
USBOTG_HCINTMSK
+0x20 W 0x00000000 Mask Register
n
*n n = 0 - 15
0x0510 Host Channel-n Transfer Size
USBOTG_HCTSIZn +0x20 W 0x00000000 Register
*n n = 0 - 15
0x0514 Host Channel-n DMA Address
USBOTG_HCDMAn +0x20 W 0x00000000 Register
*n n = 0 - 15
0x051c Host Channel-n DMA Buffer
USBOTG_HCDMABn +0x20 W 0x00000000 Address Register
*n n = 0 - 15
USBOTG_DCFG 0x0800 W 0x08200000 Device Configuration Register
USBOTG_DCTL 0x0804 W 0x00002000 Device Control Register
USBOTG_DSTS 0x0808 W 0x00000000 Device Status Register
Device IN Endpoint common
USBOTG_DIEPMSK 0x0810 W 0x00000000
interrupt mask register

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Reset
Name Offset Size Description
Value
Device OUT Endpoint
USBOTG_DOEPMSK 0x0814 W 0x00000000 common interrupt mask
register
Device All Endpoints interrupt
USBOTG_DAINT 0x0818 W 0x00000000
register
Device All Endpoint interrupt
USBOTG_DAINTMSK 0x081c W 0x00000000
mask register
Device IN token sequence
USBOTG_DTKNQR1 0x0820 W 0x00000000
learning queue read register1
Device IN token sequence
USBOTG_DTKNQR2 0x0824 W 0x00000000
learning queue read register2
Device VBUS discharge time
USBOTG_DVBUSDIS 0x0828 W 0x00000b8f
register
USBOTG_DVBUSPUL Device VBUS Pulsing Timer
0x082c W 0x00000000
SE Register
Device Threshold Control
USBOTG_DTHRCTL 0x0830 W 0x08100020
Register
Device IN endpoint FIFO
USBOTG_DIEPEMPM
0x0834 W 0x00000000 empty interrupt mask
SK
register
Device each endpoint
USBOTG_DEACHINT 0x0838 W 0x00000000
interrupt register
USBOTG_DEACHINT Device each endpoint
0x083c W 0x00000000
MSK interrupt register mask
Device each IN endpoint -n
USBOTG_DIEPEACH 0x0840
W 0x00000000 interrupt Register
MSKn +4*n
n = 0 - 15
Device each out endpoint-n
USBOTG_DOEPEACH 0x0880
W 0x00000000 interrupt register
MSKn +4*n
n = 0 - 15
Device control IN endpoint 0
USBOTG_DIEPCTL0 0x0900 W 0x00008000
control register
0x0908 Device Endpoint-n Interrupt
USBOTG_DIEPINTn +0x20 W 0x00000000 Register
*n n = 0 - 15
0x0910 Device endpoint n transfer
USBOTG_DIEPTSIZn +0x20 W 0x00000000 size register
*n n = 0 - 15
0x0914 Device endpoint-n DMA
USBOTG_DIEPDMAn +0x20 W 0x00000000 address register
*n n = 0 - 15
0x0918 Device IN endpoint transmit
USBOTG_DTXFSTSn +0x20 W 0x00000000 FIFO status register
*n n = 0 - 15
USBOTG_DIEPDMAB Device endpoint-n DMA buffer
0x091c W 0x00000000
n address register
0x0920 Device endpoint-n control
USBOTG_DIEPCTLn +0x20 W 0x00000000 register
*(n-1) n = 1 - 15
Device control OUT endpoint
USBOTG_DOEPCTL0 0x0b00 W 0x00000000
0 control register

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Reset
Name Offset Size Description
Value
0x0b08 Device endpoint-n control
USBOTG_DOEPINTn +0x20 W
0x00000000 register
*n n = 0 - 15
0x0b10 Device endpoint n transfer
USBOTG_DOEPTSIZn +0x20
W 0x00000000 size register
*n n = 0 - 15
0x0b14 Device Endpoint-n DMA
USBOTG_DOEPDMAn +0x20
W 0x00000000 Address Register
*n n = 0 - 15
0x0b1c Device endpoint-n DMA buffer
USBOTG_DOEPDMAB
+0x20
W 0x00000000 address register
n
*n n = 0 - 15
0x0b20 Device endpoint-n control
USBOTG_DOEPCTLn +0x20
W 0x00000000 register
*(n-1) n = 1 - 15
Power and clock gating
USBOTG_PCGCR 0x0b24 W 0x200b8000
control register
Notes: Size : B - Byte (8 bits) access, HW - Half WORD (16 bits) access, W
-WORD (32 bits) access

26.6.2 Detail Register Description

USBOTG_GOTGCTL
Address: Operational Base + offset (0x0000)
Control and Status Register
Bit Attr Reset Value Description
31:28 RO 0x0 reserved
ChirpEn
Chirp on enable
This bit when programmed to 1'b1 results in
the core asserting chirp_on before sending an
27 RW 0x0
actual Chirp "K" signal on USB. This bit is
present only if OTG_BC_SUPPORT = 1. If
OTG_BC_SUPPORT != 1, this bit is a reserved
bit.
MultValidBc
Multi Valued ID pin
Battery Charger ACA inputs in the following
order:
Bit 26 - rid_float.
Bit 25 - rid_gnd
26:22 RO 0x00
Bit 24 - rid_a
Bit 23 - rid_b
Bit 22 - rid_c
These bits are present only if
OTG_BC_SUPPORT = 1. Otherwise, these bits
are reserved and will read 5'h0.
21 RO 0x0 reserved

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Bit Attr Reset Value Description

OTGVer
OTG version
Indicates the OTG revision.
1'b0: OTG Version 1.3. In this version the core
20 RW 0x0
supports Data line pulsing and VBus pulsing
for SRP.
1'b1: OTG Version 2.0. In this version the core
supports only Data line pulsing for SRP.
BSesVld
B-session valid
Indicates the Device mode transceiver status.
1'b0: B-session is not valid.
1'b1: B-session is valid.
In OTG mode, you can use this bit to
19 RO 0x0
determine if the device is connected or
disconnected. Note: If you do not enabled
OTG features (such as SRP and HNP), the read
reset value will be 1.The vbus assigns the
values internally for non-SRP or non-HNP
configurations.
ASesVld
A-session valid
Indicates the Host mode transceiver status.
1'b0: A-session is not valid
1'b1: A-session is valid
18 RO 0x0
Note: If you do not enabled OTG features
(such as SRP and HNP), the read reset value
will be 1.The vbus assigns the values
internally for non-SRP or non-HNP
configurations.
DbnTime
Long/short debounce time
Indicates the debounce time of a detected
connection.
17 RO 0x0
1'b0: Long debounce time, used for physical
connections (100 ms + 2.5 us)
1'b1: Short debounce time, used for soft
connections (2.5 us)
ConIDSts
Connector ID Status
Indicates the connector ID status on a connect
16 RO 0x0
event.
1'b0: The core is in A-Device mode
1'b1: The core is in B-Device mode
15:12 RO 0x0 reserved
DevHNPEn
Device HNP Enable
The application sets this bit when it
successfully receives a SetFeature.
11 RW 0x0
SetHNPEnable command from the connected
USB host.
1'b0: HNP is not enabled in the application
1'b1: HNP is enabled in the application

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Bit Attr Reset Value Description

HstSetHNPEn
Host set HNP enable
The application sets this bit when it has
successfully enabled HNP (using the
10 RW 0x0
SetFeature.SetHNPEnable command) on the
connected device.
1'b0: Host Set HNP is not enabled
1'b1: Host Set HNP is enabled
HNPReq
HNP request
The application sets this bit to initiate an HNP
request to the connected USB host. The
application can clear this bit by writing a 0
when the Host Negotiation Success Status
9 RW 0x0
Change bit in the OTG Interrupt register
(GOTGINT.HstNegSucStsChng) is set. The
core clears this bit when the
HstNegSucStsChng bit is cleared.
1'b0: No HNP request
1'b1: HNP request
HstNegScs
Host Negotiation Success
The core sets this bit when host negotiation is
successful. The core clears this bit when the
8 RO 0x0
HNP Request (HNPReq) bit in this register is
set.
1'b0: Host negotiation failure
1'b1: Host negotiation success
7:2 RO 0x0 reserved
SesReq
Session Request
The application sets this bit to initiate a
session request on the USB. The application
can clear this bit by writing a 0 when the Host
Negotiation Success Status Change bit in the
OTG Interrupt register
(GOTGINT.HstNegSucStsChng) is set. The
core clears this bit when the
HstNegSucStsChng bit is cleared. If you use
1 RW 0x0
the USB 1.1 Full-Speed Serial Transceiver
interface to initiate the session request, the
application must wait until the VBUS
discharges to 0.2 V, after the B-Session Valid
bit in this register (GOTGCTL.BSesVld) is
cleared. This discharge time varies between
different PHYs and can be obtained from the
PHY vendor.
1'b0: No session request
1'b1: Session request

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Bit Attr Reset Value Description

SesReqScs
Session Request Success
The core sets this bit when a session request
0 RO 0x0
initiation is successful.
1'b0: Session request failure
1'b1: Session request success

USBOTG_GOTGINT
Address: Operational Base + offset (0x0004)
Interrupt Register
Bit Attr Reset Value Description
31:21 RO 0x0 reserved
MultiValueChg
Multi-Valued input changed
This bit when set indicates that there is a
20 W1C 0x0 change in the value of at least one ACA pin
value. This bit is present only if
OTG_BC_SUPPORT = 1, otherwise it is
reserved.
DbnceDone
Debounce Done
The core sets this bit when the debounce is
completed after the device connection. The
application can start driving USB reset after
19 W1C 0x0
seeing this interrupt. This bit is only valid
when the HNP Capable or SRP Capable bit is
set in the Core USB Configuration register
(GUSBCFG.HNPCap or GUSBCFG.SRPCap,
respectively).
ADevTOUTChg
A-Device Timeout Change
18 W1C 0x0 The core sets this bit to indicate that the
A-device has timed out while waiting for the
B-device to connect.
HstNegDet
Host Negotiation Detected
17 W1C 0x0
The core sets this bit when it detects a host
negotiation request on the USB
16:10 RO 0x0 reserved
HstNegSucStsChng
Host Negotiation Success Status Change
The core sets this bit on the success or failure
of a USB host negotiation request. The
9 W1C 0x0
application must read the Host Negotiation
Success bit of the OTG Control and Status
register (GOTGCTL.HstNegScs) to check for
success or failure

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Bit Attr Reset Value Description

SesReqSucStsChng
Session Request Success Status Change
The core sets this bit on the success or failure
of a session request.The application must read
8 W1C 0x0
the Session Request Success bit in the OTG
Control and Status register
(GOTGCTL.SesReqScs) to check for success or
failure.
7:3 RO 0x0 reserved
SesEndDet
Session End Detected
2 W1C 0x0
The core sets this bit when the utmisrp_bvalid
signal is deasserted
1:0 RO 0x0 reserved

USBOTG_GAHBCFG
Address: Operational Base + offset (0x0008)
AHB Configuration Register
Bit Attr Reset Value Description
31:23 RO 0x0 reserved
NotiAllDmaWrit
Notify All Dma Write Transactions
This bit is programmed to enable the System
DMA Done functionality for all the DMA write
Transactions corresponding to the
Channel/Endpoint. This bit is valid only when
GAHBCFG.RemMemSupp is set to 1.
GAHBCFG.NotiAllDmaWrit = 1.
HSOTG core asserts int_dma_req for all the
DMA write transactions on the AHB interface
along with int_dma_done, chep_last_transact
22 RW 0x0 and chep_number signal informations. The
core waits for sys_dma_done signal for all the
DMA write transactions in order to complete
the transfer of a particular Channel/Endpoint.
GAHBCFG.NotiAllDmaWrit = 0.
HSOTG core asserts int_dma_req signal only
for the last transaction of DMA write transfer
corresponding to a particular
Channel/Endpoint. Similarly, the core waits
for sys_dma_done signal only for that
transaction of DMA write to complete the
transfer of a particular Channel/Endpoint.

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Bit Attr Reset Value Description

RemMemSupp
Remote Memory Support
This bit is programmed to enable the
functionality to wait for the system DMA Done
Signal for the DMA Write Transfers.
GAHBCFG.RemMemSupp=1.
The int_dma_req output signal is asserted
when HSOTG DMA starts write transfer to the
external memory. When the core is done with
the Transfers it asserts int_dma_done signal
to flag the completion of DMA writes from
HSOTG. The core then waits for
21 RW 0x0
sys_dma_done signal from the system to
proceed further and complete the Data
Transfer corresponding to a particular
Channel/Endpoint.
GAHBCFG.RemMemSupp=0.
The int_dma_req and int_dma_done signals
are not asserted and the core proceeds with
the assertion of the XferComp interrupt as
soon as the DMA write transfer is done at the
HSOTG Core Boundary and it does not wait for
the sys_dma_done signal to complete the
DATA transfers.
20:9 RO 0x0 reserved
PTxFEmpLvl
Periodic TxFIFO Empty Level
Indicates when the Periodic TxFIFO Empty
Interrupt bit in the Core Interrupt register
(GINTSTS.PTxFEmp) is triggered. This bit is
8 RW 0x0
used only in Slave mode.
1'b0: GINTSTS.PTxFEmp interrupt indicates
that the Periodic TxFIFO is half empty
1'b1: GINTSTS.PTxFEmp interrupt indicates
that the Periodic TxFIFO is completely empty

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Bit Attr Reset Value Description

NPTxFEmpLvl
Non-Periodic TxFIFO Empty Level
This bit is used only in Slave mode. In host
mode and with Shared FIFO with device mode,
this bit indicates when the Non-Periodic
TxFIFO Empty Interrupt bit in the Core
Interrupt register GINTSTS.NPTxFEmp) is
triggered. With dedicated FIFO in device
mode, this bit indicates when IN endpoint
Transmit FIFO empty interrupt
(DIEPINTn.TxFEmp) is triggered.
Host mode and with Shared FIFO with device
7 RW 0x0
mode:
1'b0: GINTSTS.NPTxFEmp interrupt indicates
that the Non-Periodic TxFIFO is half empty
1'b1: GINTSTS.NPTxFEmp interrupt indicates
that the Non-Periodic TxFIFO is completely
empty
Dedicated FIFO in device mode:
1'b0: DIEPINTn.TxFEmp interrupt indicates
that the IN Endpoint TxFIFO is half empty
1'b1: DIEPINTn.TxFEmp interrupt indicates
that the IN Endpoint TxFIFO is completely
empty
6 RO 0x0 reserved
DMAEn
DMA Enable
1'b0: Core operates in Slave mode
5 RW 0x0
1'b1: Core operates in a DMA mode
This bit is always 0 when Slave-Only mode has
been selected.

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Bit Attr Reset Value Description

HBstLen
Burst Length/Type
This field is used in both External and Internal
DMA modes. In External DMA mode, these
bits appear on dma_burst[3:0] ports, External
DMA Mode defines the DMA burst length in
terms of 32-bit words:
4'b0000: 1 word
4'b0001: 4 words
4'b0010: 8 words
4'b0011: 16 words
4:1 RW 0x0 4'b0100: 32 words
4'b0101: 64 words
4'b0110: 128 words
4'b0111: 256 words
Others: Reserved
Internal DMA Mode AHB Master burst type:
4'b0000: Single
4'b0001: INCR
4'b0011: INCR4
4'b0101: INCR8
4'b0111: INCR16
Others: Reserved
GlblIntrMsk
Global Interrupt Mask
The application uses this bit to mask or
unmask the interrupt line assertion to itself.
Irrespective of this bit's setting, the interrupt
0 RW 0x0
status registers are updated by the core.
1'b0: Mask the interrupt assertion to the
application.
1'b1: Unmask the interrupt assertion to the
application.

USBOTG_GUSBCFG
Address: Operational Base + offset (0x000c)
USB Configuration Register
Bit Attr Reset Value Description
CorruptTxpacket
Corrupt Tx packet
31 RW 0x0
This bit is for debug purposes only. Never set
this bit to 1.

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Bit Attr Reset Value Description

ForceDevMode
Force Device Mode
Writing a 1 to this bit forces the core to device
mode irrespective of utmiotg_iddig input pin.
1'b0: Normal Mode
1'b1: Force Device Mode
30 RW 0x0
After setting the force bit, the application
must wait at least 25 ms before the change to
take effect. When the simulation is in scale
down mode, waiting for 500 us is sufficient.
This bit is valid only when OTG_MODE = 0, 1
or 2. In all other cases, this bit reads 0.
ForceHstMode
Force Host Mode
Writing a 1 to this bit forces the core to host
mode irrespective of utmiotg_iddig input pin.
1'b0: Normal Mode
1'b1: Force Host Mode
29 RW 0x0
After setting the force bit, the application
must wait at least 25 ms before the change to
take effect. When the simulation is in scale
down mode, waiting for 500 us is sufficient.
This bit is valid only when OTG_MODE =0, 1 or
2. In all other cases, this bit reads 0.
TxEndDelay
Tx End Delay
Writing a 1 to this bit enables the TxEndDelay
28 RW 0x0
timers in the core.
1'b0: Normal mode
1'b1: Introduce Tx end delay timers
IC_USBTrafCtl
IC_USB Traffic Pull Remove Control
When this bit is set, pullup/pulldown resistors
are detached from the USB
27 RW 0x0
during traffic signaling. This bit is valid only
when configuration parameter
OTG_ENABLE_IC_USB = 1 and register field
GUSBCFG.IC_USBCap is set to 1.
IC_USBCap
IC_USB-Capable
The application uses this bit to control the
IC_USB capabilities.
1'b0: IC_USB PHY Interface is not selected.
1'b1: IC_USB PHY Interface is selected.
26 RW 0x0 This bit is writable only if
OTG_ENABLE_IC_USB=1 and
OTG_FSPHY_INTERFACE!=0.The reset value
depends on the configuration parameter
OTG_SELECT_IC_USB when
OTG_ENABLE_IC_USB = 1. In all other cases,
this bit is set to 1'b0 and the bit is read only.

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Bit Attr Reset Value Description

ULPIIfDis
ULPI Interface Protect Disable
Controls circuitry built into the PHY for
protecting the ULPI interface when the link
tri-states STP and data. Any pull-ups or
25 RW 0x0
pull-downs employed by this feature can be
disabled. Please refer to the ULPI Specification
for more detail.
1'b0: Enables the interface protect circuit
1'b1: Disables the interface protect circuit
IndPassThrough
Indicator Pass Through
Controls whether the Complement Output is
qualified with the Internal Vbus Valid
comparator before being used in the Vbus
State in the RX CMD. Please refer to the ULPI
24 RW 0x0
Specification for more detail.
1'b0: Complement Output signal is qualified
with the Internal VbusValid comparator.
1'b1: Complement Output signal is not
qualified with the Internal VbusValid
comparator.
IndComple
Indicator Complement
Controls the PHY to invert the
ExternalVbusIndicator input signal,
generating the Complement Output. Please
23 RW 0x0
refer to the ULPI Specification for more detail
1'b0: PHY does not invert External Vbus
Indicator signal
1'b1: PHY does invert External Vbus Indicator
signal
TermSelDLPulse
TermSel DLine Pulsing Selection
This bit selects utmi_termselect to drive data
22 RW 0x0 line pulse during SRP.
1'b0: Data line pulsing using utmi_txvalid
(default).
1'b1: Data line pulsing using utmi_termsel.
ULPIExtVbusIndicator
ULPI External VBUS Indicator
This bit indicates to the ULPI PHY to use an
external VBUS over-current indicator.
1'b0: PHY uses internal VBUS valid
21 RW 0x0
comparator.
1'b1: PHY uses external VBUS valid
comparator.
(Valid only when RTL parameter
OTG_HSPHY_INTERFACE = 2 or 3)

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Bit Attr Reset Value Description

ULPIExtVbusDrv
ULPI External VBUS Drive
This bit selects between internal or external
supply to drive 5V on VBUS,in ULPI PHY.
20 RW 0x0 1'b0: PHY drives VBUS using internal charge
pump (default).
1'b1: PHY drives VBUS using external supply.
(Valid only when RTL parameter
OTG_HSPHY_INTERFACE = 2 or 3)
ULPIClkSusM
ULPI Clock SuspendM
This bit sets the ClockSuspendM bit in the
Interface Control register on the ULPI PHY.
This bit applies only in serial or carkit modes.
19 RW 0x0
1'b0: PHY powers down internal clock during
suspend.
1'b1: PHY does not power down internal clock.
(Valid only when RTL parameter
OTG_HSPHY_INTERFACE = 2 or 3)
ULPIAutoRes
ULPI Auto Resume
This bit sets the AutoResume bit in the
Interface Control register on the ULPI PHY.
18 RW 0x0
1'b0: PHY does not use AutoResume feature.
1'b1: PHY uses AutoResume feature.
(Valid only when RTL parameter
OTG_HSPHY_INTERFACE = 2 or 3)
ULPIFsLs
ULPI FS/LS Select
The application uses this bit to select the
FS/LS serial interface for the ULPI PHY. This
bit is valid only when the FS serial transceiver
17 RW 0x0 is selected on the ULPI PHY.
1'b0: ULPI interface
1'b1: ULPI FS/LS serial interface
(Valid only when RTL parameters
OTG_HSPHY_INTERFACE = 2 or 3 and
OTG_FSPHY_INTERFACE = 1, 2, or 3)
OtgI2CSel
UTMIFS or I2C Interface Select
The application uses this bit to select the I2C
interface.
1'b0: UTMI USB 1.1 Full-Speed interface for
16 RW 0x0 OTG signals
1'b1: I2C interface for OTG signals
This bit is writable only if I2C and UTMIFS
were specified for Enable I2C Interface?
(parameter OTG_I2C_INTERFACE = 2).
Otherwise, reads return 0.

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Bit Attr Reset Value Description

PhyLPwrClkSel
PHY Low-Power Clock Select
Selects either 480-MHz or 48-MHz
(low-power) PHY mode. In FS and LS modes,
the PHY can usually operate on a 48-MHz clock
to save power.
1'b0: 480-MHz Internal PLL clock
1'b1: 48-MHz External Clock
15 RW 0x0
In 480 MHz mode, the UTMI interface
operates at either 60 or 30-MHz, depending
upon whether 8- or 16-bit data width is
selected. In 48-MHz mode, the UTMI interface
operates at 48 MHz in FS and LS modes. This
bit drives the utmi_fsls_low_power core
output signal, and is valid only for UTMI+
PHYs.
14 RO 0x0 reserved
USBTrdTim
USB Turnaround Time
Sets the turnaround time in PHY clocks.
Specifies the response time for a MAC request
to the Packet FIFO Controller (PFC) to fetch
data from the DFIF(SPRAM). This must be
programmed to
4'h5: When the MAC interface is 16-bit
UTMI+.
13:10 RW 0x5
4'h9: When the MAC interface is 8-bit UTMI+.
Note: The values above are calculated for the
minimum AHB frequency of 30 MHz. USB
turnaround time is critical for certification
where long cables and 5-Hubs are used, so if
you need the AHB to run at less than 30 MHz,
and if USB turnaround time is not critical,
these bits can be programmed to a larger
value.
HNPCap
HNP-Capable
The application uses this bit to control the Otg
core's HNP capabilities.
9 RW 0x0 1'b0: HNP capability is not enabled.
1'b1: HNP capability is enabled.
This bit is writable only if an HNP mode was
specified for Mode of Operation (parameter
OTG_MODE). Otherwise, reads return 0.

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Bit Attr Reset Value Description

SRPCap
SRP-Capable
The application uses this bit to control the Otg
core SRP capabilities. If the core operates as a
non-SRP-capable B-device, it cannot request
the connected A-device (host) to activate
8 RW 0x0
VBUS and start a session.
0: SRP capability is not enabled.
1: SRP capability is enabled.
This bit is writable only if an SRP mode was
specified for Mode of Operation (parameter
OTG_MODE). Otherwise, reads return 0.
DDRSel
ULPI DDR Select
The application uses this bit to select a Single
Data Rate (SDR) or Double Data Rate (DDR)
7 RW 0x0 or ULPI interface.
1'b0: Single Data Rate ULPI Interface, with
8-bit-wide data bus
1'b1: Double Data Rate ULPI Interface, with
4-bit-wide data bus
PHYSel
USB 2.0 High-Speed PHY or USB 1.1
Full-Speed Serial Transceiver
The application uses this bit to select either a
high-speed UTMI+ or ULPI PHY, or a
full-speed transceiver.
1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY
1'b1: USB 1.1 full-speed serial transceiver
If a USB 1.1 Full-Speed Serial Transceiver
interface was not selected (parameter
6 RW 0x0
OTG_FSPHY_INTERFACE = 0), this bit is
always 0, with Write Only access. If a
high-speed PHY interface was not selected
(parameter OTG_HSPHY_INTERFACE = 0),
this bit is always 1, with Write Only access.
If both interface types were selected
(parameters have non-zero values), the
application uses this bit to select which
interface is active, and access is Read and
Write.

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Bit Attr Reset Value Description

FSIntf
Full-Speed Serial Interface Select
The application uses this bit to select either a
unidirectional or bidirectional USB 1.1
full-speed serial transceiver interface.
1'b0: 6-pin unidirectional full-speed serial
interface
1'b1: 3-pin bidirectional full-speed serial
interface
5 RW 0x0
If a USB 1.1 Full-Speed Serial Transceiver
interface was not selected (parameter
OTG_FSPHY_INTERFACE = 0), this bit is
always 0, with Write Only access. If a USB 1.1
FS interface was selected (parameter
OTG_FSPHY_INTERFACE! = 0), then the
application can set this bit to select between
the 3- and 6-pin interfaces, and access is Read
and Write.
ULPI_UTMI_Sel
ULPI or UTMI+ Select
The application uses this bit to select either a
UTMI+ interface or ULPI Interface.
1'b0: UTMI+ Interface
1'b1: ULPI Interface
4 RW 0x0 This bit is writable only if UTMI+ and ULPI was
specified for High-Speed
PHY Interface(s) (parameter
OTG_HSPHY_INTERFACE = 3). Otherwise,
reads return either 0 or 1,
depending on the interface selected using the
OTG_HSPHY_INTERFACE parameter.
PHYIf
PHY Interface
The application uses this bit to configure the
core to support a UTMI+ PHY with an 8- or
16-bit interface. When a ULPI PHY is chosen,
this must be set to 8-bit mode.
3 RW 0x0 1'b0: 8 bits
1'b1: 16 bits
This bit is writable only if UTMI+ and ULPI
were selected (parameter
OTG_HSPHY_DWIDTH = 3). Otherwise, this
bit returns the value for the power-on
interface selected during configuration.

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Bit Attr Reset Value Description

TOutCal
HS/FS Timeout Calibration
The number of PHY clocks that the application
programs in this field is added to the
high-speed/full-speed inter-packet timeout
duration in the core to account for any
additional delays introduced by the PHY. This
can be required, because the delay introduced
by the PHY in generating the line state
condition can vary from one PHY to another.
The USB standard timeout value for
high-speed operation is 736 to 816 (inclusive)
2:0 RW 0x0
bit times. The USB standard timeout value for
full-speed operation is 16 to 18 (inclusive) bit
times. The application must program this field
based on the speed of enumeration. The
number of bit times added per PHY clock are:
High-speed operation:
One 30-MHz PHY clock = 16 bit times
One 60-MHz PHY clock = 8 bit times
Full-speed operation:
One 30-MHz PHY clock = 0.4 bit times
One 60-MHz PHY clock = 0.2 bit times
One 48-MHz PHY clock = 0.25 bit times

USBOTG_GRSTCTL
Address: Operational Base + offset (0x0010)
Reset Register
Bit Attr Reset Value Description
AHBIdle
AHB Master Idle
31 RO 0x1
Indicates that the AHB Master State Machine
is in the IDLE condition.
DMAReq
DMA Request Signal
30 RO 0x0
Indicates that the DMA request is in progress.
Used for debug.
29:11 RO 0x0 reserved

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Bit Attr Reset Value Description

TxFNum
TxFIFO Number
This is the FIFO number that must be flushed
using the TxFIFO Flush bit. This field must not
be changed until the core clears the TxFIFO
Flush bit.
5'h0: Non-periodic TxFIFO flush in Host mode;
Non-periodic TxFIFO flush in device mode
when in shared FIFO operation. Tx FIFO 0
flush in device mode when in dedicated FIFO
mode.
5'h1: Periodic TxFIFO flush in Host mode:
Periodic TxFIFO 1 flush in Device mode when
10:6 RW 0x00
in shared FIFO operation; TXFIFO 1 flush in
device mode when in dedicated FIFO mode.
5'h2: Periodic TxFIFO 2 flush in Device mode
when in shared FIFO operation: TXFIFO 2
flush in device mode when in dedicated FIFO
mode.
...
5'hF: Periodic TxFIFO 15 flush in Device mode
when in shared FIFO operation: TXFIFO 15
flush in device mode when in dedicated FIFO
mode.
5'h10: Flush all the transmit FIFOs in device or
host mode.
TxFFlsh
TxFIFO Flush
This bit selectively flushes a single or all
transmit FIFOs, but cannot do so if
the core is in the midst of a transaction. The
application must write this bit only after
checking that the core is neither writing to the
TxFIFO nor reading from the TxFIFO. Verify
using these registers: Read NAK Effective
Interrupt ensures the core is not reading from
5 R/WSC 0x0 the FIFO. Write GRSTCTL.AHBIdle ensures the
core is not writing anything to the FIFO.
Flushing is normally recommended when
FIFOs are re-configured or when switching
between Shared FIFO and Dedicated Transmit
FIFO operation. FIFO flushing is also
recommended during device endpoint disable.
The application must wait until the core clears
this bit before performing any operations. This
bit takes eight clocks to clear, using the slower
clock of phy_clk or hclk.

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Bit Attr Reset Value Description

RxFFlsh
RxFIFO Flush
The application can flush the entire RxFIFO
using this bit, but must first ensure that the
core is not in the middle of a transaction. The
application must only write to this bit after
4 R/WSC 0x0
checking that the core is neither reading from
the RxFIFO nor writing to the RxFIFO. The
application must wait until the bit is cleared
before performing any other operations. This
bit requires 8 clocks (slowest of PHY or AHB
clock) to clear.
INTknQFlsh
IN Token Sequence Learning Queue Flush
3 R/WSC 0x0 This bit is valid only if OTG_EN_DED_TX_FIFO
= 0. The application writes this bit to flush the
IN Token Sequence Learning Queue.
FrmCntrRst
Host Frame Counter Reset
The application writes this bit to reset the
2 W1C 0x0 (micro) frame number counter inside the core.
When the (micro) frame counter is reset, the
subsequent SOF sent out by the core has a
(micro) frame number of 0.
Reset
1 R/WSC 0x0 A write to this bit issues a soft reset to the
Otg_power_dn module of the core.

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Bit Attr Reset Value Description

CSftRst
Core Soft Reset
Resets the hclk and phy_clock domains as
follows: Clears the interrupts and all the CSR
registers except the following register bits:
PCGCCTL.RstPdwnModule
PCGCCTL.GateHclk
PCGCCTL.PwrClmp
PCGCCTL.StopPPhyLPwrClkSelclk
GUSBCFG.PhyLPwrClkSel
GUSBCFG.DDRSel
GUSBCFG.PHYSel
GUSBCFG.FSIntf
GUSBCFG.ULPI_UTMI_Sel
GUSBCFG.PHYIf
HCFG.FSLSPclkSel
DCFG.DevSpd
GGPIO
GPWRDN
GADPCTL
All module state machines (except the AHB
Slave Unit) are reset to the IDLE state, and all
the transmit FIFOs and the receive FIFO are
flushed. Any transactions on the AHB Master
are terminated as soon as possible, after
0 R/WSC 0x0
gracefully completing the last data phase of
an AHB transfer. Any transactions on the USB
are terminated immediately. When
Hibernation or ADP feature is enabled, the
PMU module is not reset by the Core Soft
Reset. The application can write to this bit any
time it wants to reset the core. This is a
self-clearing bit and the core clears this bit
after all the necessary logic is reset in the
core, which can take several clocks,
depending on the current state of the core.
Once this bit is cleared software must wait at
least 3 PHY clocks before doing any access to
the PHY domain (synchronization delay).
Software must also must check that bit 31 of
this register is 1 (AHB Master is IDLE) before
starting any operation. Typically software
reset is used during software development
and also when you dynamically change the
PHY selection bits in the USB configuration
registers listed above. When you change the
PHY, the corresponding clock for the PHY is
selected and used in the PHY domain. Once a
new clock is selected, the PHY domain has to
be reset for proper operation.

USBOTG_GINTSTS

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Address: Operational Base + offset (0x0014)

Interrupt Register
Bit Attr Reset Value Description
WkUpInt
Resume/Remote Wakeup Detected Interrupt
Wakeup Interrupt during Suspend (L2) or
LPM(L1) state.
During Suspend(L2):
Device Mode: This interrupt is asserted only
when Host Initiated Resume is detected on
USB.
Host Mode: This interrupt is asserted only
31 W1C 0x0
when Device Initiated Remote Wakeup is
detected on USB.
During LPM(L1):
Device Mode: This interrupt is asserted for
either Host Initiated Resume or Device
Initiated Remote Wakeup on USB.
Host Mode: This interrupt is asserted for
either Host Initiated Resume or Device
Initiated Remote Wakeup on USB.
SessReqInt
Session Request/New Session Detected
Interrupt
In Host mode, this interrupt is asserted when
30 W1C 0x0 a session request is detected from the device.
In Host mode, this interrupt is asserted when
a session request is detected from the device.
In Device mode, this interrupt is asserted
when the utmisrp_bvalid signal goes high.
DisconnInt
Disconnect Detected Interrupt
29 W1C 0x0
This interrupt is asserted when a device
disconnect is detected.
ConIDStsChng
Connector ID Status Change
28 W1C 0x0
This interrupt is asserted when there is a
change in connector ID status.
LPM_Int
LPM Transaction Received Interrupt
Device Mode : This interrupt is asserted when
the device receives an LPM transaction and
responds with a non-ERRORed response. Host
Mode :This interrupt is asserted when the
27 W1C 0x0 device responds to an LPM transaction with a
non-ERRORed response or when the host core
has completed LPM transactions for the
programmed number of times
(GLPMCFG.RetryCnt). This field is valid only if
the Core LPM Configuration register's
LPMCapable (LPMCap) field is set to 1.

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Bit Attr Reset Value Description

PTxFEmp
Periodic TxFIFO Empty
This interrupt is asserted when the Periodic
Transmit FIFO is either half or completely
empty and there is space for at least one entry
26 RO 0x0
to be written in the Periodic Request Queue.
The half or completely empty status is
determined by the Periodic TxFIFO Empty
Level bit in the Core AHB Configuration
register (GAHBCFG.PTxFEmpLvl).
HChInt
Host Channels Interrupt
The core sets this bit to indicate that an
interrupt is pending on one of the channels of
the core (in Host mode). The application must
read the Host All Channels Interrupt (HAINT)
25 RO 0x0 register to determine the exact number of the
channel on which the interrupt occurred, and
then read the corresponding Host Channel-n
Interrupt (HCINTn) register to determine the
exact cause of the interrupt. The application
must clear the appropriate status bit in the
HCINTn register to clear this bit.
PrtInt
Host Port Interrupt
The core sets this bit to indicate a change in
port status of one of the OTG core ports in
Host mode. The application must read the
24 RO 0x0
Host Port Control and Status (HPRT) register
to determine the exact event that caused this
interrupt. The application must clear the
appropriate status bit in the Host Port Control
and Status register to clear this bit.
ResetDet
Reset Detected Interrupt
The core asserts this interrupt in Device mode
23 RW 0x0 when it detects a reset on the USB in Partial
Power-Down mode when the device is in
Suspend. This interrupt is not asserted in Host
mode.
FetSusp
Data Fetch Suspended
This interrupt is valid only in DMA mode. This
interrupt indicates that the core has stopped
22 W1C 0x0 fetching data for IN endpoints due to the
unavailability of TxFIFO space or Request
Queue space. This interrupt is used by the
application for an endpoint mismatch
algorithm.

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Bit Attr Reset Value Description

incomplP
Incomplete Periodic Transfer
In Host mode, the core sets this interrupt bit
when there are incomplete periodic
transactions still pending which are scheduled
for the current micro-frame. Incomplete
Isochronous OUT Transfer (incompISOOUT)
21 W1C 0x0
The Device mode, the core sets this interrupt
to indicate that there is at least one
isochronous OUT endpoint on which the
transfer is not completed in the current
micro-frame. This interrupt is asserted along
with the End of Periodic Frame Interrupt
(EOPF) bit in this register.
incompISOIN
Incomplete Isochronous IN Transfer
The core sets this interrupt to indicate that
there is at least one isochronous IN endpoint
on which the transfer is not completed in the
20 W1C 0x0
current micro-frame. This interrupt is
asserted along with the End of Periodic Frame
Interrupt (EOPF) bit in this register. Note: This
interrupt is not asserted in Scatter/Gather
DMA mode.
OEPInt
OUT Endpoints Interrupt
The core sets this bit to indicate that an
interrupt is pending on one of the OUT
endpoints of the core (in Device mode). The
application must read the Device All Endpoints
Interrupt (DAINT) register to determine the
19 RO 0x0 exact number of the OUT endpoint on which
the interrupt occurred, and then read the
corresponding Device OUT Endpoint-n
Interrupt (DOEPINTn) register to determine
the exact cause of the interrupt. The
application must clear the appropriate status
bit in the corresponding DOEPINTn register to
clear this bit.

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Bit Attr Reset Value Description

IEPInt
IN Endpoints Interrupt
The core sets this bit to indicate that an
interrupt is pending on one of the IN
endpoints of the core (in Device mode). The
application must read the Device All Endpoints
Interrupt (DAINT) register to determine the
18 RO 0x0 exact number of the IN endpoint on which the
interrupt occurred, and then read the
corresponding Device IN Endpoint-n Interrupt
(DIEPINTn) register to determine the exact
cause of the interrupt. The application must
clear the appropriate status bit in the
corresponding DIEPINTn register to clear this
bit.
EPMis
Endpoint Mismatch Interrupt
Note: This interrupt is valid only in shared
FIFO operation. Indicates that an IN token has
17 W1C 0x0 been received for a non-periodic endpoint, but
the data for another endpoint is present in the
top of the Non-periodic Transmit FIFO and the
IN endpoint mismatch count programmed by
the application has expired.
RstrDoneInt
Restore Done Interrupt
The core sets this bit to indicate that the
restore command after Hibernation was
16 W1C 0x0 completed by the core. The core continues
from Suspended state into the mode dictated
by PCGCCTL.RestoreMode field.This bit is
valid only when Hibernation feature is
enabled.
EOPF
End of Periodic Frame Interrupt
Indicates that the period specified in the
15 W1C 0x0
Periodic Frame Interval field of the Device
Configuration register (DCFG.PerFrInt) has
been reached in the current microframe.
ISOOutDrop
Isochronous OUT Packet Dropped Interrupt
The core sets this bit when it fails to write an
14 W1C 0x0 isochronous OUT packet into the RxFIFO
because the RxFIFO does not have enough
space to accommodate a maximum packet
size packet for the isochronous OUT endpoint.
EnumDone
Enumeration Done
The core sets this bit to indicate that speed
13 W1C 0x0
enumeration is complete. The application
must read the Device Status (DSTS) register
to obtain the enumerated speed.

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Bit Attr Reset Value Description

USBRst
USB Reset
12 W1C 0x0
The core sets this bit to indicate that a reset is
detected on the USB.
USBSusp
USB Suspend
The core sets this bit to indicate that a
11 W1C 0x0 suspend was detected on the USB. The core
enters the Suspended state when there is no
activity on the utmi_linestate signal for an
extended period of time.
ErlySusp
Early Suspend
10 W1C 0x0
The core sets this bit to indicate that an Idle
state has been detected on the USB for 3 ms.
I2CINT
I2C Interrupt
The core sets this interrupt when I2C access is
9 W1C 0x0
completed on the I2C interface. This field is
used only if the I2C interface was enabled .
Otherwise, reads return 0.
ULPICKINT
ULPI Carkit Interrupt
This field is used only if the Carkit interface
was enabled . Otherwise, reads return 0. The
core sets this interrupt when a ULPI Carkit
interrupt is received. The core's PHY sets ULPI
8 W1C 0x0 Carkit interrupt in UART or Audio mode. I2C
Carkit Interrupt (I2CCKINT) This field is used
only if the I2C interface was enabled .
Otherwise, reads return 0.The core sets this
interrupt when a Carkit interrupt is received.
The core's PHY sets the I2C Carkit interrupt in
Audio mode.
GOUTNakEff
Global OUT NAK Effective
Indicates that the Set Global OUT NAK bit in
the Device Control register DCTL.SGOUTNak),
7 RO 0x0
set by the application, has taken effect in the
core. This bit can be cleared by writing the
Clear Global OUT NAK bit in the Device Control
register (DCTL.CGOUTNak).

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Bit Attr Reset Value Description

GINNakEff
Global IN Non-Periodic NAK Effective
Indicates that the Set Global Non-periodic IN
NAK bit in the Device Control register
(DCTL.SGNPInNak), set by the application,
has taken effect in the core. That is, the core
6 RO 0x0 has sampled the Global IN NAK bit set by the
application. This bit can be cleared by clearing
the Clear Global Nonperiodic IN NAK bit in the
Device Control register (DCTL.CGNPInNak).
This interrupt does not necessarily mean that
a NAK handshake is sent out on the USB. The
STALL bit takes precedence over the NAK bit.
NPTxFEmp
Non-Periodic TxFIFO Empty
This interrupt is valid only when
OTG_EN_DED_TX_FIFO = 0. This interrupt is
asserted when the Non-periodic TxFIFO is
either half or completely empty, and there is
5 RO 0x0
space for at least one entry to be written to
the Non-periodic Transmit Request Queue.
The half or completely empty status is
determined by the Non-periodic TxFIFO
Empty Level bit in the Core AHB Configuration
register(GAHBCFG.NPTxFEmpLvl).
RxFLvl
RxFIFO Non-Empty
4 RO 0x0
Indicates that there is at least one packet
pending to be read from the RxFIFO.
Sof
Start of (micro)Frame
In Host mode, the core sets this bit to indicate
that an SOF (FS), micro-SOF(HS), or
Keep-Alive (LS) is transmitted on the USB.
The application must write a 1 to this bit to
3 W1C 0x0 clear the interrupt. In Device mode, in the
core sets this bit to indicate that an SOF token
has been received on the USB. The application
can read the Device Status register to get the
current (micro) frame number. This interrupt
is seen only when the core is operating at
either HS or FS.
OTGInt
OTG Interrupt
The core sets this bit to indicate an OTG
protocol event. The application must read the
2 RO 0x0 OTG Interrupt Status (GOTGINT) register to
determine the exact event that caused this
interrupt. The application must clear the
appropriate status bit in the GOTGINT register
to clear this bit.

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Bit Attr Reset Value Description

ModeMis
Mode Mismatch Interrupt
The core sets this bit when the application is
trying to access: A Host mode register, when
the core is operating in Device mode; A Device
1 W1C 0x0
mode register, when the core is operating in
Host mode. The register access is completed
on the AHB with an OKAY response, but is
ignored by the core internally and does not
affect the operation of the core.
CurMod
Current Mode of Operation
0 RO 0x0 Indicates the current mode.
1'b0: Device mode
1'b1: Host mode

USBOTG_GINTMSK
Address: Operational Base + offset (0x0018)
Interrupt Mask Register
Bit Attr Reset Value Description
WkUpIntMsk
31 RW 0x0 Resume/Remote Wakeup Detected Interrupt
Mask
SessReqIntMsk
30 RW 0x0 Session Request/New Session Detected
Interrupt Mask
DisconnIntMsk
29 RW 0x0
Disconnect Detected Interrupt Mask
ConIDStsChngMsk
28 RW 0x0
Connector ID Status Change Mask
LPM_IntMsk
27 RW 0x0
LPM Transaction Received Interrupt Mask
PTxFEmpMsk
26 RW 0x0
Periodic TxFIFO Empty Mask
HChIntMsk
25 RW 0x0
Host Channels Interrupt Mask
PrtIntMsk
24 RW 0x0
Host Port Interrupt Mask
ResetDetMsk
23 RW 0x0
Reset Detected Interrupt Mask
FetSuspMsk
22 RW 0x0
Data Fetch Suspended Mask
incomplPMsk_incompISOOUTMsk
Incomplete Periodic Transfer Mask(Host only)
21 RW 0x0
Incomplete Isochronous OUT Transfer
Mask(Device only)
incompISOINMsk
20 RW 0x0
Incomplete Isochronous IN Transfer Mask
OEPIntMsk
19 RW 0x0
OUT Endpoints Interrupt Mask

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Bit Attr Reset Value Description

IEPIntMsk
18 RW 0x0
IN Endpoints Interrupt Mask
EPMisMsk
17 RW 0x0
Endpoint Mismatch Interrupt Mask
RstrDoneIntMsk
Restore Done Interrupt Mask
16 RW 0x0
This field is valid only when Hibernation
feature is enabled.
EOPFMsk
15 RW 0x0
End of Periodic Frame Interrupt Mask
ISOOutDropMsk
14 RW 0x0 Isochronous OUT Packet Dropped Interrupt
Mask
EnumDoneMsk
13 RW 0x0
Enumeration Done Mask
USBRstMsk
12 RW 0x0
USB Reset Mask
USBSuspMsk
11 RW 0x0
USB Suspend Mask
ErlySuspMsk
10 RW 0x0
Early Suspend Mask
I2CIntMsk
9 RW 0x0
I2C Interrupt Mask
ULPICKINTMsk_I2CCKINTMsk
8 RW 0x0 ULPI Carkit Interrupt Mask (ULPICKINTMsk)
I2C Carkit Interrupt Mask (I2CCKINTMsk)
GOUTNakEffMsk
7 RW 0x0
Global OUT NAK Effective Mask
GINNakEffMsk
6 RW 0x0
Global Non-periodic IN NAK Effective Mask
NPTxFEmpMsk
5 RW 0x0
Non-periodic TxFIFO Empty Mask
RxFLvlMsk
4 RW 0x0
Receive FIFO Non-Empty Mask
SofMsk
3 RW 0x0
Start of (micro)Frame Mask
OTGIntMsk
2 RW 0x0
OTG Interrupt Mask
ModeMisMsk
1 RW 0x0
Mode Mismatch Interrupt Mask
0 RO 0x0 reserved

USBOTG_GRXSTSR
Address: Operational Base + offset (0x001c)
Receive Status Debug Read Register
Bit Attr Reset Value Description
31:25 RO 0x0 reserved

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Bit Attr Reset Value Description

FN
Frame Number
(Device Only)This is the least significant 4 bits
24:21 RO 0x0 of the (micro) frame number in which the
packet is received on the USB. This field is
supported only when isochronous OUT
endpoints are supported.
PktSts
Packet Status
Indicates the status of the received
packet(Host Only)
4'b0010: IN data packet received
4'b0011: IN transfer completed (triggers an
interrupt)
4'b0101: Data toggle error (triggers an
interrupt)
4'b0111: Channel halted (triggers an
interrupt)
20:17 RO 0x0 Others: Reserved
Indicates the status of the received
packet(Device only)
4'b0001: Global OUT NAK (triggers an
interrupt)
4'b0010: OUT data packet received
4'b0011: OUT transfer completed (triggers
an interrupt)
4'b0100: SETUP transaction completed
(triggers an interrupt)
4'b0110: SETUP data packet received
Others: Reserved
DPID
Data PID
Indicates the Data PID of the received packet
16:15 RO 0x0 2'b00: DATA0
2'b10: DATA1
2'b01: DATA2
2'b11: MDATA
BCnt
Byte Count
14:4 RW 0x000
Indicates the byte count of the received data
packet.
ChNum_EPNum
Channel Number(Host) Endpoint
Number(Device)
3:0 RO 0x0 (Host Only) Indicates the channel number to
which the current received packet belongs.
(Device Only) Indicates the endpoint number
to which the current received packet belongs.

USBOTG_GRXSTSP
Address: Operational Base + offset (0x0020)
Receive Status Read and Pop Register

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Bit Attr Reset Value Description

31:25 RO 0x0 reserved
FN
Frame Number
(Device Only) This is the least significant 4
24:21 RO 0x0 bits of the (micro) frame number in which the
packet is received on the USB. This field is
supported only when isochronous OUT
endpoints are supported.
PktSts
Packet Status
Indicates the status of the received
packet(Host Only)
4'b0010: IN data packet received
4'b0011: IN transfer completed (triggers an
interrupt)
4'b0101: Data toggle error (triggers an
interrupt)
4'b0111: Channel halted (triggers an
interrupt)
20:17 RO 0x0 Others: Reserved
Indicates the status of the received
packet(Device only)
4'b0001: Global OUT NAK (triggers an
interrupt)
4'b0010: OUT data packet received
4'b0011: OUT transfer completed (triggers
an interrupt)
4'b0100: SETUP transaction completed
(triggers an interrupt)
4'b0110: SETUP data packet received
Others: Reserved
DPID
Data PID
Indicates the Data PID of the received OUT
data packet
16:15 RO 0x0
2'b00: DATA0
2'b10: DATA1
2'b01: DATA2
2'b11: MDATA
BCnt
Byte Count
14:4 RO 0x000
Indicates the byte count of the received data
packet.
ChNum_EPNum
Channel Number(Host) Endpoint
Number(Device)
3:0 RO 0x0 (Host Only) Indicates the channel number to
which the current received packet belongs.
(Device Only) Indicates the endpoint number
to which the current received packet belongs.

USBOTG_GRXFSIZ

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Address: Operational Base + offset (0x0024)

Receive FIFO Size Register
Bit Attr Reset Value Description
31:16 RO 0x0 reserved
RxFDep
RxFIFO Depth
This value is in terms of 32-bit words.
Minimum value is 16, Maximum value is
32,768. The power-on reset value of this
register is specified as the Largest Rx Data
15:0 RW 0x0000 FIFO Depth. If Enable Dynamic FIFO Sizing?
was deselected, these flops are optimized,
and reads return the power-on value. If
Enable Dynamic FIFO Sizing? was selected ,
you can write a new value in this field. You can
write a new value in this field. Programmed
values must not exceed the power-on value.

USBOTG_GNPTXFSIZ
Address: Operational Base + offset (0x0028)
Non-Periodic Transmit FIFO Size Register
Bit Attr Reset Value Description
NPTxFDep
Non-periodic TxFIFO
For host mode, this field is always valid. For
Device mode, this field is valid only when
OTG_EN_DED_TX_FIFO==0. This value is in
terms of 32-bit words. Minimum value is 16
Maximum value is 32,768
This field is determined by Enable Dynamic
FIFO Sizing.
OTG_DFIFO_DYNAMIC = 0: These flops are
optimized, and reads return the
Power on value.
31:16 RW 0x0000 OTG_DFIFO_DYNAMIC = 1: The application
can write a new value in this field.
Programmed values must not exceed the
power-on value.
The power-on reset value of this field is
specified by OTG_EN_DED_TX_FIFO:
OTG_EN_DED_TX_FIFO = 0:The reset value
is the Largest Non-periodic Tx
Data FIFO Depth parameter,
OTG_TX_NPERIO_DFIFO_DEPTH.
OTG_EN_DED_TX_FIFO = 1: The reset value
is parameter
OTG_TX_HNPERIO_DFIFO_DEPTH.

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Bit Attr Reset Value Description

NPTxFStAddr
Non-periodic Transmit RAM
For host mode, this field is always valid. This
field contains the memory start address for
Non-periodic Transmit FIFO RAM. This field is
determined by Enable Dynamic FIFO
Sizing?(OTG_DFIFO_DYNAMIC):
OTG_DFIFO_DYNAMIC = 0: These flops are
15:0 RW 0x0000 optimized, and reads return the power-on
value.
OTG_DFIFO_DYNAMIC = 1: The application
can write a new value in this field.
Programmed values must not exceed the
power-on value.
The power-on reset value of this field is
specified by Largest Rx Data FIFO Depth
(parameter OTG_RX_DFIFO_DEPTH).

USBOTG_GNPTXSTS
Address: Operational Base + offset (0x002c)
Non-Periodic Transmit FIFO/Queue Status Register
Bit Attr Reset Value Description
31 RO 0x0 reserved
NPTxQTop
Top of the Non-periodic Transmit Request
Queue
Entry in the Non-periodic Tx Request Queue
that is currently being processed by the MAC.
Bits [30:27]: Channel/endpoint number
Bits [26:25]:
30:24 RO 0x00
2'b00: IN/OUT token
2'b01: Zero-length transmit packet (device
IN/host OUT)
2'b10: PING/CSPLIT token
2'b11: Channel halt command
Bit [24]: Terminate (last entry for selected
channel/endpoint)
NPTxQSpcAvail
Non-periodic Transmit Request Queue Space
Available
Indicates the amount of free space available in
the Non-periodic Transmit Request Queue.
This queue holds both IN and OUT requests in
Host mode. Device mode has only IN
23:16 RO 0x00
requests.
8'h0: Non-periodic Transmit Request Queue
is full
8'h1: 1 location available
8'h2: 2 locations available
n: n locations available (0 <=n <= 8)
Others: Reserved

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Bit Attr Reset Value Description

NPTxFSpcAvail
Non-periodic TxFIFO Space Avail
Indicates the amount of free space available in
the Non-periodic TxFIFO. Values are in terms
of 32-bit words.
16'h0: Non-periodic TxFIFO is full
15:0 RO 0x0000
16'h1: 1 word available
16'h2: 2 words available
16'hn: n words available (where 0 <=n
<=32,768)
16'h8000: 32,768 words available
Others: Reserved

USBOTG_GI2CCTL
Address: Operational Base + offset (0x0030)
I2C Address Register
Bit Attr Reset Value Description
BsyDne
I2C Busy/Done
The application sets this bit to 1'b1 to start a
request on the I2C interface. When the
31 R/WSC 0x0
transfer is complete, the core de-asserts this
bit to 1'b0. As long as the bit is set, indicating
that the I2C interface is busy, the application
cannot start another request on the interface.
RW
Read/Write Indicator
Indicates whether a read or write register
transfer must be performed on the interface.
30 RW 0x0
Read/write bursting is not supported for
registers.
1'b1: Read
1'b0: Write
29 RO 0x0 reserved
I2CDatSe0
I2C DatSe0 USB Mode
28 RW 0x1 Selects the FS interface USB mode.
1'b1: VP_VM USB mode
1'b0: DAT_SE0 USB mode
I2CDevAdr
I2C Device Address
Selects the address of the I2C Slave on the
USB 1.1 full-speed serial transceiver that the
27:26 RW 0x0 core uses for OTG signaling.
2'b00: 7'h2C
2'b01: 7'h2D
2'b10: 7'h2E
2'b11: 7'h2F

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Bit Attr Reset Value Description

I2CSuspCtl
I2C Suspend Control
Selects how Suspend is connected to a
25 RW 0x0 full-speed transceiver in I2C mode.
1'b0: Use the dedicated utmi_suspend_n pin
1'b1: Use an I2C write to program the
Suspend bit in the PHY register
Ack
I2C ACK
Indicates whether an ACK response was
received from the I2C Slave. This bit is valid
24 RO 0x1
when BsyDne is cleared by the core, after
application has initiated an I2C access.
1'b0: NAK
1'b1: ACK
I2CEn
I2C Enable
23 RW 0x0
Enables the I2C Master to initiate I2C
transactions on the I2C interface
Addr
I2C Address
This is the 7-bit I2C device address used by
software to access any external I2C Slave,
22:16 RW 0x00
including the I2C Slave on a USB 1.1 OTG
full-speed serial transceiver. Software can
change this address to access different I2C
Slaves.
RegAddr
I2C Register Addr
15:8 RW 0x00
This field programs the address of the register
to be read from or written to.
RWData
I2C Read/Write Data
After a register read operation, this field holds
the read data for the application. During a
7:0 RW 0x00
write operation, the application can use this
register to program the write data to be
written to a register. During writes, this field
holds the write data.

USBOTG_GPVNDCTL
Address: Operational Base + offset (0x0034)
PHY Vendor Control Register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

DisUlpiDrvr
Disable ULPI Drivers
This field is used only if the Carkit interface
was enabled (OTG_ULPI_CARKIT = 1).
Otherwise, reads return 0. The application
sets this bit when it has finished processing
31 R/WSC 0x0
the ULPI Carkit Interrupt
(GINTSTS.ULPICKINT). When set, the Otg
core disables drivers for output signals and
masks input signal for the ULPI interface. Otg
clears this bit before enabling the ULPI
interface.
30:28 RO 0x0 reserved
VStsDone
VStatus Done
The core sets this bit when the vendor control
27 R/WSC 0x0
access is done. This bit is cleared by the core
when the application sets the New Register
Request bit (bit 25).
VStsBsy
VStatus Busy
26 RO 0x0 The core sets this bit when the vendor control
access is in progress and clears this bit when
done.
NewRegReq
New Register Request
25 R/WSC 0x0
The application sets this bit for a new vendor
control access.
24:23 RO 0x0 reserved
RegWr
Register Write
22 RW 0x0
Set this bit for register writes, and clear it for
register reads.
RegAddr
Register Address
21:16 RW 0x00 The 6-bit PHY register address for immediate
PHY Register Set access. Set to
6'h2F for Extended PHY Register Set access.
VCtrl
UTMI+ Vendor Control Register Address
The 4-bit register address a vendor defined
15:8 RW 0x00 4-bit parallel output bus. Bits 11:8 of this field
are placed on utmi_vcontrol[3:0]. ULPI
Extended Register Address (ExtRegAddr) The
6-bit PHY extended register address.
RegData
Register Data
7:0 RW 0x00 Contains the write data for register write.
Read data for register read, valid when
VStatus Done is set.

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USBOTG_GGPIO
Address: Operational Base + offset (0x0038)
General Purpost Input/Output Register
Bit Attr Reset Value Description
GPO
General Purpose Output
This field is driven as an output from the core,
31:16 RW 0x0000
gp_o[15:0]. The application can program this
field to determine the corresponding value on
the gp_o[15:0] output.
GPI
General Purpose Input
15:0 RO 0x0000
This field's read value reflects the gp_i[15:0]
core input value.

USBOTG_GUID
Address: Operational Base + offset (0x003c)
User ID Register
Bit Attr Reset Value Description
UserID
31:0 RW 0x00000000
Application-programmable ID field.

USBOTG_GSNPSID
Address: Operational Base + offset (0x0040)
Core ID Register
Bit Attr Reset Value Description
CoreID
31:0 RO 0x00004f54
Release number of the core being used

USBOTG_GHWCFG1
Address: Operational Base + offset (0x0044)
User HW Config1 Register
Bit Attr Reset Value Description
epdir
Endpoint Direction
This 32-bit field uses two bits per endpoint to
determine the endpoint direction.
Endpoint
Bits [31:30]: Endpoint 15 direction
Bits [29:28]: Endpoint 14 direction
...
31:0 RO 0x00000000
Bits [3:2]: Endpoint 1 direction
Bits[1:0]: Endpoint 0 direction (always
BIDIR)
Direction
2'b00: BIDIR (IN and OUT) endpoint
2'b01: IN endpoint
2'b10: OUT endpoint
2'b11: Reserved

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USBOTG_GHWCFG2
Address: Operational Base + offset (0x0048)
User HW Config2 Register
Bit Attr Reset Value Description
OTG_ENABLE_IC_USB
IC_USB mode specified for mode of operation
(parameter OTG_ENABLE_IC_USB). To
31 RO 0x0
choose IC_USB_MODE, both
OTG_FSPHY_INTERFACE and
OTG_ENABLE_IC_USB must be 1.
TknQDepth
Device Mode IN Token Sequence Learning
30:26 RO 0x00
Queue Depth
Range: 0-30
PTxQDepth
Host Mode Periodic Request Queue Depth
2'b00: 2
25:24 RO 0x0
2'b01: 4
2'b10: 8
Others: Reserved
NPTxQDepth
Non-periodic Request Queue Depth
2'b00: 2
23:22 RO 0x0
2'b01: 4
2'b10: 8
Others: Reserved
21 RO 0x0 reserved
MultiProcIntrpt
Multi-Processor Interrupt Enabled
20 RO 0x0
1'b0: No
1'b1: Yes
DynFifoSizing
Dynamic FIFO Sizing Enabled
19 RO 0x0
1'b0: No
1'b1: Yes
PerioSupport
Periodic OUT Channels Supported in Host
18 RO 0x0 Mode
1'b0: No
1'b1: Yes
NumHstChnl
Number of Host Channels
Indicates the number of host channels
17:14 RO 0x0
supported by the core in Host mode. The
range of this field is 0-15: 0 specifies 1
channel, 15 specifies 16 channels.
NumDevEps
Number of Device Endpoints
Indicates the number of device endpoints
13:10 RO 0x0
supported by the core in Device mode in
addition to control endpoint 0. The range of
this field is 1-15.

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Bit Attr Reset Value Description

FSPhyType
Full-Speed PHY Interface Type
2'b00: Full-speed interface not supported
9:8 RO 0x0
2'b01: Dedicated full-speed interface
2'b10: FS pins shared with UTMI+ pins
2'b11: FS pins shared with ULPI pins
HSPhyType
High-Speed PHY Interface Type
2'b00: High-Speed interface not supported
7:6 RO 0x0
2'b01: UTMI+
2'b10: ULPI
2'b11: UTMI+ and ULPI
SingPnt
Point-to-Point
1'b0: Multi-point application (hub and split
5 RO 0x0
support)
1'b1: Single-point application (no hub and no
split support)
OtgArch
Architecture
2'b00: Slave-Only
4:3 RO 0x0
2'b01: External DMA
2'b10: Internal DMA
Others: Reserved
OtgMode
Mode of Operation
3'b000: HNP- and SRP-Capable OTG (Host
and Device)
3'b001: SRP-Capable OTG (Host and Device)
3'b010: Non-HNP and Non-SRP Capable OTG
2:0 RO 0x0
(Host and Device)
3'b011: SRP-Capable Device
3'b100: Non-OTG Device
3'b101: SRP-Capable Host
3'b110: Non-OTG Host
Others: Reserved

USBOTG_GHWCFG3
Address: Operational Base + offset (0x004c)
User HW Config3 Register
Bit Attr Reset Value Description
DfifoDepth
DFIFO Depth
31:16 RO 0x0000 This value is in terms of 32-bit words.
Minimum value is 32
Maximum value is 32,768
OTG_ENABLE_LPM
15 RO 0x0 LPM mode specified for Mode of Operation
(parameter OTG_ENABLE_LPM).

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Bit Attr Reset Value Description

OTG_BC_SUPPORT
This bit indicates the HS OTG controller
14 RO 0x0 support for Battery Charger.
1'b0: No Battery Charger Support
1'b1: Battery Charger support present.
OTG_ENABLE_HSIC
HSIC mode specified for Mode of Operation
(parameter OTG_ENABLE_HSIC).
13 RO 0x0 Value Range: 0-1
1'b1: HSIC-capable with shared UTMI PHY
interface
1'b0: Non-HSIC-capable
OTG_ADP_SUPPORT
This bit indicates whether ADP logic is present
within or external to the HS OTG
controller
12 RO 0x0
1'b0: No ADP logic present with HSOTG
controller
1'b1: ADP logic is present along with HSOTG
controller.
RstType
Reset Style for Clocked always Blocks in RTL
11 RO 0x0
1'b0: Asynchronous reset is used in the core
1'b1: Synchronous reset is used in the core
OptFeature
Optional Features Removed
Indicates whether the User ID register, GPIO
interface ports, and SOF toggle and counter
10 RO 0x0 ports were removed for gate count
optimization by enabling Remove Optional
Features?
1'b0: No
1'b1: Yes
VndctlSupt
Vendor Control Interface Support
9 RO 0x0 1'b0: Vendor Control Interface is not
available on the core.
1'b1: Vendor Control Interface is available.
I2CIntSel
I2C Selection
8 RO 0x0 1'b0: I2C Interface is not available on the
core.
1'b1: I2C Interface is available on the core.
OtgEn
OTG Function Enabled
The application uses this bit to indicate the
7 RO 0x0
Otg core's OTG capabilities.
1'b0: Not OTG capable
1'b1: OTG Capable

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Bit Attr Reset Value Description

PktSizeWidth
Width of Packet Size Counters
3'b000: 4 bits
3'b001: 5 bits
3'b010: 6 bits
6:4 RO 0x0
3'b011: 7 bits
3'b100: 8 bits
3'b101: 9 bits
3'b110: 10 bits
Others: Reserved
XferSizeWidth
Width of Transfer Size Counters
4'b0000: 11 bits
3:0 RO 0x0 4'b0001: 12 bits
...
4'b1000: 19 bits
Others: Reserved

USBOTG_GHWCFG4
Address: Operational Base + offset (0x0050)
User HW Config4 Register
Bit Attr Reset Value Description
SGDMA
31 RO 0x0 Scatter/Gather DMA
1'b1: Dynamic configuration
SGDMACon
Scatter/Gather DMA configuration
30 RO 0x0
1'b0: Non-Scatter/Gather DMA configuration
1'b1: Scatter/Gather DMA configuration
INEps
Number of Device Mode IN Endpoints
Including Control Endpoint
Range 0 -15
29:26 RO 0x0
0:1 IN Endpoint
1:2 IN Endpoints
....
15:16 IN Endpoints
DedFifoMode
Enable Dedicated Transmit FIFO for device IN
Endpoints
25 RW 0x0 1'b0: Dedicated Transmit FIFO Operation not
enabled.
1'b1: Dedicated Transmit FIFO Operation
enabled.
SessEndFltr
session_end Filter Enabled
24 RW 0x0
1'b0: No filter
1'b1: Filter

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Bit Attr Reset Value Description

BValidFltr
"b_valid" Filter Enabled
23 RW 0x0
1'b0: No filter
1'b1: Filter
AValidFltr
"a_valid" Filter Enabled
22 RO 0x0
1'b0: No filter
1'b1: Filter
VBusValidFltr
"vbus_valid" Filter Enabled
21 RO 0x0
1'b0: No filter
1'b1: Filter
IddgFltr
"iddig" Filter Enable
20 RO 0x0
1'b0: No filter
1'b1: Filter
NumCtlEps
Number of Device Mode Control Endpoints in
19:16 RO 0x0
Addition to Endpoint
Range: 0-15
PhyDataWidth
UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper
Data Width
When a ULPI PHY is used, an internal wrapper
15:14 RO 0x0 converts ULPI to UTMI+.
2'b00: 8 bits
2'b01: 16 bits
2'b10: 8/16 bits, software selectable
Others: Reserved
13:7 RO 0x0 reserved
EnHiber
Enable Hibernation
6 RO 0x0
1'b0: Hibernation feature not enabled
1'b1: Hibernation feature enabled
AhbFreq
Minimum AHB Frequency Less Than 60 MHz
5 RO 0x0
1'b0: No
1'b1: Yes
EnParPwrDown
Enable Partial Power Down
4 RO 0x0
1'b0: Partial Power Down Not Enabled
1'b1: Partial Power Down Enabled
NumDevPerioEps
3:0 RO 0x0 Number of Device Mode Periodic IN Endpoints
Range: 0-15

USBOTG_GLPMCFG
Address: Operational Base + offset (0x0054)
Core LPM Configuration Register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

InvSelHsic
HSIC-Invert Select HSIC
The application uses this bit to control the Otg
core HSIC enable/disable. This bit overrides
and functionally inverts the if_sel_hsic input
port signal. If the core operates as
non-HSIC-capable, it can only connect to
non-HSIC-capable PHYs. If the core operates
as HSIC-capable, it can only connect to HSIC
capable PHYs. If the if_sel_hsic input signal
31 RW 0x0 is1:
1'b1: HSIC capability is not enabled.
1'b0: HSIC capability is enabled,
If InvSelHsic = 1'b0: HSIC capability is
enabled. If the if_sel_hsic input signal is 0:
1'b1: HSIC capability is enabled,
1'b0: HSIC capability is not enabled.
This bit is writable only if an HSIC mode was
specified for Mode of Operation (parameter
OTG_ENABLE_HSIC). This bit is valid only if
OTG_ENABLE_HSIC is enabled.
HSICCon
HSIC-Connect
The application must use this bit to initiate the
HSIC Attach sequence. Host Mode: Once this
bit is set, the host core configures to drive the
HSIC Idle state (STROBE = 1 & DATA = 0) on
the bus. It then waits for the device to initiate
30 RW 0x0
the Connect sequence. Device Mode: Once
this bit is set, the device core waits for the
HSIC Idle line state on the bus. Upon receiving
the Idle line state, it initiates the HSIC
Connect sequence. This bit is valid only if
OTG_ENABLE_HSIC is 1, if_sel_hsic = 1 and
InvSelHSIC is 0. Otherwise, it is read-only.
29:28 RO 0x0 reserved
LPM_RetryCnt_Sts
LPM Retry Count Status
27:25 RO 0x0
Number of LPM host retries remaining to be
transmitted for the current LPM sequence.
SndLPM
Send LPM Transaction
Host Mode: When the application software
sets this bit, an LPM transaction containing
two tokens, EXT and LPM, is sent. The
24 RW 0x0 hardware clears this bit once a valid response
(STALL, NYET, or ACK) is received from the
device or the core has finished transmitting
the programmed number of LPM retries. Note:
This bit must only be set when the host is
connected to a local port.

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Bit Attr Reset Value Description

LPM_Retry_Cnt
LPM Retry Count
When the device gives an ERROR response,
23:21 R/WSC 0x0
this is the number of additional LPM retries
that the host performs until a valid device
response (STALL, NYET, or ACK) is received.
LPM_Chnl_Indx
LPM Channel Index
The channel number on which the LPM
transaction must be applied while sending an
20:17 RW 0x0 LPM transaction to the local device. Based on
the LPM channel index, the core automatically
inserts the device address and endpoint
number programmed in the corresponding
channel into the LPM transaction.
L1ResumeOK
Sleep State Resume OK
Indicates that the application or host can start
a resume from the Sleep state. This bit is valid
in the LPM Sleep (L1) state. It is set in Sleep
16 RO 0x0 mode after a delay of 50 us (TL1Residency).
The bit is reset when SlpSts is 0
1'b1: The application/core can start resume
from the Sleep state
1'b0: The application/core cannot start
resume from the Sleep state

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Bit Attr Reset Value Description

SlpSts
Port Sleep Status
Device Mode: This bit is set as long as a Sleep
condition is present on the USB bus. The core
enters the Sleep state when an ACK response
is sent to an LPM transaction and the timer
TL1TokenRetry. has expired. To stop the PHY
clock, the application must set the Port Clock
Stop bit, which asserts the PHY Suspend input
pin. The application must rely on SlpSts and
not ACK in CoreL1Res to confirm transition
into sleep.
The core comes out of sleep:
When there is any activity on the USB
line_state
When the application writes to the Remote
Wakeup Signaling bit in the Device Control
register (DCTL.RmtWkUpSig) or when the
15 RO 0x0 application resets or soft-disconnects the
device.
Host Mode: The host transitions to the Sleep
(L1) state as a sideeffect of a successful LPM
transaction by the core to the local port with
an ACK response from the device. The read
value of this bit reflects the port's current
sleep status. The core clears this bit after:
The core detects a remote L1 Wakeup signal
The application sets the Port Reset bit or the
Port L1Resume bit in the HPRT register or
The application sets the L1Resume/ Remote
Wakeup Detected Interrupt bit or Disconnect
Detected Interrupt bit in the Core Interrupt
register (GINTSTS.L1WkUpInt or
GINTSTS.DisconnInt, respectively).
Values:
1'b0: Core not in L1
1'b1: Core in L1
CoreL1Res
LPM Response
Device Mode: The core's response to the
received LPM transaction is reflected in these
two bits. Host Mode: The handshake response
14:13 RO 0x0 received from the local device for LPM
transaction.
2'b11: ACK
2'b10: NYET
2'b01: STALL
2'b00: ERROR (No handshake response)

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Bit Attr Reset Value Description

HIRD_Thres
HIRD Threshold
Device Mode: The core asserts L1SuspendM to
put the PHY into Deep Low-Power mode in L1
when the HIRD value is greater than or equal
to the value defined in this field
(GLPMCFG.HIRD_Thres[3:0]), and
HIRD_Thres[4] is set to 1'b1.
Host Mode: The core asserts L1SuspendM to
put the PHY into Deep Low-Power mode in L1
when HIRD_Thres[4] is set to 1'b1.
HIRD_Thres[3:0] specifies the time for which
resume signaling is to be reflected by the host
TL1HubDrvResume2) on the USB when it
detects device-initiated resume. HIRD_Thres
must not be programmed with a value greater
than 4'b1100 in Host mode, because this
12:8 RW 0x00 exceeds maximum TL1HubDrvResume2.
No HIRD_Thres[3:0] resume time(us)
1 4'b0000 60
2 4'b0001 135
3 4'b0010 210
4 4'b0011 285
5 4'b0100 360
6 4'b0101 435
7 4'b0110 510
8 4'b0111 585
9 4'b1000 660
10 4'b1001 735
11 4'b1010 810
12 4'b1011 885
13 4'b1100 960
14 4'b1101 invalid
15 4'b1110 invalid
16 4'b1111 invalid

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Bit Attr Reset Value Description

EnblSlpM
Enable utmi_sleep_n
For ULPI interface: The application uses this
bit to write to the function control [7] in the L1
state, to enable the PHY to go into Low Power
mode. For the host, this bit is valid only in
Local Device mode.
1'b0: Writes to the ULPI Function Control Bit
[7] are disabled.
1'b1: The core is enabled to write to the ULPI
Function Control Bit [7], which enables the
PHY to enter Low-Power mode.
Note: When a ULPI interface is configured,
enabling this bit results in a write to Bit 7 of
the ULPI Function Control register. The ULPI
7 RW 0x0 PHY supports writing to this bit, and in the L1
state asserts SleepM when
utmi_l1_suspend_n cannot be asserted.
When a ULPI interface is configured, this bit
must always be set if you are using the ULPI
PHY. Note: For ULPI interface, do not clear this
bit during the resume. For all other interfaces:
The application uses this bit to control
utmi_sleep_n assertion to the PHY in the L1
state. For the host, this bit is valid only in
Local Device mode.
1'b0: utmi_sleep_n assertion from the core is
not transferred to the external PHY.
1'b1: utmi_sleep_n assertion from the core is
transferred to the external PHY when
utmi_l1_suspend_n cannot be asserted.
bRemoteWake
RemoteWakeEnable
Host Mode: The remote wakeup value to be
sent in the LPM transaction's wIndex field.
6 RW 0x0
Device Mode: This field is updated with the
received bRemoteWake LPM token's
bmAttribute when an ACK/NYET/STALL
response is sent to an LPM transaction.

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Bit Attr Reset Value Description

HIRD
Host-Initiated Resume Duration
Host Mode: The value of HIRD to be sent in an
LPM transaction. This value is also used to
initiate resume for a duration .TL1HubDrvResume1
for host initiated resume. Device Mode: This
field is updated with the Received LPM Token
HIRD bmAttribute when an ACK/NYET/STALL
response is sent to an LPM transaction
Sl. No HIRD[3:0] THIRD (us)
1 4'b0000 50
2 4'b0001 125
3 4'b0010 200
5:2 RW 0x0
4 4'b0011 275
5 4'b0100 350
6 4'b0101 425
7 4'b0110 500
8 4'b0111 575
9 4'b1000 650
10 4'b1001 725
11 4'b1010 800
12 4'b1011 875
13 4'b1100 950
14 4'b1101 1025
15 4'b1110 1100
16 4'b1111 1175
AppL1Res
LPM response programmed by application
Handshake response to LPM token
pre-programmed by device application
software. The response depends on
GLPMCFG.LPMCap. If GLPMCFG.LPMCap is
1'b0, the core always responds with a NYET. If
GLPMCFG.LPMCap is 1'b1, the core responds
as follows:
1'b1: ACK. Even though an ACK is
pre-programmed, the core responds with an
ACK only on a successful LPM transaction. The
1 RW 0x0
LPM transaction is successful if: There are no
PID/CRC5 errors in both the EXT token and
the LPM token (else ERROR); A valid
bLinkState = 0001B (L1) is received in the
LPM transaction (else STALL); No data is
pending in the Transmit queue (else NYET)
1'b0: NYET. The pre-programmed software bit
is overridden for response to LPM token when:
(1) The received bLinkState is not L1 (STALL
response); (2) An error is detected in either of
the LPM token packets due to corruption
(ERROR response).

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Bit Attr Reset Value Description

LPMCap
LPM-Capable
The application uses this bit to control the OTG
core LPM capabilities. If the core operates as a
non-LPM-capable host, it cannot request the
connected device/hub to activate LPM mode.
If the core operates as a non-LPM-capable
0 RW 0x0 device, it cannot respond to any LPM
transactions.
1'b0: LPM capability is not enabled.
1'b1: LPM capability is enabled.
This bit is writable only if an LPM mode was
specified for Mode of Operation (parameter
OTG_ENABLE_LPM). Otherwise, reads return
0.

USBOTG_GPWRDN
Address: Operational Base + offset (0x0058)
Global Power Down Register
Bit Attr Reset Value Description
31:29 RO 0x0 reserved
MultValIdBC
Multi Valued ID pin
Battery Charger ACA inputs in the following
order:
Bit 26 - rid_float.
Bit 25 - rid_gnd
28:24 RO 0x00 Bit 24 - rid_a
Bit 23 - rid_b
Bit 22 - rid_c
These bits are present only if
OTG_BC_SUPPORT = 1.
Otherwise, these bits are reserved and will
read 5'h0.
ADPInt
23 W1C 0x0 ADP Interupt
This bit is set whenever there is a ADP event.
BSessVld
B Session Valid
This field reflects the B session valid status
signal from the PHY.
22 RO 0x0
1'b0: B-Valid is 0.
1'b1: B-Valid is 1.
This bit is valid only when GPWRDN.PMUActv
is 1.

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Bit Attr Reset Value Description

IDDIG
This bit indicates the status of the signal
IDDIG. The application must read this bit after
receiving GPWRDN.StsChngInt and decode
based on the previous value stored by the
21 RO 0x0
application. Indicates the current mode.
1'b1: Device mode
1'b0: Host mode
This bit is valid only when GPWRDN.PMUActv
is 1.
LineState
This field indicates the current linestate on
USB as seen by the PMU module.
2'b00: DM = 0, DP = 0.
20:19 RO 0x0 2'b01: DM = 0, DP = 1.
2'b10: DM = 1, DP = 0.
2'b11: Not-defined.
This bit is valid only when GPWRDN.PMUActv
is 1.
StsChngIntMsk
18 RW 0x0
Mask For StsChng Interrupt
StsChngInt
This field indicates a status change in either
the IDDIG or BSessVld signal.
1'b0: No Status change
1'b1: status change detected
17 W1C 0x0
After receiving this interrupt the application
should read the GPWRDN register and
interpret the change in IDDIG or BSesVld with
respect to the previous value stored by the
application.
SRPDetectMsk
16 RW 0x0
Mask For SRPDetect Interrupt
SRPDetect
This field indicates that SRP has been detected
by the PMU. This field generates an interrupt.
After detecting SRP during hibernation the
15 W1C 0x0 application should not restore the core. The
application should get into the initialization
process.
1'b0: SRP not detected
1'b1: SRP detected
ConnDetMsk
Mask for ConnectDet interrupt
14 RW 0x0
This bit is valid only when OTG_EN_PWROPT
= 2.
ConnectDet
This field indicates that a new connect has
been detected
13 W1C 0x0 1'b0: Connect not detected
1'b1: Connect detected
This bit is valid only when OTG_EN_PWROPT
= 2.

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Bit Attr Reset Value Description

DisconnectDetectMsk
Mask For DisconnectDetect Interrupt
12 RW 0x0
This bit is valid only when OTG_EN_PWROPT
= 2.
DisconnectDetect
This field indicates that Disconnect has been
detected by the PMU. This field generates an
interrupt. After detecting disconnect during
hibernation the application must not restore
11 W1C 0x0 the core, but instead start the initialization
process.
1'b0: Disconnect not detected
1'b1: Disconnect detected
This bit is valid only when OTG_EN_PWROPT
= 2.
ResetDetMsk
10 RW 0x0 Mask For ResetDetected interrupt.This bit is
valid only when OTG_EN_PWROPT = 2.
ResetDetected
This field indicates that Reset has been
detected by the PMU module. This field
generates an interrupt.
9 W1C 0x0
1'b0: Reset Not Detected
1'b1: Reset Detected
This bit is valid only when OTG_EN_PWROPT
= 2.
LineStageChangeMsk
Mask For LineStateChange interrupt
8 RW 0x0
This bit is valid only when OTG_EN_PWROPT
= 2.
LnStsChng
Line State Change
This interrupt is asserted when there is a
Linestate Change detected by the PMU. The
application should read GPWRDN.Linestate to
7 W1C 0x0 determine the current linestate on USB.
1'b0: No LineState change on USB
1'b1: LineState change on USB
This bit is valid only when GPWRDN.PMUActv
is 1.This bit is valid only when
OTG_EN_PWROPT = 2.
DisableVBUS
The application should program this bit if
HPRT0.PrtPwr was programmed to 0 before
entering Hibernation. This is to indicate PMU
6 RW 0x0
whether session was ended before entering
Hibernation.
1'b0: HPRT0.PrtPwr was not programed to 0.
1'b1: HPRT0.PrtPwr was programmed to 0.

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Bit Attr Reset Value Description

PwrDnSwtch
Power Down Switch
This bit indicates to the OTG core VDD switch
is in ON/OFF state
5 RW 0x0
1'b0: OTG is in ON state
1'b1: OTG is in OFF state
Note: This bit must not be written to during
normal mode of operation.
PwrDnRst_n
Power Down ResetN
The application must program this bit to reset
the DWC OTG core during the Hibernation exit
process or during ADP when powering up the
4 RW 0x0 core (in case the DWC OTG core was powered
off during ADP process).
1'b1: OTG is in normal operation
1'b0: reset OTG
Note: This bit must not be written to during
normal mode of operation.
PwrDnClmp
Power Down Clamp
The application must program this bit to
enable or disable the clamps to all the outputs
3 RW 0x0
of the DWC OTG core module to prevent the
corruption of other active logic.
1'b0: Disable PMU power clamp
1'b1: Enable PMU power clamp
Restore
The application should program this bit to
enable or disable restore mode from the PMU
module.
2 RW 0x0 1'b0: OTG in normal mode of operation
1'b1: OTG in restore mode
Note: This bit must not be written to during
normal mode of operation. This bit is valid
only when OTG_EN_PWROPT = 2.
PMUActv
PMU Active
This is bit is to enable or disable the PMU logic.
1 RW 0x0 1'b0: Disable PMU module
1'b1: Enable PMU module
Note: This bit must not be written to during
normal mode of operation.

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Bit Attr Reset Value Description

PMUIntSel
PMU Interrupt Select
When the hibernation functionality is selected
using the configuration option
OTG_EN_PWR_OPT = 2, a write to this bit with
1'b1 enables the PMU to generate interrupts
to the application. During this state all
0 RW 0x0 interrupts from the core module are blocked
to the application. Note: This bit must be set
to 1'b1 before the core is put into hibernation
1'b0: Internal OTG_core interrupt is selected
1'b1: the external OTG_pmu interrupt is
selected
Note: This bit must not be written to during
normal mode of operation.

USBOTG_GDFIFOCFG
Address: Operational Base + offset (0x005c)
Global DFIFO Software Config Register
Bit Attr Reset Value Description
EPInfoBaseAddr
31:16 RW 0x0000 This field provides the start address of the EP
info controller.
GDFIFOCfg
This field is for dynamic programming of the
DFIFO Size. This value takes effect
15:0 RW 0x0000 only when the application programs a
non-zero value to this register. The core does
not have any corrective logic if the FIFO sizes
are programmed incorrectly.

USBOTG_GADPCTL
Address: Operational Base + offset (0x0060)
ADP Timer,Control and Status Register
Bit Attr Reset Value Description
31:29 RO 0x0 reserved
AR
Access Request
2'b00 Read/Write Valid (updated by the
28:27 R/WSC 0x0 core)
2'b01 Read
2'b10 Write
2'b11 Reserved
AdpTmoutMsk
ADP Timeout Interrupt Mask
26 RW 0x0 When this bit is set, it unmasks the interrupt
because of AdpTmoutInt. This bit is valid only
if OTG_Ver = 1'b1(GOTGCTL[20]).

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Bit Attr Reset Value Description

AdpSnsIntMsk
ADP Sense Interrupt Mask
25 RW 0x0 When this bit is set, it unmasks the interrupt
due to AdpSnsInt. This bit is valid only if
OTG_Ver = 1'b1(GOTGCTL[20]).
AdpPrbIntMsk
ADP Probe Interrupt Mask
24 RW 0x0 When this bit is set, it unmasks the interrupt
due to AdpPrbInt.This bit is valid only if
OTG_Ver = 1'b1(GOTGCTL[20]).
AdpTmoutInt
ADP Timeout Interrupt
This bit is relevant only for an ADP probe.
When this bit is set, it means that the
ramp time has completed (GADPCTL.RTIM has
23 W1C 0x0
reached its terminal value of
0x7FF). This is a debug feature that allows
software to read the ramp time after
each cycle. This bit is valid only if OTG_Ver =
1'b1.
AdpSnsInt
ADP Sense Interrupt
When this bit is set, it means that the VBUS
22 W1C 0x0
voltage is greater than VadpSns
value or VadpSns is reached. This bit is valid
only if OTG_Ver = 1'b1 (GOTGCTL[20]).
AdpPrbInt
ADP Probe Interrupt
When this bit is set, it means that the VBUS
21 W1C 0x0
voltage is greater than VadpPrb or
VadpPrb is reached. This bit is valid only if
OTG_Ver = 1'b1 (GOTGCTL[20]).
ADPEn
ADP Enable
When set, the core performs either ADP
20 RW 0x0
probing or sensing based on EnaPrb or
EnaSns. This bit is valid only if OTG_Ver =
1'b1 (GOTGCTL[20]).
ADPRes
ADP Reset
When set, ADP controller is reset. This bit is
19 R/WSC 0x0
auto-cleared after the reset procedure is
complete in ADP controller.This bit is valid
only if OTG_Ver = 1'b1 (GOTGCTL[20]).
EnaSns
Enable Sense
18 RW 0x0 When programmed to 1'b1, the core performs
a sense operation. This bit is valid only if
OTG_Ver = 1'b1 (GOTGCTL[20]).

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Bit Attr Reset Value Description

EnaPrb
Enable Probe
17 RW 0x0 When programmed to 1'b1, the core performs
a probe operation. This bit is valid only if
OTG_Ver = 1'b1 (GOTGCTL[20]).
RTIM
RAMP TIME
These bits capture the latest time it took for
VBUS to ramp from VADP_SINK to VADP_PRB.
The bits are defined in units of 32 kHz clock
cycles as follows:
3'b000 - 1 cycles
3'b001 - 2 cycles
3'b010 - 3 cycles
16:6 RO 0x000
and so on till
0x7FF - 2048 cycles
A time of 1024 cycles at 32 kHz corresponds
to a time of 32 msec.
(Note for scaledown ramp_timeout =
prb_delta == 2'b00 => 200 cycles
prb_delta == 2'b01 => 100 cycles
prb_delta == 2'b01 => 50 cycles
prb_delta == 2'b01 => 25 cycles.)
PrbPer
Probe Period
These bits sets the TadpPrd as follows:
2'b00 - 0.625 to 0.925 sec (typical 0.775
sec)
2'b01 - 1.25 to 1.85 sec (typical 1.55 sec)
5:4 RW 0x0 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec)
2'b11 - Reserved
(PRB_PER is also scaledown
prb_per== 2'b00 => 400 ADP clocks
prb_per== 2'b01 => 600 ADP clocks
prb_per== 2'b10 => 800 ADP clocks
prb_per==2'b11 => 1000 ADP clocks)
PrbDelta
Probe Delta
These bits set the resolution for RTIM value.
The bits are defined in units of 32
kHz clock cycles as follows:
2'b00 - 1 cycles
3:2 RW 0x0
2'b01 - 2 cycles
2'b10 - 3 cycles
2'b11 - 4 cycles
For example if this value is chosen to 2'b01, it
means that RTIM increments for
every three 32Khz clock cycles.

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Bit Attr Reset Value Description

PrbDschg
Probe Discharge
These bits set the times for TadpDschg. These
bits are defined as follows:
2'b00 4 msec (Scaledown 2 32Khz clock
cycles)
1:0 RW 0x0
2'b01 8 msec (Scaledown 4 32Khz clock
cycles)
2'b10 16 msec (Scaledown 8 32Khz clock
cycles)
2'b11 32 msec (Scaledown 16 32Khz clock
cycles)

USBOTG_HPTXFSIZ
Address: Operational Base + offset (0x0100)
Host Periodic Transmit FIFO Size Register
Bit Attr Reset Value Description
PTxFSize
Host Periodic TxFIFO Depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 32,768
The power-on reset value of this register is
specified as the Largest Host Mode Periodic Tx
Data FIFO Depth (parameter
31:16 RW 0x0000 OTG_TX_HPERIO_DFIFO_DEPTH). If Enable
Dynamic FIFO Sizing? Was deselected
(parameter OTG_DFIFO_DYNAMIC = 0),
these flops are optimized, and reads return
the power-on value. If Enable Dynamic FIFO
Sizing? was selected (parameter
OTG_DFIFO_DYNAMIC = 1), you can write a
new value in this field. Programmed values
must not exceed the power-on value set .

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Bit Attr Reset Value Description

PTxFStAddr
Host Periodic TxFIFO Start Address
The power-on reset value of this register is the
sum of the Largest Rx Data FIFO
Depth and Largest Non-periodic Tx Data FIFO
Depth specified.
These parameters are:
In shared FIFO operation:
OTG_RX_DFIFO_DEPTH +
OTG_TX_NPERIO_DFIFO_DEPTH.
In dedicated FIFO mode:
15:0 RW 0x0000
OTG_RX_DFIFO_DEPTH +
OTG_TX_HNPERIO_DFIFO_DEPTH.
If Enable Dynamic FIFO Sizing? was
deselected (parameter OTG_DFIFO_DYNAMIC
= 0 ), these flops are optimized, and reads
return the power-on value.
If Enable Dynamic FIFO Sizing? was selected
(parameter OTG_DFIFO_DYNAMIC = 1), you
can write a new value in this field.
Programmed values must not exceed the
power-on value.

USBOTG_DIEPTXFn
Address: Operational Base + offset (0x0104+0x4*(n-1)), n = 1 - 15
Device Periodic Transmit FIFO-n Size Register
Bit Attr Reset Value Description
INEP1TxFDep
IN Endpoint TxFIFO Depth
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 32,768
The power-on reset value of this register is
specified as the Largest IN Endpoint FIFO
number Depth (parameter
OTG_TX_DINEP_DFIFO_DEPTH_n)(0 < n <=
15).
31:16 RW 0x0000
If Enable Dynamic FIFO Sizing? was
deselected (parameter
OTG_DFIFO_DYNAMIC = 0), these flops are
optimized, and reads return the
Power-on value.
If Enable Dynamic FIFO Sizing? was selected
(parameter OTG_DFIFO_DYNAMIC = 1), you
can write a new value in this field.
Programmed values must not exceed the
Power-on value .

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Bit Attr Reset Value Description

INEP1TxFStAddr
IN Endpoint FIFO1 Transmit RAM Start
Address
This field contains the memory start address
for IN endpoint Transmit FIFOn
(0 < n <= 15). The power-on reset value of
this register is specified as the Largest Rx
Data FIFO Depth (parameter
OTG_RX_DFIFO_DEPTH).
OTG_RX_DFIFO_DEPTH + SUM 0 to n-1
(OTG_DINEP_TXFIFO_DEPTH_n)
For example start address of IN endpoint FIFO
1 is OTG_RX_DFIFO_DEPTH +
OTG_DINEP_TXFIFO_DEPTH_0. The start
15:0 RW 0x0000
address of IN endpoint FIFO 2 is
OTG_RX_DFIFO_DEPTH +
OTG_DINEP_TXFIFO_DEPTH_0 +
OTG_DINEP_TXFIFO_DEPTH_1. If Enable
Dynamic FIFO Sizing? was deselected
(parameter OTG_DFIFO_DYNAMIC = 0),
these flops are optimized, and reads return
the power-on value. If Enable Dynamic FIFO
Sizing? was selected (parameter
OTG_DFIFO_DYNAMIC = 1), and you have
programmed a new value for RxFIFO depth,
you can write that value in this field.
Programmed values must not exceed the
power-on value set .

USBOTG_HCFG
Address: Operational Base + offset (0x0400)
Host Configuration Register
Bit Attr Reset Value Description
31:27 RO 0x0 reserved
PerSchedEna
Enable Periodic Scheduling
Applicable in Scatter/Gather DMA mode only.
Enables periodic scheduling within the core.
Initially, the bit is reset. The core will not
process any periodic channels. As soon as this
bit is set, the core will get ready to start
scheduling periodic channels and sets
HCFG.PerSchedStat. The setting of
26 RW 0x0
HCFG.PerSchedStat indicates the core has
enabled periodic scheduling. Once
HCFG.PerSchedEna is set, the application is
not supposed to again reset the bit unless
HCFG.PerSchedStat is set. As soon as this bit
is reset, the core will get ready to stop
scheduling periodic channels and resets
HCFG.PerSchedStat. In non-Scatter/Gather
DMA mode, this bit is reserved.

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Bit Attr Reset Value Description

FrListEn
Frame List Entries
25:24 RW 0x0 The value in the register specifies the number
of entries in the Frame list. This field is valid
only in Scatter/Gather DMA mode.
DescDMA
Enable Scatter/gather DMA in Host mode
When the Scatter/Gather DMA option selected
during configuration of the RTL, theapplication
can set this bit during initialization to enable
the Scatter/Gather DMA operation. NOTE:
This bit must be modified only once after a
reset. The following combinations are
available for programming:
23 RW 0x0 GAHBCFG.DMAEn=0, HCFG.DescDMA=0 =>
Slave mode
GAHBCFG.DMAEn=0, HCFG.DescDMA=1 =>
Invalid
GAHBCFG.DMAEn=1, HCFG.DescDMA=0 =>
Buffered DMA mode
GAHBCFG.DMAEn=1, HCFG.DescDMA=1 =>
Scatter/Gather DMA mode
In non-Scatter/Gather DMA mode, this bit is
reserved.
22:16 RO 0x0 reserved
ResValid
Resume Validation Period
This field is effective only when
HCFG.Ena32KHzS is set. It controls the
15:8 RW 0x00
resume period when the core resumes from
suspend. The core counts the ResValid
number of clock cycles to detect a valid
resume when this is set.
Ena32KHzS
Enable 32-KHz Suspend Mode
This bit can only be set if the USB 1.1
Full-Speed Serial Transceiver Interface has
been selected. If USB 1.1 Full-Speed Serial
7 RW 0x0 Transceiver Interface has not been selected,
this bit must be zero. When the USB 1.1
Full-Speed Serial Transceiver Interface is
chosen and this bit is set, the core expects the
48-MHz PHY clock to be switched to 32 KHz
during a suspend.
6:3 RO 0x0 reserved

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Bit Attr Reset Value Description

FSLSSupp
FS- and LS-Only Support
The application uses this bit to control the core
enumeration speed. Using this bit, the
application can make the core enumerate as a
FS host, even if the connected device supports
2 RW 0x0
HS traffic. Do not make changes to this field
after initial programming.
1'b0: HS/FS/LS, based on the maximum
speed supported by the connected device
1'b1: FS/LS-only, even if the connected
device can support HS
FSLSPclkSel
FS/LS PHY Clock Select
1:0 RW 0x0 2'b00: PHY clock is running at 30/60 MHz
2'b01: PHY clock is running at 48 MHz
Others: Reserved

USBOTG_HFIR
Address: Operational Base + offset (0x0404)
Host Frame Interval Register
Bit Attr Reset Value Description
31:16 RO 0x0 reserved
FrInt
Frame Interval
The value that the application programs to
this field specifies the interval between two
consecutive SOFs (FS) or micro-SOFs (HS) or
Keep-Alive tokens (HS). This field contains the
number of PHY clocks that constitute the
required frame interval. The default value set
in this field for a FS operation when the PHY
clock frequency is 60 MHz. The application can
15:0 RW 0x0000 write a value to this register only after the Port
Enable bit of the Host Port Control and Status
register (HPRT.PrtEnaPort) has been set. If no
value is programmed, the core calculates the
value based on the PHY clock specified in the
FS/LS PHY Clock Select field of the Host
Configuration register (HCFG.FSLSPclkSel).
Do not change the value of this field after the
initial configuration.
125 us * (PHY clock frequency for HS)
1 ms * (PHY clock frequency for FS/LS)

USBOTG_HFNUM
Address: Operational Base + offset (0x0408)
Host Frame Number/Frame Time Remaining Register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

FrRem
Frame Time Remaining
Indicates the amount of time remaining in the
current micro-frame (HS) or frame
31:16 RO 0x0000 (FS/LS), in terms of PHY clocks. This field
decrements on each PHY clock. When it
reaches zero, this field is reloaded with the
value in the Frame Interval register and a new
SOF is transmitted on the USB.
FrNum
Frame Number
This field increments when a new SOF is
transmitted on the USB, and is reset to 0 when
15:0 RO 0xffff it reaches 16'h3FFF. This field is writable only
if Remove Optional Features? was not
selected (OTG_RM_OTG_FEATURES = 0).
Otherwise, reads return the frame number
value.

USBOTG_HPTXSTS
Address: Operational Base + offset (0x0410)
Host Periodic Transmit FIFO/Queue Status Register
Bit Attr Reset Value Description
PTxQTop
Top of the Periodic Transmit Request Queue
This indicates the entry in the Periodic Tx
Request Queue that is currently being
processed by the MAC. This register is used for
debugging.
Bit [31]: Odd/Even (micro)frame
1'b0: send in even (micro)frame
31:24 RO 0x00 1'b1: send in odd (micro)frame
Bits [30:27]: Channel/endpoint number
Bits [26:25]: Type
2'b00: IN/OUT
2'b01: Zero-length packet
2'b10: CSPLIT
2'b11: Disable channel command
Bit [24]: Terminate (last entry for the
selected channel/endpoint)

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Bit Attr Reset Value Description

PTxQSpcAvail
Periodic Transmit Request Queue Space
Available
Indicates the number of free locations
available to be written in the Periodic Transmit
Request Queue. This queue holds both IN and
23:16 RO 0x00 OUT requests.
8'h0: Periodic Transmit Request Queue is
full
8'h1: 1 location available
8'h2: 2 locations available
n: n locations available (0 <=n <= 16)
Others: Reserved
PTxFSpcAvail
Periodic Transmit Data FIFO Space Available
Indicates the number of free locations
available to be written to in the Periodic
TxFIFO. Values are in terms of 32-bit words
. 16'h0: Periodic TxFIFO is full
15:0 RW 0x0000
. 16'h1: 1 word available
. 16'h2: 2 words available
. 16'hn: n words available (where 0 . n .
32,768)
. 16'h8000: 32,768 words available
. Others: Reserved

USBOTG_HAINT
Address: Operational Base + offset (0x0414)
Host All Channels Interrupt Reigster
Bit Attr Reset Value Description
31:16 RO 0x0 reserved
HAINT
Channel Interrupts
One bit per channel:
15:0 RO 0x0000 Bit 0 for Channel 0
Bit 1 for Channel 1
…...
Bit 15 for Channel 15

USBOTG_HAINTMSK
Address: Operational Base + offset (0x0418)
Host All Channels Interrupt Mask Register
Bit Attr Reset Value Description
31:16 RO 0x0 reserved
HAINTMsk
Channel Interrupt Mask
15:0 RW 0x0000
One bit per channel: Bit 0 for channel 0, bit 15
for channel 15

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USBOTG_HPRT
Address: Operational Base + offset (0x0440)
Host Port Control and Status Register
Bit Attr Reset Value Description
31:19 RO 0x0 reserved
PrtSpd
Port Speed
Indicates the speed of the device attached to
this port.
18:17 RO 0x0
2'b00: High speed
2'b01: Full speed
2'b10: Low speed
2'b11: Reserved
PrtTstCtl
Port Test Control
The application writes a nonzero value to this
field to put the port into a Test mode,and the
corresponding pattern is signaled on the port.
4'b0000: Test mode disabled
16:13 RW 0x0
4'b0001: Test_J mode
4'b0010: Test_K mode
4'b0011: Test_SE0_NAK mode
4'b0100: Test_Packet mode
4'b0101: Test_Force_Enable
Others: Reserved
PrtPwr
Port Power
The application uses this field to control power
to this port (write 1'b1 to set to 1'b1and write
12 R/WSC 0x0
1'b0 to set to 1'b0), and the core can clear this
bit on an over current condition.
1'b0: Power off
1'b1: Power on
PrtLnSts
Port Line Status
11:10 RO 0x0 Indicates the current logic level USB data lines
Bit [10]: Logic level of D+
Bit [11]: Logic level of D
9 RO 0x0 reserved

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Bit Attr Reset Value Description

PrtRst
Port Reset
When the application sets this bit, a reset
sequence is started on this port. The
application must time the reset period and
clear this bit after the reset sequence is
complete.
1'b0: Port not in reset
1'b1: Port in reset
To start a reset on the port, the application
8 RW 0x0
must leave this bit set for at least the
minimum duration mentioned below, as
specified in the USB 2.0 specification,
Section 7.1.7.5. The application can leave it
set for another 10 ms in addition to the
required minimum duration, before clearing
the bit, even though there is no
maximum limit set by the USB standard.
High speed: 50 ms
Full speed/Low speed: 10 ms
PrtSusp
Port Suspend
The application sets this bit to put this port in
Suspend mode. The core only stops sending
SOFs when this is set. To stop the PHY clock,
the application must set the Port Clock Stop
bit, which asserts the suspended input pin of
the PHY.
The read value of this bit reflects the current
7 R/WSC 0x0 suspend status of the port. This bit is cleared
by the core after a remote wakeup signal is
detected or the application sets the Port Reset
bit or Port Resume bit in this register or the
Resume/Remote Wakeup Detected Interrupt
bit or Disconnect Detected Interrupt bit in the
Core Interrupt register (GINTSTS.WkUpInt or
GINTSTS.DisconnInt, respectively).
1'b0: Port not in Suspend mode
1'b1: Port in Suspend mode

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Bit Attr Reset Value Description

PrtRes
Port Resume
The application sets this bit to drive resume
signaling on the port. The core
continues to drive the resume signal until the
application clears this bit.
If the core detects a USB remote wakeup
sequence, as indicated by the Port
Resume/Remote Wakeup Detected Interrupt
bit of the Core Interrupt register
(GINTSTS.WkUpInt), the core starts driving
resume signaling without application
intervention and clears this bit when it detects
a disconnect condition. The read
value of this bit indicates whether the core is
currently driving resume signaling.
1'b0: No resume driven
1'b1: Resume driven
6 R/WSC 0x0
When LPM is enabled and the core is in the L1
(Sleep) state, setting this bit results in the
following behavior:
The core continues to drive the resume signal
until a pre-determined time specified in the
GLPMCFG.HIRD_Thres[3:0] field.
If the core detects a USB remote wakeup
sequence, as indicated by the Port L1
Resume/Remote L1 Wakeup Detected
Interrupt bit of the Core Interrupt register
(GINTSTS.L1WkUpInt), the core starts driving
resume signaling without application
intervention and clears this bit at the end of
the resume. The read value of this bit
indicates whether the core is currently driving
resume signaling.
1'b0: No resume driven
1'b1: Resume driven
PrtOvrCurrChng
Port Overcurrent Change
5 W1C 0x0 The core sets this bit when the status of the
Port Overcurrent Active bit (bit 4) in this
register changes.
PrtOvrCurrAct
Port Overcurrent Active
Indicates the overcurrent condition of the
4 RO 0x0
port.
1'b0: No overcurrent condition
1'b1: Overcurrent condition
PrtEnChng
Port Enable/Disable Change
3 W1C 0x0 The core sets this bit when the status of the
Port Enable bit [2] of this register
changes.

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Bit Attr Reset Value Description

PrtEna
Port Enable
A port is enabled only by the core after a reset
sequence, and is disabled by an
overcurrent condition, a disconnect condition,
or by the application clearing this bit.The
2 W1C 0x0
application cannot set this bit by a register
write. It can only clear it to disable the port.
This bit does not trigger any interrupt to the
application.
1'b0: Port disabled
1'b1: Port enabled
PrtConnDet
Port Connect Detected
The core sets this bit when a device
connection is detected to trigger an interrupt
1 W1C 0x0
to the application using the Host Port
Interrupt bit of the Core Interrupt register
(GINTSTS.PrtInt). The application must write
a 1 to this bit to clear the interrupt.
PrtConnSts
Port Connect Status
0 RO 0x0
1'b0: No device is attached to the port.
1'b1: A device is attached to the port.

USBOTG_HCCHARn
Address: Operational Base + offset (0x0500)
Host Channel-n Characteristics Register
Bit Attr Reset Value Description
ChEna
Channel Enable
When Scatter/Gather mode is enabled
1'b0: Indicates that the descriptor structure
is not yet ready.
1'b1: Indicates that the descriptor structure
31 R/WSC 0x0 and data buffer with data is setup and this
channel can access the descriptor.
When Scatter/Gather mode is disabled, This
field is set by the application and cleared by
the OTG host.
1'b0: Channel disabled
1'b1: Channel enabled
ChDis
Channel Disable
The application sets this bit to stop
transmitting/receiving data on a channel,
30 R/WSC 0x0
even before the transfer for that channel is
complete. The application must wait for the
Channel Disabled interrupt before treating the
channel as disabled.

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Bit Attr Reset Value Description

OddFrm
Odd Frame
This field is set (reset) by the application to
indicate that the OTG host must perform a
transfer in an odd (micro) frame. This field is
applicable for only periodic (isochronous and
29 RW 0x0
interrupt) transactions.
1'b0: Even (micro)frame
1'b1: Odd (micro)frame
This field is not applicable for Scatter/Gather
DMA mode and need not be programmed by
the application and is ignored by the core.
DevAddr
Device Address
28:22 RW 0x00
This field selects the specific device serving as
the data source or sink.
MC_EC
Multi Count (MC) / Error Count (EC)
When the Split Enable bit of the Host
Channel-n Split Control register
(HCSPLTn.SpltEna) is reset (1'b0), this field
indicates to the host the number of
transactions that must be executed per
micro-frame for this periodic endpoint. For
non periodic transfers, this field is used only in
DMA mode, and specifies the
number packets to be fetched for this channel
before the internal DMA engine
21:20 RW 0x0 changes arbitration.
2'b00: Reserved This field yields undefined
results.
2'b01: 1 transaction
2'b10: 2 transactions to be issued for this
endpoint per micro-frame
2'b11: 3 transactions to be issued for this
endpoint per micro-frame
When HCSPLTn.SpltEna is set (1'b1), this field
indicates the number of immediate retries to
be performed for a periodic split transactions
on transaction errors. This field must be set to
at least 2'b01.
EPType
Endpoint Type
Indicates the transfer type selected.
19:18 RW 0x0 2'b00: Control
2'b01: Isochronous
2'b10: Bulk
2'b11: Interrupt
LSpdDev
Low-Speed Device
17 RW 0x0 This field is set by the application to indicate
that this channel is communicating to a
low-speed device.

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Bit Attr Reset Value Description

16 RO 0x0 reserved
EPDir
Endpoint Direction
Indicates whether the transaction is IN or
15 RW 0x0
OUT.
1'b0: OUT
1'b1: IN
EPNum
Endpoint Number
14:11 RW 0x0
Indicates the endpoint number on the device
serving as the data source or sink.
MPS
Maximum Packet Size
10:0 RW 0x000
Indicates the maximum packet size of the
associated endpoint.

USBOTG_HCSPLTn
Address: Operational Base + offset (0x0504)
Host Channel-n Split Control Register
Bit Attr Reset Value Description
SpltEna
Split Enable
31 RW 0x0 The application sets this field to indicate that
this channel is enabled to perform split
transactions.
30:17 RO 0x0 reserved
CompSplt
Do Complete Split
16 RW 0x0 The application sets this field to request the
OTG host to perform a complete split
transaction.
XactPos
Transaction Position
This field is used to determine whether to send
all, first, middle, or last payloads with each
OUT transaction.
2'b11: All. This is the entire data payload is of
this transaction (which is less than or equal to
188 bytes).
15:14 RW 0x0
2'b10: Begin. This is the first data payload of
this transaction (which is larger than 188
bytes).
2'b00: Mid. This is the middle payload of this
transaction (which is larger than 188bytes).
2'b01: End. This is the last payload of this
transaction (which is larger than 188
bytes).
HubAddr
Hub Address
13:7 RW 0x00
This field holds the device address of the
transaction translator's hub.

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Bit Attr Reset Value Description

6:1 RO 0x0 reserved
PrtAddr
Port Address
0 RW 0x0
This field is the port number of the recipient
transaction translator.

USBOTG_HCINTn
Address: Operational Base + offset (0x0508)
Host Channel-n Interrupt Register
Bit Attr Reset Value Description
31:14 RO 0x0 reserved
DESC_LST_ROLLIntr
Descriptor rollover interrupt
This bit is valid only when Scatter/Gather DMA
13 W1C 0x0 mode is enabled. The core sets this bit when
the corresponding channel's descriptor list
rolls over. For non-Scatter/Gather DMA mode,
this bit is reserved.
XCS_XACT_ERR
Excessive Transaction Error
This bit is valid only when Scatter/Gather DMA
mode is enabled. The core sets this bit when 3
12 W1C 0x0 consecutive transaction errors occurred on
the USB bus. XCS_XACT_ERR will not be
generated for Isochronous channels. For
non-Scatter/Gather DMA mode, this bit is
reserved.
BNAIntr
BNA (Buffer Not Available) Interrupt
This bit is valid only when Scatter/Gather DMA
mode is enabled. The core generates this
11 W1C 0x0 interrupt when the descriptor accessed is not
ready for the Core to process. BNA will not be
generated for Isochronous channels. For
non-Scatter/Gather DMA mode, this bit is
reserved.
DataTglErr
Data Toggle Error
10 W1C 0x0
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core.
FrmOvrun
Frame Overrun
9 W1C 0x0
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core
BblErr
Babble Error
8 W1C 0x0
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core.

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Bit Attr Reset Value Description

XactErr
Transaction Error
Indicates one of the following errors occurred
7 W1C 0x0 on the USB: CRC check failure,
Timeout, Bit stuff error, False EOP. In
Scatter/Gather DMA mode, the interrupt due
to this bit is masked in the core.
NYET
NYET Response Received Interrupt
6 WO 0x0
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core.
ACK
ACK Response Received/Transmitted
5 W1C 0x0 Interrupt
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core.
NAK
NAK Response Received Interrupt
4 W1C 0x0
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core.
STALL
STALL Response Received Interrupt
3 W1C 0x0
In Scatter/Gather DMA mode, the interrupt
due to this bit is masked in the core.
AHBErr
AHB Error
This is generated only in DMA mode when
2 W1C 0x0 there is an AHB error during AHB
read/write.The application can read the
corresponding channel's DMA address register
to get the error address.
ChHltd
Channel Halted
In non-Scatter/Gather DMA mode, it indicates
the transfer completed abnormally either
because of any USB transaction error or in
response to disable request by the application
or because of a completed transfer. In
1 W1C 0x0
Scatter/Gather DMA mode, this indicates that
transfer completed due to any of the
following: EOL being set in descriptor, AHB
error, Excessive transaction errors, In
response to disable request by the
application, Babble, Stall, Buffer Not
Available (BNA)
XferCompl
Transfer Completed
For Scatter/Gather DMA mode, it indicates
that current descriptor processing got
0 W1C 0x0
completed with IOC bit set in its descriptor. In
non-Scatter/Gather DMA mode, it indicates
that Transfer completed normally without any
errors.

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USBOTG_HCINTMSKn
Address: Operational Base + offset (0x050c)
Host Channel-n Interrupt Mask Register
Bit Attr Reset Value Description
31:14 RO 0x0 reserved
DESC_LST_ROLLIntrMsk
Descriptor rollover interrupt Mask register
13 RW 0x0 This bit is valid only when Scatter/Gather DMA
mode is enabled. In non-Scatter/Gather DMA
mode, this bit is reserved.
12 RO 0x0 reserved
BNAIntrMsk
BNA (Buffer Not Available) Interrupt mask
register
11 RW 0x0
This bit is valid only when Scatter/Gather DMA
mode is enabled. In non-Scatter/Gather DMA
mode, this bit is reserved.
DataTglErrMsk
Data Toggle Error Mask
10 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode.
FrmOvrunMsk
Frame Overrun Mask
9 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode.
BblErrMsk
Babble Error Mask
8 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode.
XactErrMsk
Transaction Error Mask
7 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode
NyetMsk
NYET Response Received Interrupt Mask
6 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode.
AckMsk
ACK Response Received/Transmitted
5 RW 0x0 Interrupt Mask
This bit is not applicable in Scatter/Gather
DMA mode.
NakMsk
NAK Response Received Interrupt Mask
4 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode.
StallMsk
STALL Response Received Interrupt Mask
3 RW 0x0
This bit is not applicable in Scatter/Gather
DMA mode.

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Bit Attr Reset Value Description

AHBErrMsk
AHB Error Mask
2 RW 0x0
Note: This bit is only accessible when
OTG_ARCHITECTURE = 2
ChHltdMsk
1 RW 0x0
Channel Halted Mask
XferComplMsk
Transfer Completed Mask
0 RW 0x0 This bit is valid only when Scatter/Gather DMA
mode is enabled. In non-Scatter/Gather DMA
mode, this bit is reserved.

USBOTG_HCTSIZn
Address: Operational Base + offset (0x0510)
Host Channel-n Transfer Size Register
Bit Attr Reset Value Description
DoPng
Do Ping
This bit is used only for OUT transfers. Setting
31 RW 0x0 this field to 1 directs the host to do PING
protocol. Note: Do not set this bit for IN
transfers. If this bit is set for IN transfers it
disables the channel.
Pid
PID
The application programs this field with the
type of PID to use for the initial transaction.
The host maintains this field for the rest of the
30:29 RW 0x0
transfer.
2'b00: DATA0
2'b01: DATA2
2'b10: DATA1
2'b11: MDATA (non-control)/SETUP (control)
PktCnt
Packet Count
This field is programmed by the application
with the expected number of packets to be
transmitted (OUT) or received (IN).The host
decrements this count on every successful
28:19 RW 0x000
transmission or reception of an OUT/IN
packet. Once this count reaches zero, the
application is interrupted to indicate normal
completion. The width of this counter is
specified as Width of Packet Counters
(parameter OTG_PACKET_COUNT_WIDTH).

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Bit Attr Reset Value Description

XferSize
Transfer Size
For an OUT, this field is the number of data
bytes the host sends during the transfer. For
an IN, this field is the buffer size that the
application has Reserved for the transfer. The
18:0 RW 0x00000
application is expected to program this field as
an integer multiple of the maximum packet
size for IN transactions (periodic and
non-periodic). The width of this counter is
specified as Width of Transfer Size Counters
(parameter OTG_TRANS_COUNT_WIDTH).

USBOTG_HCDMAn
Address: Operational Base + offset (0x0514)
Host Channel-n DMA Address Register
Bit Attr Reset Value Description
DMAAddr
DMA Address
This field holds the start address in the
31:0 RW 0x00000000 external memory from which the data for
the endpoint must be fetched or to which it
must be stored. This register is
incremented on every AHB transaction.

USBOTG_HCDMABn
Address: Operational Base + offset (0x051c)
Host Channel-n DMA Buffer Address Register
Bit Attr Reset Value Description
HCDMABn
Holds the current buffer address
This register is updated as and when the data
31:0 RO 0x00000000 transfer for the corresponding end point is in
progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this
field is reserved.

USBOTG_DCFG
Address: Operational Base + offset (0x0800)
Device Cconfiguration Register
Bit Attr Reset Value Description
ResValid
Resume Validation Period
This field controls the period when the core
resumes from a suspend. When this bit is set,
31:26 RW 0x02
the core counts for the ResValid number of
clock cycles to detect a valid resume. This field
is effective only when DCFG.Ena32KHzSusp is
set.

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Bit Attr Reset Value Description

PerSchIntvl
Periodic Scheduling Interval
PerSchIntvl must be programmed only for
Scatter/Gather DMA mode. Description: This
field specifies the amount of time the Internal
DMA engine must allocate for fetching periodic
IN endpoint data. Based on the number of
periodic endpoints, this value must be
specified as 25,50 or 75% of (micro)frame.
When any periodic endpoints are active, the
internal DMA engine allocates the specified
25:24 RW 0x0
amount of time in fetching periodic IN
endpoint data. When no periodic endpoints
are active, then the internal DMA engine
services nonperiodic endpoints, ignoring this
field. After the specified time within a
(micro) frame, the DMA switches to fetching
for nonperiodic endpoints.
2'b00: 25% of (micro) frame.
2'b01: 50% of (micro) frame.
2'b10: 75% of (micro) frame.
2'b11: Reserved.
DescDMA
Enable Scatter/Gather DMA in Device mode
When the Scatter/Gather DMA option selected
during configuration of the RTL, the
application can set this bit during initialization
to enable the Scatter/Gather DMA
operation. NOTE: This bit must be modified
only once after a reset. The following
23 RW 0x0 combinations are available for programming:
GAHBCFG.DMAEn=0,DCFG.DescDMA=0 =>
Slave mode
GAHBCFG.DMAEn=0,DCFG.DescDMA=1 =>
Invalid
GAHBCFG.DMAEn=1,DCFG.DescDMA=0 =>
Buffered DMA mode
GAHBCFG.DMAEn=1,DCFG.DescDMA=1 =>
Scatter/Gather DMA mode
EPMisCnt
IN Endpoint Mismatch Count
This field is valid only in shared FIFO
operation.The application programs this filed
with a count that determines when the core
generates an Endpoint Mismatch interrupt
22:18 RW 0x08
(GINTSTS.EPMis). The core loads this value
into an internal counter and decrements it.
The counter is reloaded whenever there is a
match or when the counter expires. The width
of this counter depends on the depth of the
Token Queue.
17:13 RO 0x0 reserved

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Bit Attr Reset Value Description

PerFrInt
Periodic Frame Interval
Indicates the time within a (micro) frame at
which the application must be notified using
the End Of Periodic Frame Interrupt. This can
12:11 RW 0x0 be used to determine if all the isochronous
traffic for that (micro) frame is complete.
2'b00: 80% of the (micro)frame interval
2'b01: 85%
2'b10: 90%
2'b11: 95%
DevAddr
Device Address
10:4 RW 0x00
The application must program this field after
every SetAddress control command.
Ena32KHzS
Enable 32-KHz Suspend Mode
When the USB 1.1 Full-Speed Serial
Transceiver Interface is chosen and this bit is
set, the core expects the 48-MHz PHY clock to
3 RW 0x0 be switched to 32 KHz during a suspend. This
bit can only be set if USB 1.1 Full-Speed Serial
Transceiver Interface has been selected. If
USB 1.1 Full-Speed Serial Transceiver
Interface has not been selected, this bit must
be zero.
NZStsOUTHShk
Non-Zero-Length Status OUT Handshake
The application can use this field to select the
handshake the core sends on receiving a
nonzero-length data packet during the OUT
transaction of a control transfer's Status
stage.
1'b1: Send a STALL handshake on a
2 RW 0x0
nonzero-length status OUT transaction and do
not send the received OUT packet to the
application.
1'b0: Send the received OUT packet to the
application (zero-length or nonzerolength)
and send a handshake based on the NAK and
STALL bits for the endpoint in the Device
Endpoint Control register.

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Bit Attr Reset Value Description

DevSpd
Device Speed
Indicates the speed at which the application
requires the core to enumerate, or the
maximum speed the application can support.
However, the actual bus speed is determined
only after the chirp sequence is completed,
and is based on the speed of the USB host to
1:0 RW 0x0
which the core is connected.
2'b00: High speed (USB 2.0 PHY clock is 30
MHz or 60 MHz)
2'b01: Full speed (USB 2.0 PHY clock is 30
MHz or 60 MHz)
2'b10: Reserved
2'b11: Full speed (USB 1.1 transceiver clock
is 48 MHz)

USBOTG_DCTL
Address: Operational Base + offset (0x0804)
Device Control Register
Bit Attr Reset Value Description
31:17 RO 0x0 reserved
NakOnBble
Set NAK automatically on babble
16 RW 0x0
The core sets NAK automatically for the
endpoint on which babble is received.

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Bit Attr Reset Value Description

IgnrFrmNum
Ignore frame number for isochronous
endpoints in case of Scatte
Do NOT program IgnrFrmNum bit to 1'b1
when the core is operating in Threshold mode.
Note: When Scatter/Gather DMA mode is
enabled this feature is not applicable to
highspeed, high-bandwidth transfers. When
this bit is enabled, there must be only one
packet per descriptor.
1'b0: The core transmits the packets only in
the frame number in which they are
intended to be transmitted.
1'b1: The core ignores the frame number,
sending packets immediately as the packets
are ready.
Scatter/Gather:
In Scatter/Gather DMA mode, when this bit is
enabled, the packets are not flushed when an
15 RW 0x0
ISOC IN token is received for an elapsed
frame.
When Scatter/Gather DMA mode is disabled,
this field is used by the application to enable
periodic transfer interrupt. The application
can program periodic endpoint transfers for
multiple (micro) frames.
1'b0: Periodic transfer interrupt feature is
disabled; the application must program
transfers for periodic endpoints every
(micro)frame
1'b1: Periodic transfer interrupt feature is
enabled; the application can program
transfers for multiple (micro)frames for
periodic endpoints.
In non-Scatter/Gather DMA mode, the
application receives transfer complete
interrupt after transfers for multiple (micro)
frames are completed.
GMC
Global Multi Count
GMC must be programmed only once after
initialization. Applicable only for
Scatter/Gather DMA mode. This indicates the
number of packets to be serviced for that end
point before moving to the next end point. It is
14:13 RW 0x1
only for nonperiodic end points.
2'b00: Invalid.
2'b01: 1 packet.
2'b10: 2 packets.
2'b11: 3 packets.
When Scatter/Gather DMA mode is disabled,
this field is reserved. and reads 2'b00.
12 RO 0x0 reserved

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Bit Attr Reset Value Description

PWROnPrgDone
Power-On Programming Done
11 RW 0x0 The application uses this bit to indicate that
register programming is completed after a
wake-up from Power Down mode.
CGOUTNak
10 WO 0x0 Clear Global OUT NAK
A write to this field clears the Global OUT NAK.
SGOUTNak
Set Global OUT NAK
A write to this field sets the Global OUT NAK.
The application uses this bit to send a NAK
9 WO 0x0 handshake on all OUT endpoints. The
application must set this bit only after making
sure that the Global OUT NAK Effective bit in
the Core Interrupt Register
(GINTSTS.GOUTNakEff) is cleared.
CGNPInNak
Clear Global Non-periodic IN NAK
8 WO 0x0
A write to this field clears the Global
Non-periodic IN NAK.
SGNPInNak
Set Global Non-periodic IN NAK
A write to this field sets the Global
Non-periodic IN NAK.The application uses this
bit to send a NAK handshake on all
non-periodic IN endpoints. The core can also
7 WO 0x0
set this bit when a timeout condition is
detected on a non-periodic endpoint in shared
FIFO operation. The application must set this
bit only after making sure that the Global IN
NAK Effective bit in the Core Interrupt
Register (GINTSTS.GINNakEff) is cleared.
TstCtl
Test Control
3'b000: Test mode disabled
3'b001: Test_J mode
6:4 RW 0x0 3'b010: Test_K mode
3'b011: Test_SE0_NAK mode
3'b100: Test_Packet mode
3'b101: Test_Force_Enable
Others: Reserved
GOUTNakSts
Global OUT NAK Status
1'b0: A handshake is sent based on the FIFO
Status and the NAK and STALL bit
settings.
3 RO 0x0
1'b1: No data is written to the RxFIFO,
irrespective of space availability. Sends a NAK
handshake on all packets, except on SETUP
transactions. All isochronous OUT packets are
dropped

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Bit Attr Reset Value Description

GNPINNakSts
Global Non-periodic IN NAK Status
1'b0: A handshake is sent out based on the
2 RO 0x0 data availability in the transmit FIFO.
1'b1: A NAK handshake is sent out on all
non-periodic IN endpoints, irrespective of the
data availability in the transmit FIFO.
SftDiscon
Soft Disconnect
The application uses this bit to signal the Otg
core to do a soft disconnect. As long as this bit
is set, the host does not see that the device is
connected, and the device does not receive
signals on the USB. The core stays in the
disconnected state until the application clears
this bit.
1'b0: Normal operation. When this bit is
1 RW 0x0
cleared after a soft disconnect, the core
drives the phy_opmode_o signal on the
UTMI+ to 2'b00, which generates a device
connect event to the USB host. When the
device is reconnected, the USB host restarts
device enumeration.
1'b1: The core drives the phy_opmode_o
signal on the UTMI+ to 2'b01, which
generates a device disconnect event to the
USB host.
RmtWkUpSig
Remote Wakeup Signaling
When the application sets this bit, the core
initiates remote signaling to wake the USB
host. The application must set this bit to
instruct the core to exit the Suspend state. As
specified in the USB 2.0 specification, the
application must clear this bit 1-15 ms after
setting it. If LPM is enabled and the core is in
the L1 (Sleep) state, when the application sets
0 RW 0x0
this bit, the core initiates L1 remote signaling
to wake up the USB host. The application must
set this bit to instruct the core to exit the
Sleep state. As specified in the LPM
specification, the hardware automatically
clears this bit 50 us (TL1DevDrvResume) after
being set by the application. The application
must not set this bit when GLPMCFG
bRemoteWake from the previous LPM
transaction is zero.

USBOTG_DSTS
Address: Operational Base + offset (0x0808)
Device Status Register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

31:22 RO 0x0 reserved
SOFFN
Frame or Micro-frame Number of the Received
SOF
21:8 RW 0x0000 When the core is operating at high speed, this
field contains a micro-frame number. When
the core is operating at full or low speed, this
field contains a frame number.
7:4 RO 0x0 reserved
ErrticErr
Erratic Error
The core sets this bit to report any erratic
errors (phy_rxvalid_i/phy_rxvldh_i or
phy_rxactive_i is asserted for at least 2 ms,
due to PHY error) seen on the UTMI+. Due to
3 RW 0x0 erratic errors, the Otg core goes into
Suspended state and an interrupt is generated
to the application with Early Suspend bit of the
Core Interrupt register (GINTSTS.ErlySusp).
If the early suspend is asserted due to an
erratic error, the application can only perform
a soft disconnect recover.
EnumSpd
Enumerated Speed
Indicates the speed at which the OTG core has
come up after speed detection through a chirp
sequence.
2'b00: High speed (PHY clock is running at 30
or 60 MHz)
2:1 RW 0x0 2'b01: Full speed (PHY clock is running at 30
or 60 MHz)
2'b10: Low speed (PHY clock is running at 48
MHz, internal phy_clk at 6 MHz)
2'b11: Full speed (PHY clock is running at 48
MHz)
Low speed is not supported for devices using a
UTMI+ PHY.
SuspSts
Suspend Status
In Device mode, this bit is set as long as a
Suspend condition is detected on the USB.
The core enters the Suspended state when
there is no activity on the utmi_linestate
0 RW 0x0
signal for an extended period of time. The core
comes out of the suspend: When there is any
activity on the utmi_linestate signal, When
the application writes to the Remote Wakeup
Signaling bit in the Device Control register
(DCTL.RmtWkUpSig).

USBOTG_DIEPMSK
Address: Operational Base + offset (0x0810)

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Device IN Endpoint common interrupt mask register

Bit Attr Reset Value Description
31:14 RO 0x0 reserved
NAKMsk
13 RW 0x0
NAK interrupt Mask
12:10 RO 0x0 reserved
BNAInIntrMsk
9 RW 0x0
BNA Interrupt Mask
TxfifoUndrnMsk
8 RW 0x0
Fifo Underrun Mask
7 RO 0x0 reserved
INEPNakEffMsk
6 RW 0x0
IN Endpoint NAK Effective Mask
INTknEPMisMsk
5 RW 0x0
IN Token received with EP Mismatch Mask
INTknTXFEmpMsk
4 RW 0x0
IN Token Received When TxFIFO Empty Mask
TimeOUTMsk
3 RW 0x0
Timeout Condition Mask
AHBErrMsk
2 RW 0x0
AHB Error Mask
EPDisbldMsk
1 RW 0x0
Endpoint Disabled Interrupt Mask
XferComplMsk
0 RW 0x0
Transfer Completed Interrupt Mask

USBOTG_DOEPMSK
Address: Operational Base + offset (0x0814)
Device OUT Endpoint common interrupt mask register
Bit Attr Reset Value Description
31:15 RO 0x0 reserved
NYETMsk
14 RW 0x0
NYET Interrupt Mask
NAKMsk
13 RW 0x0
NAK Interrupt Mask
BbleErrMsk
12 RW 0x0
Babble Interrupt Mask
11:10 RO 0x0 reserved
BnaOutIntrMsk
9 RW 0x0
BNA interrupt Mask
OutPktErrMsk
8 RW 0x0
OUT Packet Error Mask
7 RO 0x0 reserved
Back2BackSETup
6 RW 0x0 Back-to-Back SETUP Packets Received Mask
Applies to control OUT endpoints only.
5 RO 0x0 reserved
OUTTknEPdisMsk
OUT Token Received when Endpoint Disabled
4 RW 0x0
Mask
Applies to control OUT endpoints only.

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Bit Attr Reset Value Description

SetUPMsk
3 RW 0x0 SETUP Phase Done Mask
Applies to control endpoints only.
AHBErrMsk
2 RW 0x0
AHB Error
EPDisbldMsk
1 RW 0x0
Endpoint Disabled Interrupt Mask
XferComplMsk
0 RW 0x0
Transfer Completed Interrupt Mask

USBOTG_DAINT
Address: Operational Base + offset (0x0818)
Device All Endpoints interrupt register
Bit Attr Reset Value Description
OutEPInt
OUT Endpoint Interrupt Bits
31:16 RO 0x0000
One bit per OUT endpoint: Bit 16 for OUT
endpoint 0, bit 31 for OUT endpoint 15
InEpInt
IN Endpoint Interrupt Bits
15:0 RO 0x0000
One bit per IN Endpoint: Bit 0 for IN endpoint
0, bit 15 for endpoint 15

USBOTG_DAINTMSK
Address: Operational Base + offset (0x081c)
Device All Endpoint interrupt mask register
Bit Attr Reset Value Description
OutEpMsk
OUT EP Interrupt Mask Bits
31:16 RW 0x0000
One per OUT Endpoint: Bit 16 for OUT EP 0, bit
31 for OUT EP 15
InEpMsk
IN EP Interrupt Mask Bits
15:0 RW 0x0000
One bit per IN Endpoint: Bit 0 for IN EP 0, bit
15 for IN EP 15

USBOTG_DTKNQR1
Address: Operational Base + offset (0x0820)
Device IN token sequence learning queue read register1
Bit Attr Reset Value Description
EPTkn
Endpoint Token
Four bits per token represent the endpoint
number of the token:
31:8 RO 0x000000 Bits [31:28]: Endpoint number of Token 5
Bits [27:24]: Endpoint number of Token 4
.......
Bits [15:12]: Endpoint number of Token 1
Bits [11:8]: Endpoint number of Token 0

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Bit Attr Reset Value Description

WrapBit
Wrap Bit
7 RO 0x0
This bit is set when the write pointer wraps. It
is cleared when the learning queue is cleared.
6:5 RO 0x0 reserved
INTknWPtr
4:0 RO 0x00
IN Token Queue Write Pointer

USBOTG_DTKNQR2
Address: Operational Base + offset (0x0824)
Device IN token sequence learning queue read register2
Bit Attr Reset Value Description
EPTkn
Endpoint Token
Four bits per token represent the endpoint
number of the token:
31:0 RW 0x00000000 Bits [31:28]: Endpoint number of Token 13
Bits [27:24]: Endpoint number of Token 12
.......
Bits [7:4]: Endpoint number of Token 7
Bits [3:0]: Endpoint number of Token 6

USBOTG_DVBUSDIS
Address: Operational Base + offset (0x0828)
Device VBUS discharge time register
Bit Attr Reset Value Description
31:16 RO 0x0 reserved
DVBUSDis
Device VBUS Discharge Time
Specifies the VBUS discharge time after VBUS
pulsing during SRP. This value
equals: VBUS discharge time in PHY clocks /
15:0 RW 0x0b8f
1,024.The value you use depends whether the
PHY is operating at 30 MHz (16-bit data width)
or 60 MHz (8-bit data width). Depending on
your VBUS load, this value can need
adjustment.

USBOTG_DVBUSPULSE
Address: Operational Base + offset (0x082c)
Device VBUS Pulsing Timer Register
Bit Attr Reset Value Description
31:12 RO 0x0 reserved

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Bit Attr Reset Value Description

DVBUSPulse
Device VBUS Pulsing Time
Specifies the VBUS pulsing time during SRP.
This value equals:VBUS pulsing time in PHY
11:0 RW 0x000
clocks / 1,024.The value you use depends
whether the PHY is operating at 30 MHz
(16-bit data width) or 60 MHz (8-bit data
width).

USBOTG_DTHRCTL
Address: Operational Base + offset (0x0830)
Device Threshold Control Register
Bit Attr Reset Value Description
31:28 RO 0x0 reserved
ArbPrkEn
Arbiter Parking Enable
This bit controls internal DMA arbiter parking
for IN endpoints. When threshold is enabled
27 RW 0x1 and this bit is set to one, then the arbiter
parks on the IN endpoint for which there is a
token received on the USB. This is done to
avoid getting into under-run conditions. By
default the parking is enabled.
26 RO 0x0 reserved
RxThrLen
Receive Threshold Length
This field specifies Receive threshold size in
DWORDS. This field also specifies the amount
of data received on the USB before the core
25:17 RW 0x008 can start transmitting on the AHB. The
threshold length has to be at least eight
DWORDS.
The recommended value for ThrLen is to be
the same as the programmed AHB Burst
Length (GAHBCFG.HBstLen).
RxThrEn
Receive Threshold Enable
16 RW 0x0
When this bit is set, the core enables
thresholding in the receive direction.
15:13 RO 0x0 reserved

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Bit Attr Reset Value Description

AHBThrRatio
AHB Threshold Ratio
These bits define the ratio between the AHB
threshold and the MAC threshold for the
transmit path only. The AHB threshold always
remains less than or equal to the USB
threshold, because this does not increase
overhead. Both the AHB and the MAC
threshold must be DWORD-aligned. The
application needs to program TxThrLen and
the AHBThrRatio to make the AHB Threshold
12:11 RW 0x0
value DWORD aligned. If the AHB threshold
value is not DWORD aligned, the core might
not behave correctly. When programming the
TxThrLen and AHBThrRatio, the application
must ensure that the minimum AHB threshold
value does not go below 8 DWORDS to meet
the USB turnaround time requirements.
2'b00: AHB threshold = MAC threshold
2'b01: AHB threshold = MAC threshold / 2
2'b10: AHB threshold = MAC threshold / 4
2'b11: AHB threshold = MAC threshold / 8
TxThrLen
Transmit Threshold Length
This field specifies Transmit threshold size in
DWORDS. This field also forms the MAC
threshold and specifies the amount of data, in
bytes, to be in the corresponding endpoint
transmit FIFO before the core can start a
transaction on the USB. When the value of
AHBThrRatio is 2'h00, the threshold length
10:2 RW 0x008
must be at least 8 DWORDS. If the
AHBThrRatio is nonzero, the application must
ensure that the AHB threshold value does not
go below the recommended 8 DWORDs.
This field controls both isochronous and
non-isochronous IN endpoint thresholds.
The recommended value for ThrLen is to be
the same as the programmed AHB Burst
Length (GAHBCFG.HBstLen).
ISOThrEn
ISO IN Endpoints Threshold Enable
1 RW 0x0
When this bit is set, the core enables
threshold for isochronous IN endpoints.
NonISOThrEn
Non-ISO IN Endpoints Threshold Enable
0 RW 0x0
When this bit is set, the core enables
threshold for Non Isochronous IN endpoints.

USBOTG_DIEPEMPMSK
Address: Operational Base + offset (0x0834)
Device IN endpoint FIFO empty interrupt mask register

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Bit Attr Reset Value Description

31:16 RO 0x0 reserved
InEpTxfEmpMsk
IN EP Tx FIFO Empty Interrupt Mask Bits
These bits act as mask bits for DIEPINTn.
15:0 RW 0x0000 TxFEmp interrupt One bit per IN Endpoint:
Bit 0 for IN endpoint 0
...
Bit 15 for endpoint 15

USBOTG_DEACHINT
Address: Operational Base + offset (0x0838)
Device each endpoint interrupt register
Bit Attr Reset Value Description
EchOutEPInt
OUT Endpoint Interrupt Bits
One bit per OUT endpoint:
31:16 RO 0x0000
Bit 16 for OUT endpoint 0
...
Bit 31 for OUT endpoint 15
EchInEpInt
IN Endpoint Interrupt Bits
One bit per IN Endpoint:
15:0 RO 0x0000
Bit 0 for IN endpoint 0
...
Bit 15 for endpoint 15

USBOTG_DEACHINTMSK
Address: Operational Base + offset (0x083c)
Device each endpoint interrupt register mask
Bit Attr Reset Value Description
EchOutEpMsk
OUT EP Interrupt Mask Bits
One per OUT Endpoint:
31:16 RW 0x0000
Bit 16 for IN endpoint 0
...
Bit 31 for endpoint 15
EchInEpMsk
IN EP Interrupt Mask Bits
One bit per IN Endpoint:
15:0 RW 0x0000
Bit 0 for IN endpoint 0
...
Bit 15 for endpoint 15

USBOTG_DIEPEACHMSKn
Address: Operational Base + offset (0x0840)
Device each IN endpoint -n interrupt Register
Bit Attr Reset Value Description
31:14 RO 0x0 reserved

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Bit Attr Reset Value Description

NAKMsk
13 RW 0x0
NAK interrupt Mask
12:10 RO 0x0 reserved
BNAInIntrMsk
9 RW 0x0
BNA interrupt Mask
TxfifoUndrnMsk
8 RW 0x0
Fifo Under run Mask
7 RO 0x0 reserved
INEPNakEffMsk
6 RW 0x0
IN Endpoint NAK Effective Mask
INTknEPMisMsk
5 RW 0x0
IN Token received with EP Mismatch Mask
INTknTXFEmpMsk
4 RW 0x0
IN Token Received When TxFIFO Empty Mask
TimeOUTMsk
3 RW 0x0 Timeout Condition Mask(Non-isochronous
endpoints)
AHBErrMsk
2 RW 0x0
AHB Error Mask
EPDisbldMsk
1 RW 0x0
Endpoint Disabled Interrupt Mask
XferComplMsk
0 RW 0x0
Transfer Completed Interrupt Mask

USBOTG_DOEPEACHMSKn
Address: Operational Base + offset (0x0880)
Device each out endpoint-n interrupt register
Bit Attr Reset Value Description
31:15 RO 0x0 reserved
NYETMsk
14 RW 0x0
NYET interrupt Mask
NAKMsk
13 RW 0x0
NAK interrupt Mask
BbleErrMsk
12 RW 0x0
Babble interrupt Mask
11:10 RO 0x0 reserved
BnaOutIntrMsk
9 RW 0x0
BNA interrupt Mask
OutPktErrMsk
8 RW 0x0
OUT Packet Error Mask
7 RO 0x0 reserved
Back2BackSETup
6 RW 0x0 Back-to-Back SETUP Packets Received Mask
Applies to control OUT endpoints only.
5 RO 0x0 reserved
OUTTknEPdisMsk
OUT Token Received when Endpoint Disabled
4 RW 0x0
Mask
Applies to control OUT endpoints only.

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Bit Attr Reset Value Description

SetUPMsk
3 RW 0x0 SETUP Phase Done Mask
Applies to control endpoints only.
AHBErrMsk
2 RW 0x0
AHB Error
EPDisbldMsk
1 RW 0x0
Endpoint Disabled Interrupt Mask
XferComplMsk
0 RW 0x0
Transfer Completed Interrupt Mask

USBOTG_DIEPCTL0
Address: Operational Base + offset (0x0900)
Device control IN endpoint 0 control register
Bit Attr Reset Value Description
EPEna
Endpoint Enable
When Scatter/Gather DMA mode is enabled,
for IN endpoints this bit indicates that the
descriptor structure and data buffer with data
ready to transmit is setup. When
31 R/WSC 0x0 Scatter/Gather DMA mode is disabled-such as
in buffer-pointer based
DMA mode-this bit indicates that data is ready
to be transmitted on the endpoint.
The core clears this bit before setting the
following interrupts on this endpoint:
Endpoint Disabled; Transfer Completed.
EPDis
Endpoint Disable
The application sets this bit to stop
transmitting data on an endpoint, even before
the transfer for that endpoint is complete. The
application must wait for the Endpoint
30 R/WSC 0x0
Disabled interrupt before treating the
endpoint as disabled. The core clears this bit
before setting the Endpoint Disabled
Interrupt. The application must set this bit
only if Endpoint Enable is already set for this
endpoint.
29:28 RO 0x0 reserved
SNAK
Set NAK
A write to this bit sets the NAK bit for the
endpoint. Using this bit, the application can
27 WO 0x0
control the transmission of NAK handshakes
on an endpoint. The core can also set this bit
for an endpoint after a SETUP packet is
received on that endpoint.

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Bit Attr Reset Value Description

CNAK
Clear NAK
26 WO 0x0
A write to this bit clears the NAK bit for the
endpoint.
25:23 RO 0x0 reserved
TxFNum
TxFIFO Number
For Shared FIFO operation, this value is
always set to 0, indicating that control IN
22 RW 0x0
endpoint 0 data is always written in the
Non-Periodic Transmit FIFO. For Dedicated
FIFO operation, this value is set to the FIFO
number that is assigned to IN Endpoint 0.
Stall
STALL Handshake
The application can only set this bit, and the
core clears it, when a SETUP token is received
21 R/WSC 0x0
for this endpoint. If a NAK bit, Global
Non-periodic IN NAK, or Global OUT NAK is set
along with this bit, the STALL bit takes
priority.
20 RO 0x0 reserved
EPType
19:18 RO 0x0 Endpoint Type
Hardcoded to 00 for control
NAKSts
NAK Status
Indicates the following:
1'b0: The core is transmitting non-NAK
handshakes based on the FIFO status
1'b1: The core is transmitting NAK
17 RO 0x0 handshakes on this endpoint.
When this bit is set, either by the application
or core, the core stops transmitting data, even
if there is data available in the TxFIFO.
Irrespective of this bit's setting, the core
always responds to SETUP data packets with
an ACK handshake.
16 RO 0x0 reserved
USBActEP
USB Active Endpoint
15 RO 0x1 This bit is always set to 1, indicating that
control endpoint 0 is always active in all
configurations and interfaces.

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Bit Attr Reset Value Description

NextEp
Next Endpoint
Applies to non-periodic IN endpoints only.
Indicates the endpoint number to be fetched
after the data for the current endpoint is
14:11 RW 0x0
fetched. The core can access this field, even
when the Endpoint Enable (EPEna) bit is not
set. This field is not valid in Slave mode. Note:
This field is valid only for Shared FIFO
operations.
10:2 RO 0x0 reserved
MPS
Maximum Packet Size
Applies to IN and OUT endpoints. The
application must program this field with the
maximum packet size for the current logical
1:0 RW 0x0
endpoint.
2'b00: 64 bytes
2'b01: 32 bytes
2'b10: 16 bytes
2'b11: 8 bytes

USBOTG_DIEPINTn
Address: Operational Base + offset (0x0908)
Device Endpoint-n Interrupt Register
Bit Attr Reset Value Description
31:15 RO 0x0 reserved
NYETIntrpt
NYET interrupt
14 W1C 0x0 The core generates this interrupt when a NYET
response is transmitted for a non-
isochronous OUT endpoint.
NAKIntrpt
NAK interrupt
The core generates this interrupt when a NAK
is transmitted or received by the device. In
13 W1C 0x0
case of isochronous IN endpoints the interrupt
gets generated when a zero length packet is
transmitted due to un-availability of data in
the TXFifo.
BbleErrIntrpt
BbleErr (Babble Error) interrupt
12 W1C 0x0
The core generates this interrupt when babble
is received for the endpoint.

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Bit Attr Reset Value Description

PktDrpSts
Packet Dropped Status
This bit indicates to the application that an
ISOC OUT packet has been dropped. This bit
11 W1C 0x0 does not have an associated mask bit and
does not generate an interrupt. Dependency:
This bit is valid in non-Scatter/Gather DMA
mode when periodic transfer interrupt feature
is selected.
10 RO 0x0 reserved
BNAIntr
BNA (Buffer Not Available) Interrupt
The core generates this interrupt when the
9 W1C 0x0 descriptor accessed is not ready for the Core
to process, such as Host busy or DMA done
Dependency: This bit is valid only when
Scatter/Gather DMA mode is enabled.
TxfifoUndrn
FIFO Under-run
Applies to IN endpoints only. The core
generates this interrupt when it detects a
transmit FIFO under-run condition for this
endpoint. Dependency: This interrupt is valid
only when both of the following conditions are
true: Parameter OTG_EN_DED_TX_FIFO==1;
8 W1C 0x0
Threshold is enabled; OUT Packet
Error(OutPktErr). Applies to OUT endpoints
only. This interrupt is asserted when the core
detects an overflow or a CRC error for an OUT
packet. Dependency: This interrupt is valid
only when both of the following conditions are
true: Parameter OTG_EN_DED_TX_FIFO==1;
Threshold is enabled.
TxFEmp
Transmit FIFO Empty
This bit is valid only for IN Endpoints. This
interrupt is asserted when the TxFIFO for this
7 W1C 0x0 endpoint is either half or completely empty.
The half or completely empty status is
determined by the TxFIFO Empty Level bit in
the Core AHB Configuration register
(GAHBCFG.NPTxFEmpLvl)).

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Bit Attr Reset Value Description

INEPNakEff
IN Endpoint NAK Effective
Applies to periodic IN endpoints only. This bit
can be cleared when the application clears the
IN endpoint NAK by writing to
DIEPCTLn.CNAK. This interrupt indicates that
the core has sampled the NAK bit set (either
by the
application or by the core). The interrupt
indicates that the IN endpoint NAK bit set by
6 W1C 0x0 the application has taken effect in the core.
This interrupt does not guarantee that a NAK
handshake is sent on the USB. A STALL bit
takes priority over a NAK bit. This bit is
applicable only when the endpoint is enabled.
Back-to-Back SETUP Packets Received
(Back2BackSETup) Applies to Control OUT
endpoints only.
This bit indicates that the core has received
more than three back-to-back SETUP
packets for this particular endpoint.
INTknEPMis
IN Token Received with EP Mismatch
Applies to non-periodic IN endpoints only.
Indicates that the data in the top of the
non-periodic TxFIFO belongs to an endpoint
other than the one for which the IN token was
received. This interrupt is asserted on the
endpoint for which the IN token was received.
Status Phase Received For Control Write
(StsPhseRcvd)
This interrupt is valid only for Control OUT
endpoints and only in Scatter Gather DMA
5 W1C 0x0
mode. This interrupt is generated only after
the core has transferred all the data that the
host has sent during the data phase of a
control write transfer, to the system memory
buffer. The interrupt indicates to the
application that the host has switched from
data phase to the status phase of a Control
Write transfer. The application can use this
interrupt to ACK or STALL the Status phase,
after it has decoded the data phase. This is
applicable only in case of Scatter Gather DMA
mode.

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Bit Attr Reset Value Description

INTknTXFEmp
IN Token Received When TxFIFO is Empty
Indicates that an IN token was received when
the associated TxFIFO periodic/nonperiodic)
was empty. This interrupt is asserted on the
endpoint for which the IN token was received.
4 W1C 0x0
OUT Token Received When Endpoint Disabled
(OUTTknEPdis) Indicates that an OUT token
was received when the endpoint was not yet
enabled. This interrupt is asserted on the
endpoint for which the OUT token was
received.
TimeOUT
Timeout Condition
In shared TX FIFO mode, applies to
non-isochronous IN endpoints only. In
dedicated FIFO mode, applies only to Control
IN endpoints. In Scatter/Gather DMA mode,
the TimeOUT interrupt is not asserted.
Indicates that the core has detected a timeout
3 W1C 0x0 condition on the USB for the last IN token on
this endpoint.
SETUP Phase Done (SetUp) Applies to control
OUT endpoints only. Indicates that the SETUP
phase for the control endpoint is complete and
no more back-to-back SETUP packets were
received for the current control transfer. On
this interrupt, the application can decode the
received SETUP data packet.
AHBErr
AHB Error
Applies to IN and OUT endpoints. This is
generated only in Internal DMA mode when
2 W1C 0x0
there is an AHB error during an AHB
read/write. The application can read the
corresponding endpoint DMA address register
to get the error address.
EPDisbld
Endpoint Disabled Interrupt
1 W1C 0x0 Applies to IN and OUT endpoints. This bit
indicates that the endpoint is disabled per the
application's request.

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Bit Attr Reset Value Description

XferCompl
Transfer Completed Interrupt
Applies to IN and OUT endpoints. When
Scatter/Gather DMA mode is enabled: For IN
endpoint this field indicates that the requested
data from the descriptor is moved from
external system memory to internal FIFO.
For OUT endpoint this field indicates that the
0 W1C 0x0 requested data from the internal FIFO is
moved to external system memory. This
interrupt is generated only when the
corresponding endpoint descriptor is closed,
and the IOC bit for the corresponding
descriptor is set. When Scatter/Gather DMA
mode is disabled, this field indicates that the
programmed transfer is complete on the AHB
as well as on the USB, for this endpoint.

USBOTG_DIEPTSIZn
Address: Operational Base + offset (0x0910)
Device endpoint n transfer size register
Bit Attr Reset Value Description
31 RO 0x0 reserved

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Bit Attr Reset Value Description

MC
Multi Count
Applies to IN endpoints only. For periodic IN
endpoints, this field indicates the number of
packets that must be transmitted per
microframe on the USB. The core uses this
field to calculate the data PID for isochronous
IN endpoints.
2'b01: 1 packet
2'b10: 2 packets
2'b11: 3 packets
For non-periodic IN endpoints, this field is
valid only in Internal DMA mode. It specifies
the number of packets the core must fetch for
an IN endpoint before it switches to the
endpoint pointed to by the Next Endpoint field
30:29 RW 0x0 of the Device Endpoint-n Control register
(DIEPCTLn.NextEp). Received Data PID
(RxDPID)
Applies to isochronous OUT endpoints only.
This is the data PID received in the last packet
for this endpoint.
2'b00: DATA0
2'b01: DATA2
2'b10: DATA1
2'b11: MDATA
SETUP Packet Count (SUPCnt).Applies to
control OUT Endpoints only. This field
specifies the number of back-to-back SETUP
data packets the endpoint can receive.
2'b01: 1 packet
2'b10: 2 packets
2'b11: 3 packets
PktCnt
Packet Count
Indicates the total number of USB packets
that constitute the Transfer Size amount of
data for this endpoint. The power-on value is
specified for Width of Packet Counters during
coreConsultant configuration (parameter
28:19 RW 0x000
OTG_PACKET_COUNT_WIDTH). IN
Endpoints: This field is decremented every
time a packet (maximum size or short packet)
is read from the TxFIFO. OUT Endpoints: This
field is decremented every time a packet
(maximum size or
short packet) is written to the RxFIFO.

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Bit Attr Reset Value Description

XferSize
Transfer Size
This field contains the transfer size in bytes for
the current endpoint. The power-on value is
specified for Width of Transfer Size Counters
during configuration (parameter
OTG_TRANS_COUNT_WIDTH). The core only
interrupts the application after it has
18:0 RW 0x00000 exhausted the transfer size amount of data.
The transfer size can be set to the maximum
packet size of the endpoint, to be interrupted
at the end of each packet. IN Endpoints: The
core decrements this field every time a packet
from the external memory is written to the
TxFIFO.OUT Endpoints: The core decrements
this field every time a packet is read from the
RxFIFO and written to the external memory.

USBOTG_DIEPDMAn
Address: Operational Base + offset (0x0914)
Device endpoint-n DMA address register
Bit Attr Reset Value Description
DMAAddr
DMA Address
Holds the start address of the external
memory for storing or fetching endpoint
data. Note: For control endpoints, this field
stores control OUT data packets as well as
SETUP transaction data packets. When more
than three SETUP packets are received
back-to-back, the SETUP data packet in the
31:0 RW 0x00000000
memory is overwritten.
This register is incremented on every AHB
transaction. The application can give
only a DWORD-aligned address. When
Scatter/Gather DMA mode is not enabled, the
application programs the start address value
in this field. When Scatter/Gather DMA mode
is enabled, this field indicates the base pointer
for the descriptor list.

USBOTG_DTXFSTSn
Address: Operational Base + offset (0x0918)
Device IN endpoint transmit FIFO status register
Bit Attr Reset Value Description
31:16 RO 0x0 reserved

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Bit Attr Reset Value Description

INEPTxFSpcAvail
IN Endpoint TxFIFO Space Avail
Indicates the amount of free space available in
the Endpoint TxFIFO. Values are in terms of
32-bit words.
16'h0: Endpoint TxFIFO is full
15:0 RW 0x0000
16'h1: 1 word available
16'h2: 2 words available
16'hn: n words available (where 0 . n .
32,768)
16'h8000: 32,768 words available
Others: Reserved

USBOTG_DIEPDMABn
Address: Operational Base + offset (0x091c)
Device endpoint-n DMA buffer address register
Bit Attr Reset Value Description
DMABufferAddr
DMA Buffer Address
Holds the current buffer address.This register
is updated as and when the data
31:0 RO 0x00000000
transfer for the corresponding end point is in
progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this
field is reserved.

USBOTG_DIEPCTLn
Address: Operational Base + offset (0x0920)
Device endpoint-n control register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

EPEna
Endpoint Enable
Applies to IN and OUT endpoints. When
Scatter/Gather DMA mode is enabled, For IN
endpoints this bit indicates that the descriptor
structure and data buffer with data ready to
transmit is setup. For OUT endpoint it
indicates that the descriptor structure and
data buffer to receive data is setup. When
Scatter/Gather DMA mode is enabled-such as
for buffer-pointer based DMA mode: For IN
31 R/WSC 0x0
endpoints, this bit indicates that data is ready
to be transmitted on the endpoint ; For OUT
endpoints, this bit indicates that the
application has allocated the memory to start
receiving data from the USB. The core clears
this bit before setting any of the following
interrupts on this endpoint: SETUP Phase
Done, Endpoint Disabled, Transfer
Completed. Note: For control endpoints in
DMA mode, this bit must be set to be able to
transfer SETUP data packets in memory.
EPDis
Endpoint Disable
Applies to IN and OUT endpoints. The
application sets this bit to stop
transmitting/receiving data on an endpoint,
even before the transfer for that endpoint is
30 R/WSC 0x0 complete. The application must wait for the
Endpoint Disabled interrupt before treating
the endpoint as disabled. The core clears this
bit before setting the Endpoint Disabled
interrupt. The application must set this bit
only if Endpoint Enable is already set for this
endpoint.
SetD1PID
Set DATA1 PID
Applies to interrupt/bulk IN and OUT
endpoints only. Writing to this field sets the
Endpoint Data PID (DPID) field in this register
to DATA1.This field is applicable both for
Scatter/Gather DMA mode and
29 WO 0x0
non-Scatter/Gather DMA mode. Set Odd
(micro) frame (SetOddFr). Applies to
isochronous IN and OUT endpoints only.
Writing to this field sets the Even/Odd (micro)
frame (EO_FrNum) field to odd (micro) frame.
This field is not applicable for Scatter/Gather
DMA mode.

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Bit Attr Reset Value Description

SetD0PID
Set DATA0 PID
Applies to interrupt/bulk IN and OUT
endpoints only. Writing to this field sets the
Endpoint Data PID (DPID) field in this register
to DATA0.This field is applicable both for
Scatter/Gather DMA mode and
non-Scatter/Gather DMA mode. In
non-Scatter/Gather DMA mode: Set Even
28 WO 0x0 (micro) frame (SetEvenFr) Applies to
isochronous IN and OUT endpoints only.
Writing to this field sets the Even/Odd (micro)
frame (EO_FrNum) field to even (micro)
frame. When Scatter/Gather DMA mode is
enabled, this field is reserved. The frame
number in which to send data is in the
transmit descriptor structure. The frame in
which to receive data is updated in recept
descriptor structure.
SNAK
Set NAK
Applies to IN and OUT endpoints. A write to
this bit sets the NAK bit for the endpoint.
27 WO 0x0 Using this bit, the application can control the
transmission of NAK handshakes on an
endpoint. The core can also set this bit for OUT
endpoints on a Transfer Completed interrupt,
or after a SETUP is received on the endpoint.
CNAK
Clear NAK
26 WO 0x0
Applies to IN and OUT endpoints. A write to
this bit clears the NAK bit for the endpoint.

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Bit Attr Reset Value Description

TxFNum
TxFIFO Number
Shared FIFO Operation:non-periodic
endpoints must set this bit to zero. Periodic
endpoints must map this to the corresponding
Periodic TxFIFO number. 4'h0: Non-Periodic
TxFIFO; Others: Specified Periodic TxFIFO
number. Note: An interrupt IN endpoint can
be configured as a non-periodic endpoint for
applications such as mass storage. The core
treats an IN endpoint as a non-periodic
25:22 RW 0x0 endpoint if the TxFNum field is set to 0.
Otherwise, a separate periodic FIFO must be
allocated for an interrupt IN endpoint, and the
number of this FIFO must be programmed into
the TxFNum field. Configuring an interrupt IN
endpoint as a non-periodic endpoint saves the
extra periodic FIFO area. Dedicated FIFO
Operation: these bits specify the FIFO number
associated with this endpoint. Each active IN
endpoint must be programmed to a separate
FIFO number. This field is valid only for IN
endpoints.
Stall
STALL Handshake
Applies to non-control, non-isochronous IN
and OUT endpoints only. The application sets
this bit to stall all tokens from the USB host to
this endpoint. If a NAK bit, Global
Non-periodic IN NAK, or Global OUT NAK is set
along with this bit, the STALL bit takes
priority. Only the application can clear this bit,
21 RW 0x0 never the core.
Applies to control endpoints only. The
application can only set this bit, and the core
clears it, when a SETUP token is received for
this endpoint. If a NAK bit, Global
Non-periodic IN NAK, or Global OUT NAK is set
along with this bit, the STALL bit takes
priority. Irrespective of this bit's setting, the
core always responds to SETUP data packets
with an ACK handshake.
Snp
Snoop Mode
Applies to OUT endpoints only. This bit
20 RW 0x0 configures the endpoint to Snoop mode. In
Snoop mode, the core does not check the
correctness of OUT packets before
transferring them to application memory.

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Bit Attr Reset Value Description

EPType
Endpoint Type
Applies to IN and OUT endpoints. This is the
transfer type supported by this logical
19:18 RW 0x0 endpoint.
2'b00: Control
2'b01: Isochronous
2'b10: Bulk
2'b11: Interrupt
NAKSts
NAK Status
Applies to IN and OUT endpoints. Indicates
the following:
1'b0: The core is transmitting non-NAK
handshakes based on the FIFO status.
1'b1: The core is transmitting NAK
handshakes on this endpoint.
When either the application or the core sets
this bit: The core stops receiving any data on
17 RO 0x0 an OUT endpoint, even if there is space in the
RxFIFO to accommodate the incoming packet.
For non-isochronous IN endpoints: The core
stops transmitting any data on an IN
endpoint, even if there data is available in the
TxFIFO. For isochronous IN endpoints: The
core sends out a zero-length data packet,
even if there data is available in the TxFIFO.
Irrespective of this bit's setting, the core
always responds to SETUP data packets with
an ACK handshake.

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Bit Attr Reset Value Description

DPID
Endpoint Data PID
Applies to interrupt/bulk IN and OUT
endpoints only. Contains the PID of the packet
to be received or transmitted on this endpoint.
The application must program the PID of the
first packet to be received or transmitted on
this endpoint, after the endpoint is activated.
The applications use the SetD1PID and
SetD0PID fields of this register to program
either DATA0 or DATA1 PID.
1'b0: DATA0
1'b1: DATA1
This field is applicable both for Scatter/Gather
DMA mode and non-Scatter/Gather
DMA mode. Even/Odd (Micro)Frame
(EO_FrNum) In non-Scatter/Gather DMA
16 RO 0x0 mode:
Applies to isochronous IN and OUT endpoints
only. Indicates the (micro) frame number in
which the core transmits/receives
isochronous data for this endpoint. The
application must program the even/odd
(micro) frame number in which it intends to
transmit/receive isochronous data for this
endpoint using the SetEvnFr and SetOddFr
fields in this register.
1'b0: Even (micro)frame
1'b1: Odd (micro)frame
When Scatter/Gather DMA mode is enabled,
this field is reserved. The frame number in
which to send data is provided in the transmit
descriptor structure. The frame in which data
is received is updated in receive descriptor
structure.
USBActEP
USB Active Endpoint
Applies to IN and OUT endpoints. Indicates
whether this endpoint is active in the current
configuration and interface. The core clears
15 R/WSC 0x0
this bit for all endpoints (other than EP 0) after
detecting a USB reset. After receiving the
SetConfiguration and SetInterface
commands, the application must program
endpoint registers accordingly and set this bit.

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Bit Attr Reset Value Description

NextEp
Next Endpoint
Applies to non-periodic IN endpoints only.
Indicates the endpoint number to be fetched
after the data for the current endpoint is
14:11 RW 0x0
fetched. The core can access this field, even
when the Endpoint Enable (EPEna) bit is low.
This field is not valid in Slave mode operation.
Note: This field is valid only for Shared FIFO
operations.
MPS
Maximum Packet Size
Applies to IN and OUT endpoints. The
10:0 RW 0x000
application must program this field with the
maximum packet size for the current logical
endpoint. This value is in bytes.

USBOTG_DOEPCTL0
Address: Operational Base + offset (0x0b00)
Device control OUT endpoint 0 control register
Bit Attr Reset Value Description
EPEna
Endpoint Enable
When Scatter/Gather DMA mode is enabled,
for OUT endpoints this bit indicates that the
descriptor structure and data buffer to receive
data is setup. When Scatter/Gather DMA
mode is disabled? such as for buffer-pointer
based DMA mode)-this bit indicates that the
31 R/WSC 0x0 application has allocated the memory to
start receiving data from the USB. The core
clears this bit before setting any of the
following interrupts on this endpoint: SETUP
Phase Done, Endpoint Disabled, Transfer
Completed.
Note: In DMA mode, this bit must be set for
the core to transfer SETUP data packets into
memory.
EPDis
Endpoint Disable
30 WO 0x0
The application cannot disable control OUT
endpoint 0.
29:28 RO 0x0 reserved
SNAK
Set NAK
A write to this bit sets the NAK bit for the
endpoint. Using this bit, the application can
27 WO 0x0
control the transmission of NAK handshakes
on an endpoint. The core can also set bit on a
Transfer Completed interrupt, or after a
SETUP is received on the endpoint.

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Bit Attr Reset Value Description

CNAK
Clear NAK
26 WO 0x0
A write to this bit clears the NAK bit for the
endpoint.
25:22 RO 0x0 reserved
Stall
STALL Handshake
The application can only set this bit, and the
core clears it, when a SETUP token is received
21 R/WSC 0x0 for this endpoint. If a NAK bit or Global OUT
NAK is set along with this bit, the STALL bit
takes priority. Irrespective of this bit’s setting,
the core always responds to SETUP data
packets with an ACK handshake.
Snp
Snoop Mode
This bit configures the endpoint to Snoop
20 RW 0x0
mode. In Snoop mode, the core does not
check the correctness of OUT packets before
transferring them to application memory.
EPType
19:18 RO 0x0 Endpoint Type
Hardcoded to 2’b00 for control.
NAKSts
NAK Status
Indicates the following:
1'b0: The core is transmitting non-NAK
handshakes based on the FIFO status.
1'b1: The core is transmitting NAK
handshakes on this endpoint.
17 RO 0x0
When either the application or the core sets
this bit, the core stops receiving data, even if
there is space in the RxFIFO to accommodate
the incoming packet.
Irrespective of this bit setting, the core always
responds to SETUP data packets with an ACK
handshake.
16 RO 0x0 reserved
USBActEP
USB Active Endpoint
15 RO 0x0 This bit is always set to 1, indicating that a
control endpoint 0 is always active in all
configurations and interfaces.
14:2 RO 0x0 reserved

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Bit Attr Reset Value Description

MPS
Maximum Packet Size
The maximum packet size for control OUT
endpoint 0 is the same as what is
1:0 RO 0x0 programmed in control IN Endpoint 0.
2'b00: 64 bytes
2'b01: 32 bytes
2'b10: 16 bytes
2'b11: 8 bytes

USBOTG_DOEPINTn
Address: Operational Base + offset (0x0b08)
Device endpoint-n control register
Bit Attr Reset Value Description
31:15 RO 0x0 reserved
NYETIntrpt
NYET interrupt
14 W1C 0x0 The core generates this interrupt when a NYET
response is transmitted for a non-isochronous
OUT endpoint.
NAKIntrpt
NAK interrupt
The core generates this interrupt when a NAK
is transmitted or received by the device. In
13 W1C 0x0
case of isochronous IN endpoints the interrupt
gets generated when a zero length packet is
transmitted due to un-availability of data in
the TXFifo.
BbleErrIntrpt
BbleErr (Babble Error) interrupt
12 W1C 0x0
The core generates this interrupt when babble
is received for the endpoint.
PktDrpSts
Packet Dropped Status
This bit indicates to the application that an
ISOC OUT packet has been dropped. This bit
11 W1C 0x0 does not have an associated mask bit and
does not generate an interrupt. Dependency:
This bit is valid in non-Scatter/Gather DMA
mode when periodic transfer interrupt feature
is selected.
10 RO 0x0 reserved
BNAIntr
BNA (Buffer Not Available) Interrupt
The core generates this interrupt when the
9 W1C 0x0 descriptor accessed is not ready for the Core
to process, such as Host busy or DMA done.
Dependency: This bit is valid only when
Scatter/Gather DMA mode is enabled.

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Bit Attr Reset Value Description

TxfifoUndrn
FIFO Underrun
Applies to IN endpoints only. The core
generates this interrupt when it detects a
transmit FIFO under-run condition for this
endpoint. Dependency: This interrupt is valid
only when both of the following conditions are
true: Parameter
8 W1C 0x0 OTG_EN_DED_TX_FIFO==1, Threshold is
enabled, OUT Packet Error (OutPktErr).
Applies to OUT endpoints only. This interrupt
is asserted when the core detects an overflow
or a CRC error for an OUT packet.
Dependency: This interrupt is valid only when
both of the following conditions are true:
Parameter OTG_EN_DED_TX_FIFO==1,
Thresholding is enabled.
TxFEmp
Transmit FIFO Empty
This bit is valid only for IN Endpoints. This
interrupt is asserted when the TxFIFO for this
7 W1C 0x0 endpoint is either half or completely empty.
The half or completely empty status is
determined by the TxFIFO Empty Level bit in
the Core AHB Configuration
register(GAHBCFG.NPTxFEmpLvl)).
INEPNakEff
IN Endpoint NAK Effective
Applies to periodic IN endpoints only. This bit
can be cleared when the application clears the
IN endpoint NAK by writing to
DIEPCTLn.CNAK. This interrupt indicates that
the core has sampled the NAK bit set (either
by the application or by the core). The
interrupt indicates that the IN endpoint NAK
bit set by the application has taken effect in
6 W1C 0x0
the core. This interrupt does not guarantee
that a NAK handshake is sent on the USB. A
STALL bit takes priority over a NAK bit. This bit
is applicable only when the endpoint is
enabled. Back-to-Back SETUP Packets
Received (Back2BackSETup) Applies to
Control OUT endpoints only.
This bit indicates that the core has received
more than three back-to-back SETUP
packets for this particular endpoint.

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Bit Attr Reset Value Description

INTknEPMis
IN Token Received with EP Mismatch
Applies to non-periodic IN endpoints only.
Indicates that the data in the top of the
non-periodic TxFIFO belongs to an endpoint
other than the one for which the IN token was
5 W1C 0x0 received. This interrupt is asserted on the
endpoint for which the IN token was received.
Status Phase Received For Control Write
(StsPhseRcvd)
This interrupt is valid only for Control OUT
endpoints and only in Scatter Gather DMA
mode.
INTknTXFEmp
IN Token Received When TxFIFO is Empty
Indicates that an IN token was received when
the associated TxFIFO periodic/non-periodic)
was empty. This interrupt is asserted on the
endpoint for which the IN token was received.
4 W1C 0x0
OUT Token Received When Endpoint Disabled
(OUTTknEPdis) Indicates that an OUT token
was received when the endpoint was not yet
enabled. This interrupt is asserted on the
endpoint for which the OUT token was
received.
TimeOUT
Timeout Condition
In shared TX FIFO mode, applies to
non-isochronous IN endpoints only. In
dedicated FIFO mode, applies only to Control
IN endpoints. In Scatter/Gather DMA mode,
the Timeout interrupt is not asserted.
Indicates that the core has detected a timeout
3 W1C 0x0 condition on the USB for the last IN token on
this endpoint. SETUP Phase Done (SetUp).
Applies to control OUT endpoints only.
Indicates that the SETUP phase for the control
endpoint is complete and no more
back-to-back SETUP packets were received
for the current control transfer. On this
interrupt, the application can decode the
received SETUP data packet.
AHBErr
AHB Error
Applies to IN and OUT endpoints. This is
generated only in Internal DMA mode when
2 W1C 0x0
there is an AHB error during an AHB
read/write. The application can read the
corresponding endpoint DMA address register
to get the error address.

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Bit Attr Reset Value Description

EPDisbld
Endpoint Disabled Interrupt
1 W1C 0x0 Applies to IN and OUT endpoints. This bit
indicates that the endpoint is disabled per the
application's request.
XferCompl
Transfer Completed Interrupt
Applies to IN and OUT endpoints. When
Scatter/Gather DMA mode is enabled
For IN endpoint this field indicates that the
requested data from the descriptor is moved
from external system memory to internal
FIFO. For OUT endpoint this field indicates
0 W1C 0x0 that the requested data from the internal FIFO
is moved to external system memory. This
interrupt is generated only when the
corresponding endpoint descriptor is closed,
and the IOC bit for the corresponding
descriptor is set. When Scatter/Gather DMA
mode is disabled, this field indicates that the
programmed transfer is complete on the AHB
as well as on the USB, for this endpoint.

USBOTG_DOEPTSIZn
Address: Operational Base + offset (0x0b10)
Device endpoint n transfer size register
Bit Attr Reset Value Description
31 RO 0x0 reserved

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Bit Attr Reset Value Description

MC
Multi Count
Applies to IN endpoints only. For periodic IN
endpoints, this field indicates the number of
packets that must be transmitted per
micro-frame on the USB. The core uses this
field to calculate the data PID for isochronous
IN endpoints.
2'b01: 1 packet
2'b10: 2 packets
2'b11: 3 packets
For non-periodic IN endpoints, this field is
valid only in Internal DMA mode. It specifies
the number of packets the core must fetch for
an IN endpoint before it switches to the
endpoint pointed to by the Next Endpoint field
30:29 RW 0x0 of the Device Endpoint-n Control register
(DIEPCTLn.NextEp). Received Data PID
(RxDPID)
Applies to isochronous OUT endpoints only.
This is the data PID received in the last packet
for this endpoint.
2'b00: DATA0
2'b01: DATA2
2'b10: DATA1
2'b11: MDATA
SETUP Packet Count (SUPCnt).Applies to
control OUT Endpoints only. This field
specifies the number of back-to-back SETUP
data packets the endpoint can receive.
2'b01: 1 packet
2'b10: 2 packets
2'b11: 3 packets
PktCnt
Packet Count
Indicates the total number of USB packets
that constitute the Transfer Size amount of
data for this endpoint. The power-on value is
specified for Width of Packet Counters
28:19 RW 0x000 (parameter OTG_PACKET_COUNT_WIDTH).
IN Endpoints: This field is decremented every
time a packet (maximum size or short packet)
is read from the TxFIFO. OUT Endpoints: This
field is decremented every time a packet
(maximum size or short packet) is written to
the RxFIFO.

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Bit Attr Reset Value Description

XferSize
Transfer Size
This field contains the transfer size in bytes for
the current endpoint. The power-on value is
specified for Width of Transfer Size Counters
(parameter OTG_TRANS_COUNT_WIDTH).
The core only interrupts the application after it
has exhausted the transfer size amount of
18:0 RW 0x00000 data. The transfer size can be set to the
maximum packet size of the endpoint, to be
interrupted at the end of each packet. IN
Endpoints: The core decrements this field
every time a packet from the external
memory is written to the TxFIFO.
OUT Endpoints: The core decrements this
field every time a packet is read from the
RxFIFO and written to the external memory.

USBOTG_DOEPDMAn
Address: Operational Base + offset (0x0b14)
Device Endpoint-n DMA Address Register
Bit Attr Reset Value Description
DMAAddr
DMA Address
Holds the start address of the external
memory for storing or fetching endpoint
data. Note: For control endpoints, this field
stores control OUT data packets as well as
SETUP transaction data packets. When more
than three SETUP packets are received
back-to-back, the SETUP data packet in the
31:0 RW 0x00000000
memory is overwritten.
This register is incremented on every AHB
transaction. The application can give only a
DWORD-aligned address. When
Scatter/Gather DMA mode is not enabled, the
application programs the start address value
in this field. When Scatter/Gather DMA mode
is enabled, this field indicates the base pointer
for the descriptor list.

USBOTG_DOEPDMABn
Address: Operational Base + offset (0x0b1c)
Device endpoint-n DMA buffer address register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

DMABufferAddr
DMA Buffer Address
Holds the current buffer address. This register
is updated as and when the data
31:0 RO 0x00000000
transfer for the corresponding end point is in
progress. This register is present only in
Scatter/Gather DMA mode. Otherwise this
field is reserved.

USBOTG_DOEPCTLn
Address: Operational Base + offset (0x0b20)
Device endpoint-n control register
Bit Attr Reset Value Description
EPEna
Endpoint Enable
Applies to IN and OUT endpoints. When
Scatter/Gather DMA mode is enabled,
For IN endpoints this bit indicates that the
descriptor structure and data buffer with data
ready to transmit is setup. For OUT endpoint it
indicates that the descriptor structure and
data buffer to receive data is setup. When
Scatter/Gather DMA mode is enabled-such as
for buffer-pointer based DMA mode:
31 R/WSC 0x0
For IN endpoints, this bit indicates that data
is ready to be transmitted on the
endpoint; For OUT endpoints, this bit indicates
that the application has allocated the memory
to start receiving data from the USB. The core
clears this bit before setting any of the
following interrupts on this endpoint: SETUP
Phase Done, Endpoint Disabled, Transfer
Completed. Note: For control endpoints in
DMA mode, this bit must be set to be able to
transfer SETUP data packets in memory.
EPDis
Endpoint Disable
Applies to IN and OUT endpoints. The
application sets this bit to stop
transmitting/receiving data on an endpoint,
even before the transfer for that endpoint is
30 R/WSC 0x0 complete. The application must wait for the
Endpoint Disabled interrupt before treating
the endpoint as disabled. The core clears this
bit before setting the Endpoint Disabled
interrupt. The application must set this bit
only if Endpoint Enable is already set for this
endpoint.

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Bit Attr Reset Value Description

SetD1PID
Field0001 Abstract
Applies to interrupt/bulk IN and OUT
endpoints only.Writing to this field sets the
Endpoint Data PID (DPID) field in this register
to DATA1.This field is applicable both for
Scatter/Gather DMA mode and
29 RO 0x0
non-Scatter/Gather DMA mode. Set Odd
(micro) frame (SetOddFr). Applies to
isochronous IN and OUT endpoints only.
Writing to this field sets the Even/Odd (micro)
frame (EO_FrNum) field to odd (micro) frame.
This field is not applicable for Scatter/Gather
DMA mode.
SetD0PID
Set DATA0 PID
Applies to interrupt/bulk IN and OUT
endpoints only. Writing to this field sets the
Endpoint Data PID (DPID) field in this register
to DATA0.This field is applicable both for
Scatter/Gather DMA mode and
non-Scatter/Gather DMA mode. In
non-Scatter/Gather DMA mode: Set Even
28 WO 0x0 (micro) frame (SetEvenFr) Applies to
isochronous IN and OUT endpoints only.
Writing to this field sets the Even/Odd (micro)
frame (EO_FrNum) field to even (micro)
frame. When Scatter/Gather DMA mode is
enabled, this field is reserved. The frame
number in which to send data is in the
transmit descriptor structure. The frame in
which to receive data is updated in recept
descriptor structure.
SNAK
Set NAK
Applies to IN and OUT endpoints. A write to
this bit sets the NAK bit for the endpoint.
27 WO 0x0 Using this bit, the application can control the
transmission of NAK handshakes on an
endpoint. The core can also set this bit for OUT
endpoints on a Transfer Completed interrupt,
or after a SETUP is received on the endpoint.
CNAK
Clear NAK
26 WO 0x0
Applies to IN and OUT endpoints. A write to
this bit clears the NAK bit for the endpoint.

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Bit Attr Reset Value Description

TxFNum
TxFIFO Number
Shared FIFO Operation: non-periodic
endpoints must set this bit to zero. Periodic
endpoints must map this to the corresponding
Periodic TxFIFO number. 4'h0: Non-Periodic
TxFIFO; Others: Specified Periodic TxFIFO
number. Note: An interrupt IN endpoint can
be configured as a non-periodic endpoint for
applications such as mass storage. The core
treats an IN endpoint as a non-periodic
25:22 RW 0x0 endpoint if the TxFNum field is set to 0.
Otherwise, a separate periodic FIFO must be
allocated for an interrupt IN endpoint using
coreConsultant, and the number of this FIFO
must be programmed into the TxFNum field.
Configuring an interrupt IN endpoint as a
non-periodic endpoint saves the extra periodic
FIFO area. Dedicated FIFO Operation: these
bits specify the FIFO number associated with
this endpoint. Each active IN endpoint must
be programmed to a separate FIFO number.
This field is valid only for IN endpoints.
Stall
STALL Handshake
Applies to non-control, non-isochronous IN
and OUT endpoints only. The application sets
this bit to stall all tokens from the USB host to
this endpoint. If a NAK bit, Global
Non-periodic IN NAK, or Global OUT NAK is set
along with this bit, the STALL bit takes
priority. Only the application can clear this bit,
21 RW 0x0 never the core.
Applies to control endpoints only. The
application can only set this bit, and the core
clears it, when a SETUP token is received for
this endpoint. If a NAK bit, Global
Non-periodic IN NAK, or Global OUT NAK is set
along with this bit, the STALL bit takes
priority. Irrespective of this bit's setting, the
core always responds to SETUP data packets
with an ACK handshake.
Snp
Snoop Mode
Applies to OUT endpoints only. This bit
20 RW 0x0 configures the endpoint to Snoop mode. In
Snoop mode, the core does not check the
correctness of OUT packets before
transferring them to application memory.

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Bit Attr Reset Value Description

EPType
Endpoint Type
Applies to IN and OUT endpoints. This is the
transfer type supported by this logical
19:18 RW 0x0 endpoint.
2'b00: Control
2'b01: Isochronous
2'b10: Bulk
2'b11: Interrupt
NAKSts
NAK Status
Applies to IN and OUT endpoints. Indicates
the following:
1'b0: The core is transmitting non-NAK
handshakes based on the FIFO status.
17 RO 0x0
1'b1: The core is transmitting NAK
handshakes on this endpoint.
When either the application or the core sets
this bit: The core stops receiving any data on
an OUT endpoint, even if there is space in the
RxFIFO to accommodate the incoming packet.

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Bit Attr Reset Value Description

DPID
Endpoint Data PID
Applies to interrupt/bulk IN and OUT
endpoints only. Contains the PID of the packet
to be received or transmitted on this endpoint.
The application must program the PID of the
first packet to be received or transmitted on
this endpoint, after the endpoint is activated.
The applications use the SetD1PID and
SetD0PID fields of this register to program
either DATA0 or DATA1 PID.
1'b0: DATA0
1'b1: DATA1
This field is applicable both for Scatter/Gather
DMA mode and non-Scatter/Gather
DMA mode. Even/Odd (Micro) Frame
(EO_FrNum). In non-Scatter/Gather DMA
16 RO 0x0
mode: Applies to isochronous IN and OUT
endpoints only. Indicates the (micro) frame
number in which the core transmits/receives
isochronous data for this endpoint. The
application must program the even/odd
(micro) frame number in which it intends to
transmit/receive isochronous data for this
endpoint using the SetEvnFr and SetOddFr
fields in this register.
1'b0: Even (micro)frame
1'b1: Odd (micro)frame
When Scatter/Gather DMA mode is enabled,
this field is reserved. The frame number in
which to send data is provided in the transmit
descriptor structure. The frame in which data
is received is updated in receive descriptor
structure.
USBActEP
USB Active Endpoint
Applies to IN and OUT endpoints. Indicates
whether this endpoint is active in the current
configuration and interface. The core clears
15 R/WSC 0x0
this bit for all endpoints (other than EP 0) after
detecting a USB reset. After receiving the
SetConfiguration and SetInterface
commands, the application must program
endpoint registers accordingly and set this bit.

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Bit Attr Reset Value Description

NextEp
Next Endpoint
Applies to non-periodic IN endpoints only.
Indicates the endpoint number to be fetched
after the data for the current endpoint is
14:11 RW 0x0
fetched. The core can access this field, even
when the Endpoint Enable (EPEna) bit is low.
This field is not valid in Slave mode operation.
Note: This field is valid only for Shared FIFO
operations.
MPS
Maximum Packet Size
Applies to IN and OUT endpoints. The
10:0 RW 0x000
application must program this field with the
maximum packet size for the current logical
endpoint. This value is in bytes.

USBOTG_PCGCR
Address: Operational Base + offset (0x0b24)
Power and clock gating control register
Bit Attr Reset Value Description

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Bit Attr Reset Value Description

RestoreValue
Restore Value
(Applicable only when Hibernation is enabled
(OTG_EN_PWROPT=2). Defines port clock
select for different speeds.
[31] if_dev_mode
- 1: Device mode, core restored as device
- 0: Host mode, core restored as host
[30:29] p2hd_prt_spd (PRT speed)
- 00: HS
- 01: FS
- 10: LS
- 11: Reserved
[28:27] p2hd_dev_enum_spd (Device
enumerated speed)
- 00: HS
31:14 RW 0x0802e - 01: FS (30/60 MHz clock)
- 10: LS
- 11: FS (48 MHz clock)
[26:20] mac_dev_addr (MAC device address)
Device address
[19] mac_termselect (Termination selection)
- 0: HS_TERM (Program for High Speed)
- 1: FS_TERM (Program for Full Speed)
[18:17] mac_xcvrselect (Transceiver select)
- 00: HS_XCVR (High Speed)
- 01: FS_XCVR (Full Speed)
- 10: LS_XCVR (Low Speed)
- 11: LFS_XCVR (Reserved)
[16] sh2pl_prt_ctl[0]
- 1: port_power enabled
- 0: port_power disabled
[15:14] prt_clk_sel (Refer prt_clk_sel table)
EssRegRestored
Essential Register Values Restored
(Applicable only when Hibernation is enabled
13 RW 0x0 (OTG_EN_PWROPT=2). When a value of 1 is
written to this field, it indicates that register
values of essential registers have been
restored.
12:10 RO 0x0 reserved

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Bit Attr Reset Value Description

RestoreMode
Restore Mode
(Applicable only when Hibernation is enabled
(OTG_EN_PWROPT=2). The application
should program this bit to specify the restore
mode during RESTORE POINT before
programming PCGCCTL.EssRegRest bit is set.
9 RO 0x0 Host Mode:
1'b0: Host Initiated Resume, Host Initiated
Reset
1'b1: Device Initiated Remote Wake up
Device Mode:
1'b0: Device Initiated Remote Wake up
1'b1: Host Initiated Resume, Host Initiated
Reset
ResetAfterSusp
Reset After Suspend
Applicable in Partial power-down mode. In
partial power-down mode of operation, this bit
needs to be set in host mode before clamp is
removed if the host needs to issue reset after
suspend. If this bit is not set, then the host
8 RW 0x0
issues resume after suspend. This bit is not
applicable in device mode and non-partial
power-down mode. In Hibernation mode, this
bit needs to be set at RESTORE_POINT before
PCGCCTL.EssRegRestored is set. In this case,
PCGCCTL.restore_mode needs to be set to
wait_restore.
L1Suspended
Deep Sleep
7 RO 0x0
This bit indicates that the PHY is in deep sleep
when in L1 state.
PhySleep
PHY in Sleep
6 RO 0x0
This bit indicates that the PHY is in the Sleep
state.
Enbl_L1Gating
Enable Sleep Clock Gating
When this bit is set, core internal clock gating
5 RW 0x0 is enabled in Sleep state if the core cannot
assert utmi_l1_suspend_n. When this bit is
not set, the PHY clock is not gated in Sleep
state.
4 RO 0x0 reserved
RstPdwnModule
Reset Power-Down Modules
This bit is valid only in Partial Power-Down
3 RW 0x0 mode. The application sets this bit when the
power is turned off. The application clears this
bit after the power is turned on and the PHY
clock is up.

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Bit Attr Reset Value Description

PwrClmp
Power Clamp
This bit is valid only in Partial Power-Down
mode (OTG_EN_PWROPT = 1). The
application sets this bit before the power is
2 RW 0x0
turned off to clamp the signals between the
power-on modules and the power-off
modules. The application clears the bit to
disable the clamping before the power is
turned on.
GateHclk
Gate Hclk
The application sets this bit to gate hclk to
modules other than the AHB Slave and
1 RW 0x0
Master and wakeup logic when the USB is
suspended or the session is not valid.
The application clears this bit when the USB is
resumed or a new session starts.
StopPclk
Stop Pclk
The application sets this bit to stop the PHY
clock (phy_clk) when the USB is
0 RW 0x0
suspended, the session is not valid, or the
device is disconnected. The application clears
this bit when the USB is resumed or a new
session starts.

26.7 Interface description

Table 26-1 USB OTG 2.0 Interface Description

Module Pin Direction Pad Name pinmux

VSSA AG VSSA -
VCCA3P3 AP VCCA3P3 -
VCCCORE1P2 AP VCCCORE1P2 -
USB0PN A USB0PN -
USBRBIAS A USBRBIAS -
USB0PP A USB0PP -
VBUS_0 A VBUS_0 -
USB0ID A USB0ID -
Note: A—Analog pad ; AP—Analog power; AG—Analog ground ;DP—Digital
power ;DG–Digital ground;

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26.8 Application Note

26.8.1 Resume from Suspend Mode

Fig. 26-11 Resume Timing Sequence

When COMMONONN = 1’b1, T1 < T0 + 805 us

When COMMONONN = 1’b0, T1 < T0 + 16 us

26.8.2 Reset a port

Because the assertion of PORTRESET can occur during data reception or

transmission, PORTRESET must be de-asserted as follows:
❖ Reception:
✦ FS device: After a minimum of 3 μs of stable SE0 on LINESTATE [1:0]
✦ FS/LS host: After a minimum of 8 bit times of J state on LINESTATE [1:0]
✦ HS host/device: A minimum of 150 μs after asserting PORTRESET

❖ Transmission:

✦ FS device: After the controller sets both TXVALID and TXVALIDH to 1’b0,
followed by a minimum of 3 μs of stable SE0 on LINESTATE [1:0]
✦ FS/LS host: After the controller sets both TXVALID0 and TXVALIDH0 to
1’b0, followed by a minimum of 8 bit times of J state on LINESTATE [1:0]
✦ HS host/device: A minimum of 150 μs after the controller sets both
TXVALID0 and TXVALIDH0 to 1’b0. The preceding requirements ensure that
there is no activity on the USB when PORTRESET0 is de-asserted.
To avoid any data glitches during port reset, the controller must place the
USB 2.0 PHY into a safe state. A safe state for host and device ports is
defined as follows:
❖ Host: The USB 2.0 PHY is set to Non-Driving (OPMODE [1:0] = 2’b01),
and the 15-kΩ pull-down resistors are enabled (DPPULLDOWN and

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DMPULLDOWN = 1’b1).
❖ Device: The USB 2.0 PHY is set to Non-Driving (OPMODE [1:0] = 2’b01),
which disconnects the 1.5-kΩ resistor from the D+ line.

Fig. 26-12 Reset a port when receiving

Fig. 26-13 Reset a port when transmitting

CRU_SOFTRST4_CON contains the OTG reset signal. Please refer to “Chapter

CRU” for more details.
26.8.3 Relative GRF Registers

GRF_UOC0_CON0 ~ GRF_UOC0_CON2 is OTG PHY register.

GRF_UOC0_CON3 is OTG Controller register.
Please refer to “Chapter GRF” for more details.

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