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TPS54541
SLVSC57B – OCTOBER 2013 – REVISED FEBRUARY 2016

TPS54541 4.5-V to 42-V Input, 5-A Step-Down DC-DC Converter

With Soft-Start and Eco-mode™
1 Features 3 Description
1• High Efficiency at Light Loads with Pulse Skipping The TPS54541 device is a 42-V 5-A step-down
Eco-mode™ regulator with an integrated high-side MOSFET. The
device survives load dump pulses up to 45 V per ISO
• 87-mΩ High-Side MOSFET 7637. Current mode control provides simple external
• 152-μA Operating Quiescent Current and compensation and flexible component selection. A
2-μA Shutdown Current low-ripple pulse-skip mode reduces the no-load
• 100-kHz to 2.5-MHz Adjustable Switching supply current to 152 μA. When the enable pin is
Frequency pulled low, the shutdown supply current is reduced to
2 μA .
• Synchronizes to External Clock
Undervoltage lockout is internally set at 4.3 V but can
• Low Dropout at Light Loads with Integrated BOOT
increase using an external resistor divider at the
Recharge FET enable pin. The output voltage startup ramp is
• Adjustable UVLO Voltage and Hysteresis controlled by the soft-start pin that can also be
• UV and OV Power-Good Output configured for sequencing and tracking. An open-
• Adjustable Soft-Start and Sequencing drain power-good signal indicates the output is within
93% to 106% of the nominal voltage.
• 0.8-V 1% Internal Voltage Reference
A wide adjustable switching-frequency range allows
• 10-Pin WSON with Thermal Pad Package
for optimization of either efficiency or external
• –40°C to 150°C TJ Operating Range component size. Cycle-by-cycle current limit,
• Supported by WEBENCH® Software Tool frequency foldback, and thermal shutdown protect
internal and external components during an overload
2 Applications condition.
• Industrial Automation and Motor Control The TPS54541 device is available in a 10-pin 4-mm ×
4-mm WSON package.
• Vehicle Accessories: GPS (see SLVA412),
Entertainment Device Information(1)
• USB-Dedicated Charging Ports and Battery PART NUMBER PACKAGE BODY SIZE (NOM)
Chargers (see SLVA464)
TPS54541 WSON (10) 4.00 mm × 4.00 mm
• 12-V and 24-V Industrial, Automotive and
(1) For all available packages, see the orderable addendum at
Communications Power Systems the end of the data sheet.
Simplified Schematic
Efficiency vs Load Current
VIN
VIN PWRGD 100
36 V to 12 V
TPS54541 95

EN BOOT 90
RT/CLK VOUT
Efficiency (%)

85
SS/TR SW
12 V to 3.3 V
80
12 V to 5 V
COMP 75
FB
70

GND 65 VOUT = 12 V, fsw = 620 kHz,

VOUT = 5 V and 3.3 V, f sw = 400 kHz
60
0 0.5 1 1.5 2 2.5 3 3.5
IO - Output Current (A) C099

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 27
2 Applications ........................................................... 1 8 Application and Implementation ........................ 28
3 Description ............................................................. 1 8.1 Application Information............................................ 28
4 Revision History..................................................... 2 8.2 Typical Applications ............................................... 28
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 42
6 Specifications......................................................... 4 10 Layout................................................................... 43
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 43
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 43
6.3 Recommended Operating Conditions....................... 4 10.3 Estimated Circuit Area .......................................... 43
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 44
6.5 Electrical Characteristics........................................... 5 11.1 Device Support...................................................... 44
6.6 Timing Requirements ................................................ 6 11.2 Documentation Support ........................................ 44
6.7 Switching Requirements ........................................... 6 11.3 Community Resources.......................................... 44
6.8 Typical Characteristics .............................................. 7 11.4 Trademarks ........................................................... 44
7 Detailed Description ............................................ 12 11.5 Electrostatic Discharge Caution ............................ 44
7.1 Overview ................................................................. 12 11.6 Glossary ................................................................ 44
7.2 Functional Block Diagram ....................................... 13 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 13 Information ........................................................... 44

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (August 2015) to Revision B Page

• Added: SW, 5-ns Transient to the Absolute Maximum Ratings ............................................................................................ 4

• Changed text in the Application Information From: "iterative design procedure" To: "interactive design procedure".......... 28

Changes from Original (October 2013) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1

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5 Pin Configuration and Functions

DPR Package
10-Pin WSON With Exposed Thermal Pad
Top View

BOOT 1 10 PWRGD

VIN 2 9 SW

EN 3 8 GND

SS/TR 4 7 COMP

RT/CLK 5 6 FB

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below the
BOOT 1 O minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is
refreshed.
Error amplifier output and input to the output switch current (PWM) comparator. Connect frequency
COMP 7 O
compensation components to this pin.
Enable pin, with an internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the
EN 3 I
input undervoltage lockout with two resistors. See the Enable and Adjusting Undervoltage Lockout section.
FB 6 I Inverting input of the transconductance (gm) error amplifier.
GND 8 – Ground
Power Good is an open drain output that asserts low if the output voltage is out of regulation due to thermal
PWRGD 10 O
shutdown, dropout, over-voltage or EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the operating mode returns to resistor frequency programming.
Soft-start and Tracking. An external capacitor connected to this pin sets the output rise time. Because the
SS/TR 4 I
voltage on this pin overrides the internal reference, SS/TR can be used for tracking and sequencing.
SW 9 O The source of the internal high-side power MOSFET and switching node of the converter.
VIN 2 I Input supply voltage with 4.5-V to 42-V operating range.
The GND pin must be electrically connected to the exposed pad on the printed circuit board for proper
Thermal Pad 11 –
operation.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 45
EN –0.3 8.4
BOOT–SW –0.3 8
FB –0.3 3
COMP –0.3 3
Voltage PWRGD –0.3 6 V
SS/TR –0.3 3
RT/CLK –0.3 3.6
SW –0.6 45
SW, 5-ns Transient –7 65
SW, 10-ns Transient –2 45
Operating junction temperature –40 150 °C
Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- V
±500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VVIN Supply input voltage 4.5 42 V
VO Output voltage 0.8 41.1 V
IO Output current 0 5 A
TJ Operating junction temperature –40 150 °C

6.4 Thermal Information

TPS54541
THERMAL METRIC (1) (2) DPR (WSON) UNIT
10 PINS
RθJA Junction-to-ambient thermal resistance (standard board) 35.1 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 34.1 °C/W
RθJB Junction-to-board thermal resistance 12.3 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 12.5 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 2.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See Power Dissipation Estimate for more information.

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6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 4.5 42 V
Internal undervoltage lockout
Rising 4.1 4.3 4.48 V
threshold
Internal undervoltage lockout
325 mV
threshold hysteresis
Shutdown supply current EN = 0 V, 25°C, 4.5 V ≤ VIN ≤ 42 V 2.25 4.5
Operating: nonswitching supply μA
FB = 0.9 V, TA = 25°C 152 200
current
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V
Enable threshold +50 mV –4.6
Input current μA
Enable threshold –50 mV –0.58 –1.2 -1.8
Hysteresis current –2.2 –3.4 -4.5 μA
Enable to COMP active VIN = 12 V, TA = 25°C 540 µs
VOLTAGE REFERENCE
Voltage reference 0.792 0.8 0.808 V
HIGH-SIDE MOSFET
On-resistance VIN = 12 V, BOOT-SW = 6 V 87 185 mΩ
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance
–2 μA < ICOMP < 2 μA, VCOMP = 1 V 350 μS
(gm)
Error amplifier transconductance
–2 μA < ICOMP < 2 μA, VCOMP = 1 V, VFB = 0.4 V 77 μS
(gm) during soft-start
Error amplifier dc gain VFB = 0.8 V 10,000 V/V
Min unity gain bandwidth 2500 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±30 μA
COMP to SW current
17 A/V
transconductance
CURRENT LIMIT
All VIN and temperatures, Open Loop (1) 6.3 7.5 8.8
Current limit threshold All temperatures, VIN = 12 V, Open Loop (1) 6.3 7.5 8.3 A
VIN = 12 V, TA = 25°C, Open Loop (1) 7.1 7.5 7.9
Current limit threshold delay 60 ns
THERMAL SHUTDOWN
Thermal shutdown 176 °C
Thermal shutdown hysteresis 12 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
RT/CLK high threshold 1.55 2 V
RT/CLK low threshold 0.5 1.2 V
SOFT START AND TRACKING (SS/TR PIN)
Charge current VSS/TR = 0.4 V 1.7 µA
SS/TR-to-FB matching VSS/TR = 0.4 V 42 mV
SS/TR-to-reference crossover 98% nominal 1.16 V
SS/TR discharge current (overload) FB = 0 V, VSS/TR = 0.4 V 354 µA
SS/TR discharge voltage FB = 0 V 54 mV
POWER GOOD (PWRGD PIN)
FB threshold for PWRGD low FB falling 90%
FB threshold for PWRGD high FB rising 93%
FB threshold for PWRGD low FB rising 108%

(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.
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Electrical Characteristics (continued)

TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FB threshold for PWRGD high FB falling 106%
Hysteresis FB falling 2.5%
Output high leakage VPWRGD = 5.5 V, TA = 25°C 10 nA
On resistance IPWRGD = 3 mA, VFB < 0.79 V 45 Ω
Minimum VIN for defined output VPWRGD < 0.5 V, IPWRGD = 100 µA 0.9 2 V

6.6 Timing Requirements

TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
MIN NOM MAX UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Minimum CLK input pulse width 15 ns
RT/CLK falling edge to SW rising edge delay – Measured at 500 kHz with RT
55 ns
resistor in series

6.7 Switching Requirements

TJ = –40°C to 150°C, VIN = 4.5 V to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
ƒSW Switching frequency RT = 200 kΩ 450 500 550 kHz
Switching frequency
100 2500 kHz
range using RT mode
Switching frequency
160 2300 kHz
range using CLK mode
PLL lock in time Measured at 500 kHz 78 μs

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6.8 Typical Characteristics

0.25 0.814
RDSON - Static Drain-Source

0.809

VFB - Voltage Reference (V)

0.2
On-State Resistance ( )

0.804
0.15
0.799
0.1
0.794

0.05 BOOT-SW = 3 V 0.789

BOOT-SW = 6 V V IN ==12
VIN 12VV
0 0.784
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ ± Junction Temperature (ƒC) C001 TJ ± Junction Temperature (ƒC) C002

Figure 1. ON Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature

9 9
High Slide Switch Current (A)

High Slide Switch Current (A)

8.5 8.5

8 8

7.5 7.5

7 7

±40ƒC
6.5 6.5
25°C
V IN ==12
VIN 12VV
150°C
6 6
±50 ±25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45
TJ ± Junction Temperature (ƒC) C003 VI - Input Voltage (V) C004

Figure 3. Switch Current Limit vs Junction Temperature Figure 4. Switch Current Limit vs Input Voltage
550 500
540
FSW - Switching Frequency (kHz)

450
fSW - Switching Frequency (kHz)

530
400
520
510 350

500 300
490
250
480
200
470
460 150
RT
R T ==200
200kk, ,VIN
VIN == 12
12 V
V
450 100
±50 ±25 0 25 50 75 100 125 150 200 300 400 500 600 700 800 900 1000
TJ Junction - Temperature (ƒC) C005 RT/CLK - Resistance (k ) C006

Figure 5. Switching Frequency vs Junction Temperature Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range

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Typical Characteristics (continued)

2500 500
FSW - Switching Frequency (kHz)

450
2000

400

gm - uA/V
1500
350
1000
300

500
250
VIN
VIN ==12
12VV
0 200
0 50 100 150 200 ±50 ±25 0 25 50 75 100 125 150
RT/CLK - Resistance (k ) C007 TJ ± Junction Temperature (ƒC) C008

Figure 7. Switching Frequency vs RT/CLK Resistance High Figure 8. EA Transconductance vs Junction Temperature
Frequency Range
120 1.3
110
100 1.27
90 EN - Threshold (V)
gm - uA/V

80 1.24
70
60 1.21
50
40 1.18
30 VIN
VIN ==12
12VV VIN
VIN ==12
12VV
20 1.15
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ ± Junction Temperature (ƒC) C009 TJ ± Junction Temperature (ƒC) C010

Figure 9. EA Transconductance During Soft-Start vs Figure 10. EN Pin Voltage vs Junction Temperature
Junction Temperature
±3.5 ±0.5
±3.7 ±0.7
±3.9 ±0.9
±4.1 ±1.1
Current IEN (uA)

Current IEN (uA)

±4.3 ±1.3
±4.5 ±1.5
±4.7 ±1.7
±4.9 ±1.9
±5.1 ±2.1
±5.3 VIN ±2.3
V IN ==12
12V,
V,IEN
IEN = Threshold
= Threshold + 50
+ 50 mVmV VIN
VIN ==12
12V,
V,IEN
IEN== Threshold
Threshold + 50
- 50 mVmV
±5.5 ±2.5
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ ± Junction Temperature (ƒC) C011 TJ ± Junction Temperature (ƒC) C012

Figure 11. EN Pin Current vs Junction Temperature Figure 12. EN Pin Current vs Junction Temperature

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Typical Characteristics (continued)

±2.5 100.0
±2.7

Nominal Switching Frequency (%)

±2.9
75.0
IEN Hysteresis (uA)

±3.1
±3.3
±3.5 50.0
±3.7
±3.9
25.0
±4.1
V SENSE Falling
Vsense Falling
±4.3 VVIN
IN ==12
12VV
Vsense
V Falling
SENSE Rising
±4.5 0.0
±50 ±25 0 25 50 75 100 125 150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
TJ ± Junction Temperature (ƒC) C013 VSENSE (V) C014

Figure 13. EN Pin Current Hysteresis vs Junction Figure 14. Switching Frequency vs FB
Temperature
3 3

2.5 2.5

Supply Current IVIN (uA)

Supply Current IVIN (uA)

2 2

1.5 1.5

1 1

0.5 0.5
VIN
V IN ==12
12VV TVIN = 12
J = 25 °C V
0 0
±50 ±25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45
TJ ± Junction Temperature (ƒC) C015 VIN - Input Voltage (V) C016

Figure 15. Shutdown Supply Current vs Junction Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
Temperature
210 210

190 190
Supply Current IVIN (uA)
Supply Current IVIN (uA)

170 170

150 150

130 130

110 110

90 90
VIN
V IN ==12
12VV TVIN
J = 25 °CV
= 12
70 70
±50 ±25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45
TJ ± Junction Temperature (ƒC) C017 VIN - Input Voltage (ƒC) C018

Figure 17. VIN Supply Current vs Junction Temperature Figure 18. VIN Supply Current vs Input Voltage

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Typical Characteristics (continued)

2.6 4.5

2.5 4.4

2.4 4.3
VI(BOOT-PH) (V)

2.3 4.2

VIN (V)
2.2 4.1

2.1 4

2 3.9
BOOT-PH UVLO Falling UVLO Start Switching
1.9 3.8
BOOT-PH UVLO Rising UVLO Stop Switching
1.8 3.7
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ ± Junction Temperature (ƒC) C019 TJ ± Junction Temperature (ƒC) C020

Figure 19. BOOT-SW UVLO vs Junction Temperature Figure 20. Input Voltage UVLO vs Junction Temperature
80 110
FB
108
70
Power Good Resistance ( )

106

Power Good Threshold (%)

60 FB Falling
104
50 102
100 VIN = 12 V
40
98
30 96
94 FB Rising
20
92
10
VIN
VIN ==12
12VV 90
FB Falling
0 88
±50 ±25 0 25 50 75 100 125 150 ±50 ±25 0 25 50 75 100 125 150
TJ ± Junction Temperature (ƒC) C021 TJ ± Junction Temperature (ƒC) C022

Figure 21. PWRGD ON Resistance vs Junction Temperature Figure 22. PWRGD Threshold vs Junction Temperature
900 60
VVIN
IN = =
1212V,V,2525°C°C
800 55
SS/TR to FB Offset (mV)

700
50
600
45
Offset (mV)

500
40
400
35
300
30
200

100 25
VIN
V IN ==12
12V,
V,FB
FB==0.4
0.4VV
0 20
0 100 200 300 400 500 600 700 800 ±50 ±25 0 25 50 75 100 125 150
SS/TR (mV) C024 TJ ± Junction Temperature (ƒC) C025

Figure 23. SS/TR to FB Offset vs FB Figure 24. SS/TR to FB Offset vs Temperature

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Typical Characteristics (continued)

5.6
Start
5.5 Stop
5.4
5.3
5.2

VIN (V)
5.1 Dropout
Voltage
5.0
4.9 Dropout
4.8 Voltage

4.7
4.6
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A) C026

Figure 25. 5-V Start and Stop Voltage

(see Low Dropout Operation and Bootstrap Voltage (BOOT))

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7 Detailed Description

7.1 Overview
The TPS54541 is a 42-V 5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. The
device implements constant-frequency current-mode control which reduces output capacitance and simplifies
external frequency compensation. The wide switching frequency range of 100 to 2500 kHz allows for either
efficiency or size optimization when selecting the output filter components. The switching frequency is adjusted
using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-locked loop (PLL)
connected to the RT/CLK pin that synchronizes the power switch turn-on to a falling edge of an external clock
signal.
The TPS54541 device has a default input start-up voltage of 4.3 V typical. The EN pin adjusts the input-voltage
undervoltage-lockout (UVLO) threshold with two external resistors. An internal-pullup current source enables
operation when the EN pin is floating. The operating current is 152 μA under a no-load condition when not
switching. When the device is disabled, the supply current is 2 μA.
The integrated 87-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering 5
A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET is supplied by
a bootstrap capacitor connected from the BOOT to SW pins. The TPS54541 device reduces the external
component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage is monitored by a
UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below a preset
threshold. An automatic BOOT capacitor recharge circuit allows the TPS54541 device to operate at high duty
cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supply voltage of
the application. The minimum output voltage is the internal 0.8-V feedback reference.
Output overvoltage transients are minimized by an overvoltage protection (OVP) comparator. When the OVP
comparator is activated, the high-side MOSFET turns off and remains off until the output voltage is less than
106% of the desired output voltage.
The SS/TR (soft-start/tracking) pin minimizes inrush currents or provides power-supply sequencing during power
up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistor divider can be
connected to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged before the
output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO fault, or a
disabled condition. When the overload condition is removed, the soft-start circuit controls the recovery from the
fault output level to the nominal regulation voltage. A frequency-foldback circuit reduces the switching frequency
during startup and overcurrent fault conditions to help maintain control of the inductor current.

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7.2 Functional Block Diagram

PWRGD EN VIN

Shutdown Thermal
Shutdown UVLO
Enable
UV Logic Comparator
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Minimum Boot
Reference Current
Clamp UVLO
Pulse Sense
Error Skip
Amplifier PWM BOOT
FB Comparator

SS/TR
Logic

Shutdown

Slope
6 Compensation SW
COMP
Frequency
Foldback

Overload
Recovery

Maximum
Clamp
Oscillator
with PLL

10/9/2013 A0272435

GND POWERPAD RT/ CLK

7.3 Feature Description

7.3.1 Fixed-Frequency PWM Control
The TPS54541 device uses fixed-frequency peak-current-mode control with adjustable switching frequency. The
output voltage is compared through external resistors connected to the FB pin to an internal voltage reference by
an error amplifier. An internal oscillator initiates the turn-on of the high-side power switch. The error amplifier
output at the COMP pin controls the high-side power switch current. When the high-side MOSFET switch current
reaches the threshold level set by the COMP voltage, the power switch turns off. The COMP pin voltage
increases and decreases as the output current increases and decreases. The device implements current limiting
by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode is implemented with a
minimum voltage clamp on the COMP pin.

7.3.2 Slope Compensation Output Current

The TPS54541 device adds a compensating ramp to the MOSFET switch current-sense signal. This slope
compensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current limit of the
high-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.

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Feature Description (continued)

7.3.3 Pulse Skip Eco-mode
The TPS54541 device operates in a pulse-skipping Eco-mode at light-load currents to improve efficiency by
reducing switching and gate drive losses. If the output voltage is within regulation and the peak switch current at
the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-mode. The
pulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of
600 mV.
When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.
Because the device is not switching, the output voltage begins to decay. The voltage-control loop responds to
the falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switching
resumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers to
the regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time the
device again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at light
load currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.
During Eco-mode operation, the TPS54541 device senses and controls peak switch current, not the average
load current. Therefore the load current at which the device enters Eco-mode is dependent on the output inductor
value. As the load current approaches zero, the device enters a pulse skip mode during which it draws only 152-
μA input quiescent current. The circuit in Figure 46 enters Eco-mode at about 18-mA output current and with no
external load has an average input current of 260 µA.

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54541 device provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT
and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor refreshes when the
high-side MOSFET is off and the external low-side diode conducts. The recommended value of the BOOT
capacitor is 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating
of 10 V or higher for stable performance over temperature and voltage.
When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54541
device operates at 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When the
voltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-side
MOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET at
high output voltages, the low-side MOSFET is disabled at 24-V output and re-enabled when the output reaches
21.5 V.
Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET remains on for
many switching cycles before the MOSFET turns off to refresh the capacitor. Thus the effective duty cycle of the
switching regulator can be high, approaching 100%. The effective duty cycle of the converter during dropout is
mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode
voltage, and the printed circuit-board resistance.

The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage is
plotted versus load current. The start voltage is defined as the input voltage required to regulate the output within
1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or where
switching stops.
During high duty-cycle (low dropout) conditions, the inductor current ripple increases when the BOOT capacitor
recharges resulting in an increase in output voltage ripple. Increased ripple occurs when the off-time required to
recharge the BOOT capacitor is longer than the high-side off-time associated with cycle-by-cycle PWM control.

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Feature Description (continued)

At heavy loads, the minimum input voltage must increase to ensure a monotonic start-up. Use Equation 1 to
calculate the minimum input voltage for this condition.
VOmax = Dmax × (VVINmin – IOmax × RDS(on) + Vd) – Vd – IOmax × Rdc (1)
where
• Dmax ≥ 0.9
• Vd = forward drop of the catch diode
• RDS(on) = 1 / (–0.3 × VB2SW2 + 3.577 × VB2SW – 4.246)
– VB2SW = VBOOT + Vd
– VBOOT = (1.41 × VVIN – 0.554 – Vd × ƒSW – 1.847 × 103 × IB2SW) / (1.41 + ƒSW)
– IB2SW = 100 × 10-6 A

7.3.5 Error Amplifier

The TPS54541 voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-start
operation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-
start voltage.
The frequency-compensation components (capacitor, series resistor, and capacitor) connect between the error
amplifier output COMP pin and GND pin.

7.3.6 Adjusting the Output Voltage

The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap-reference circuit. A resistor divider from the output node to
the FB pin sets the output voltage. Using 1% tolerance or better divider resistors is recommended. Select the
low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improve efficiency at
light loads consider using larger value resistors. However, if the values are too high, the regulator is more
susceptible to noise and voltage errors from the FB input current could become noticeable.
æV - 0.8 V ö
RHS = RLS ´ ç OUT ÷
è 0.8 V ø (2)

7.3.7 Enable and Adjusting Undervoltage Lockout

The TPS54541 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceeds the
enable threshold of 1.2 V. The TPS54541 device disables when the VIN pin voltage falls below 4 V or when the
EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I1, of 1.2 μA enabling operation
of the TPS54541 device when the EN pin floats.
If an application requires a higher UVLO threshold, use the circuit shown in Figure 26 to adjust the input voltage
UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional 3.4 μA of hysteresis
current, IHYS, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.4-μA IHYS current is
removed. This additional current facilitates adjustable input-voltage UVLO hysteresis. Use Equation 3 to calculate
RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 for the desired VIN start
voltage.
In applications designed to start at relatively low input voltages (that is, from 4.5 to 9 V) and withstand high input
voltages (for example, 40 V), the EN pin can experience a voltage greater than the absolute maximum voltage of
8.4 V during the high input-voltage condition. To avoid exceeding this voltage when using the EN resistors, the
EN pin is clamped internally with a 5.8-V Zener diode capable of sinking up to 150 μA.
V - VSTOP
RUVLO1 = START
IHYS (3)
VENA
RUVLO2 =
VSTART - VENA
+ I1
RUVLO1 (4)

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Feature Description (continued)

VIN
TPS54541 VIN TPS54541

i1 ihys
RUVLO1 RUVLO1

10 kΩ
EN EN
Node

VEN
RUVLO2 RUVLO2 5.8 V

Figure 26. Adjustable Undervoltage Lockout Figure 27. Internal EN Pin Clamp
(UVLO)

7.3.8 Soft-Start/Tracking Pin (SS/TR)

The TPS54541 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pin
voltage as the reference voltage of the power supply and regulates the output accordingly. A capacitor on the
SS/TR pin to ground implements a soft-start time. The TPS54541 device has an internal pullup current source of
1.7 μA that charges the external soft-start capacitor. The calculations for the soft start time (10% to 90%) are
shown in Equation 5. The voltage reference (VREF) is 0.8 V and the soft-start current (ISS) is 1.7μA. The soft-start
capacitor should remain lower than 0.47 μF and greater than 0.47 nF.
T (ms) ´ ISS (µA)
CSS (nF) = SS
VREF (V) ´ 0.8 (5)
At power up, the TPS54541 device does not begin switching until the soft start pin is discharged to less than 54
mV to ensure a proper power-up, see Figure 28.
Also, during normal operation, the TPS54541 device stops switching, the SS/TR must discharge to 54 mV, and,
when the VIN UVLO is exceeded, the EN pin must pull below 1.2 V, otherwise a thermal shutdown event occurs.
The FB voltage follows the SS/TR pin voltage with a 42-mV offset up to 85% of the internal voltage reference.
When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the
effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).
The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.

Figure 28. Operation of SS/TR Pin when Starting

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Feature Description (continued)

7.3.9 Sequencing
Many of the common power supply sequencing methods are implemented using the SS/TR, EN, and PWRGD
pins. The sequential method is implemented using an open-drain output of a power on the reset pin of another
device. The sequential method is illustrated in Figure 29 using two TPS54541 devices. The power good is
connected to the EN pin on the TPS54541 device which enables the second power supply once the primary
supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply
provides a 1-ms startup delay. Figure 30 shows the results of Figure 29.
TPS54541 TPS54541

PWRGD
EN EN

SS /TR SS /TR

PWRGD

Figure 29. Schematic for Sequential Startup Figure 30. Sequential Startup using EN and
Sequence PWRGD

TPS54160
TPS54541

3 EN

4 SS/TR

6 PWRGD

TPS54541
TPS54160

3 EN

4 SS/TR

6 PWRGD

Figure 31. Schematic for Ratiometric Startup Figure 32. Ratiometric Startup Using Coupled
Sequence SS/TR pins

Figure 31 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The
regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the pullup
current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.

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Feature Description (continued)

TPS54541

EN VOUT 1

SS/TR

PWRGD

TPS54541
EN VOUT 2

R1

SS/ TR

R2
PWRGD
R3
R4

Figure 33. Schematic for Ratiometric and Simultaneous Startup Sequence

Ratiometric and simultaneous power-supply sequencing are implemented by connecting the resistor network of
R1 and R2 shown in Figure 33 to the output of the power supply that must be tracked or another voltage
reference source. Using Equation 6 and Equation 7, calculate the tracking resistors to initiate the VOUT2 slightly
before, after or at the same time as VOUT1. Equation 8 is the voltage difference between VOUT1 and VOUT2 at the
95% of nominal output regulation.
The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset
(VSSoffset) in the soft-start circuit and the offset created by the pullup-current source (ISS) and tracking resistors,
the VSSoffset and ISS are included as variables in the equations.
To design a ratio-metric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2
reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in a
positive number for applications which the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.
Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO, or thermal shutdown
fault, careful selection of the tracking resistors ensures that the device restarts after a fault. The calculated R1
value from Equation 6 must be greater than the value calculated in Equation 9 to ensure the device recovers
from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage, the VSSoffset becomes larger as
the soft-start circuits gradually hands-off the regulation reference to the internal voltage reference. The SS/TR pin
voltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown in
Figure 23.
V + DV VSSoffset
R1 = OUT2 ´
VREF ISS (6)
VREF ´ R1
R2 =
VOUT2 + DV - VREF (7)
DV = VOUT1 - VOUT2 (8)
R1 > 2800 ´ VOUT1 - 180 ´ DV (9)

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Feature Description (continued)

Figure 34. Ratiometric Startup with Tracking Resistors Figure 35. Ratiometric Startup with Tracking Resistors

Figure 36. Simultaneous Startup With Tracking Resistor

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Feature Description (continued)

7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)
The switching frequency of the TPS54541 device is adjustable over a wide range from 100 to 2500 kHz by
placing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and must
have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching
frequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution size
typically set the switching frequency as high as possible. Consider the tradeoffs of the conversion efficiency,
maximum input voltage, and minimum controllable on time. The minimum controllable on time is typically 135 ns,
which limits the maximum operating frequency in applications with high input to output step-down ratios. The
maximum switching frequency is also limited by the frequency-foldback circuit. A more detailed discussion of the
maximum switching frequency is provided in the next section.
92 417
RT (kW) =
ƒSW (kHz)0.991 (10)
101756
ƒSW (kHz) =
RT (kW)1.008 (11)

7.3.11 Synchronization to RT/CLK Pin

The RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implement
this synchronization feature, connect a square wave to the RT/CLK pin through either circuit network shown in
Figure 37. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2.0 V and
have a pulsewidth greater than 15 ns. The synchronization frequency range is 160 to 2300 kHz. The rising edge
of the SW synchronizes to the falling edge of RT/CLK pin signal. Design the external synchronization circuit such
that the default-frequency set resistor connects from the RT/CLK pin to ground when the synchronization signal
is off. When using a low impedance signal source, the frequency set resistor connects in parallel with an AC-
coupling capacitor to a termination resistor (for example, 50 Ω) as shown in Figure 37. The two resistors in the
series provide the default-frequency-setting resistance when the signal source is turned off. The sum of the
resistance sets the switching frequency close to the external CLK frequency. AC-coupling the synchronization
signal through a 10-pF ceramic capacitor to RT/CLK pin is recommended.
The first time the RT/CLK is pulled above the PLL threshold, the TPS54541 device switches from the RT-resistor
free-running frequency mode to the PLL-synchronized mode. The internal 0.5-V voltage source is removed and
the RT/CLK pin becomes high impedance as the PLL begins to lock onto the external signal. The switching
frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from
the resistor mode to the PLL mode and locks onto the external clock frequency within 78 µs. During the transition
from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz and then
increases or decreases to the resistor programmed frequency when the 0.5-V bias voltage is reapplied to the
RT/CLK resistor.
The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The device
implements a digital frequency foldback enables synchronization to an external clock during normal startup and
fault conditions. Figure 38, Figure 39 and Figure 40 show the device synchronized to an external system clock in
continuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).
SPACER

TPS54541 TPS54541
RT/CLK
RT/CLK
PLL PLL
RT Hi-Z
Clock
Clock RT
Source
Source

Figure 37. Synchronizing to a System Clock

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Feature Description (continued)

Figure 38. Plot of Synchronizing in CCM Figure 39. Plot of Synchronizing in DCM

Figure 40. Plot of Synchronizing in Eco-mode

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Feature Description (continued)

7.3.12 Maximum Switching Frequency
To protect the converter in overload conditions at higher switching frequencies and input voltages, the TPS54541
device implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FB pin
voltage falls from 0.8 V to 0 V. The TPS54541 device uses a digital frequency foldback to enable synchronization
to an external clock during normal startup and fault conditions. During short-circuit events, the inductor current
can exceed the peak current-limit because of the high-input voltage and the minimum controllable on time. When
the output voltage is forced low by the shorted load, the inductor current decreases slowly during the switch off
time. The frequency foldback effectively increases the off time by increasing the period of the switching cycle
providing more time for the inductor current to ramp down.
With a maximum frequency-foldback ratio of 8, there is a maximum frequency at which the inductor current is
controlled by frequency-foldback protection. Equation 13 calculates the maximum switching frequency at which
the inductor current remains under control when VOUT is forced to VOUT(SC). The selected operating frequency
must not exceed the calculated value.
Equation 12 calculates the maximum switching-frequency limitation set by the minimum controllable on time and
the input to output step-down ratio. Setting the switching frequency above this value causes the regulator to skip
switching pulses to achieve the low duty cycle required to regulate the output voltage at maximum input voltage.
1 æç IO ´ Rdc + VOUT + Vd ö÷
ƒSW (max skip ) = ´
tON ç VIN - IO ´ RDS(on ) + Vd ÷
è ø (12)

ƒDIV æç ICL ´ Rdc + VOUT(sc ) + Vd ö

÷
ƒSW(shift) = ´
tON ç VIN - ICL ´ RDS(on ) + Vd ÷
è ø (13)
where (for Equation 12 and Equation 13)
• IO = output current
• ICL = current limit
• Rdc = inductor resistance
• VIN = maximum input voltage
• VOUT = output voltage
• VOUT(SC) = output voltage during short
• Vd = diode voltage drop
• RDS(on) = switch on resistance
• tON = controllable on time
• ƒDIV = frequency divide equals (1, 2, 4, or 8)

7.3.13 Accurate Current Limit Operation

The TPS54541 device implements peak current-mode control in which the COMP pin voltage controls the peak
current of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltage
are compared each cycle. When the peak switch current intersects the COMP control voltage, the high-side
switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier increases
switch current by driving the COMP pin high. The error amplifier output is clamped internally at a level, which
sets the peak switch current limit. The TPS54541 device provides an accurate current limit threshold with a
typical current limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor
current. The relationship between the inductor value and the peak inductor current is shown in Figure 41.

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Feature Description (continued)

Peak Inductor Current

ΔCLPeak Open Loop Current Limit

Inductor Current (A)

ΔCLPeak = VIN/L x tCLdelay

tCLdelay

tON

Figure 41. Current Limit Delay

7.3.14 Power Good (PWRGD Pin)

The PWRGD pin is an open-drain output. When the FB pin is between 93% and 106% of the internal voltage
reference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is
5.5 V or less is recommended. A higher pullup resistance reduces the amount of current drawn from the pullup
voltage source when the PWRGD pin is asserted low. A lower pullup resistance reduces the switching noise
seen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V but
with reduced current sinking capability. The PWRGD achieves full current sinking capability as VIN input voltage
approaches 3 V.
The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internal
reference voltage. If the UVLO or thermal shutdown are asserted or the EN pin pulled low, the PWRGD is pulled
low.

7.3.15 Overvoltage Protection

The TPS54541 device incorporates an output overvoltage-protection (OVP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients in designs with low-output capacitance.
For example, when the power supply output is overloaded the error amplifier compares the actual output voltage
to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltage for a
considerable time, the output of the error amplifier increases to a maximum voltage corresponding to the peak
current limit threshold. When the overload condition is removed, the regulator output rises and the error amplifier
output transitions to the normal operating level. In some applications, the power-supply output voltage increases
faster than the response of the error amplifier output resulting in an output overshoot.
The OVP feature minimizes output overshoot when using a low-value output capacitor by comparing the FB pin
voltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pin
voltage is greater than the rising OVP threshold, the high-side MOSFET immediately disables to minimize output
overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of the internal
voltage reference, the high-side MOSFET resumes normal operation.

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Feature Description (continued)

7.3.16 Thermal Shutdown
The TPS54541 device provides an internal thermal shutdown to protect the device when the junction
temperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds the
thermal trip threshold. When the die temperature falls below 164°C, the device reinitiates the power-up sequence
controlled by discharging the SS/TR pin.

7.3.17 Small-Signal Model for Loop Response

Figure 42 shows a simplified equivalent model for the TPS54541 control loop which can be simulated to check
the frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a
gmEA of 350 μA/V. The error amplifier is modeled using an ideal voltage-controlled current source. The resistor
RO and capacitor CO model the open-loop gain and frequency response of the amplifier. The 1-mV AC-voltage
source between the nodes a and b effectively breaks the control loop for the frequency response measurements.
Plotting c/a provides the small signal response of the frequency compensation. Plotting a/b provides the small
signal response of the overall loop. The dynamic loop response is evaluated by replacing RL with a current
source with the appropriate load-step amplitude and step rate in a time-domain analysis. This equivalent model is
only valid for CCM operation.

SW
VO
Power Stage
gmps 17 A/V
a

R1 RESR

COMP RL
c
FB COUT
0.8 V
R3 CO RO
gmea
C2
350 mA/V R2
C1

Figure 42. Small-Signal Model for Loop Response

7.3.18 Simple Small-Signal Model for Peak-Current-Mode Control

Figure 43 describes a simple small-signal model used to design the frequency compensation. The TPS54541
power stage is approximated by a voltage-controlled current source (duty-cycle modulator) supplying current to
the output capacitor and load resistor. Equation 14 shows the control to output transfer function. The control to
output transfer function consists of a DC gain, one dominant pole, and one equivalent-series-resistor (ESR) zero.
The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 42) is the
power stage transconductance, gmPS. The gmPS for the TPS54541 device is 17 A/V. The low-frequency gain of
the power stage is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic, but the dominant pole moves with the load current (see
Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 43. As the load
current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the
same with varying load conditions. The type of output capacitor chosen determines whether the ESR zero has a
profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors can
reduce the number of frequency compensation components required to stabilize the overall loop because the
phase margin is increased by the ESR zero of the output capacitor (see Equation 17).

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Feature Description (continued)

VO

VC Adc
RESR
fp
RL
gmps
COUT

fz

Figure 43. Simple Small-Signal Model and Frequency Response for Peak Current-Mode Control

æ s ö
ç1 + ÷
VOUT 2p ´ ƒ Z
= Adc ´ è ø
VC æ s ö
ç1 + ÷
è 2 p ´ ƒP ø (14)
Adc = gmps ´ RL
(15)
1
ƒP =
COUT ´ RL ´ 2p (16)
1
ƒZ =
COUT ´ RESR ´ 2p (17)

7.3.19 Small Signal Model for Frequency Compensation

The TPS54541 device uses a transconductance amplifier for the error amplifier and supports three of the
commonly-used frequency compensation circuits. Figure 44 shows compensation circuits Type 2A, Type 2B, and
Type 1 . Type 2 circuits are typically implemented in high-bandwidth power-supply designs using low-ESR output
capacitors. The Type 1 circuit is implemented with power-supply designs with high-ESR aluminum electrolytic or
tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier to the small
signal model in Figure 44. The open-loop gain and bandwidth are modeled using the RO and CO shown in
Figure 44. See for a design example using a Type 2A network with a low-ESR output capacitor.
Equation 18 through Equation 27 are provided as references. An alternative is to use WEBENCH® software tools
to create a design based on the power-supply requirements (go to www.ti.com/WEBENCH for more information).

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Feature Description (continued)

VO

R1
FB
gmea Type 2A Type 2B Type 1
COMP

VREF
R3 C2 R3
R2 RO CO C2

C1 C1

Figure 44. Types of Frequency Compensation

Aol

A0 P1

Z1 P2
A1

BW

Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Aol (V / V )
RO =
gmea (18)
gmea
CO =
2p ´ BW (Hz) (19)
æ s ö
ç1 + ÷
è 2p ´ ƒ Z1 ø
EA = A0 ´
æ s ö æ s ö
ç1 + ÷ ´ ç1 + ÷
è 2p ´ ƒP1 ø è 2p ´ ƒP2 ø (20)
R2
A0 = gm ea ´ RO ´
R1 + R2 (21)
R2
A1 = gm ea ´ RO P R3 ´
R1 + R2 (22)
1
P1 =
2p ´ Ro ´ C1 (23)

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Feature Description (continued)

1
Z1 =
2p ´ R3 ´ C1 (24)
1
P2 = Type 2A
2p ´ R3 P RO ´ (C2 + CO ) (25)
1
P2 = Type 2B
2p ´ R3 P RO ´ CO (26)
1
P2 = Type 1
2p ´ RO ´ (C2 + CO ) (27)

7.4 Device Functional Modes

TI designed the TPS54541 to operate with input voltages above 4.5 V. When the VIN voltage is above the 4.3-V
typical rising UVLO threshold and the EN voltage is above the 1.2-V typical threshold, the device is active. If the
VIN voltage falls below the typical 4-V UVLO turnoff threshold, the device stops switching. If the EN voltage falls
below the 1.2-V threshold, the device stops switching and enters shutdown mode with a low-supply current of 2
µA typical.
The TPS54541 operates in CCM when the output current is enough to keep the inductor current above 0 A at the
end of each switching period. As a non-synchronous converter, the device enters DCM at low-output currents
when the inductor current falls to 0 A before the end of a switching period. At very-low output current, the COMP
voltage drops to the pulse-skipping threshold and the device operates in a pulse-skipping Eco-mode. In this
mode, the high-side MOSFET does not switch every switching period. This operating mode reduces power loss,
while regulating the output voltage. For more information on Eco-mode, see the Pulse Skip Eco-mode section.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54541 device is a 42-V, 5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher-dc voltage to a lower-dc voltage with a maximum available output current of 5 A.
Example applications are the following: 12-V and 24-V industrial, automotive, and communication power
systems. Use the following design procedure to select component values for the TPS54541 device. The
spreadsheet (SLVC452) on the product page can help with all calculations. Alternatively, use the WEBENCH
software to generate a complete design. The WEBENCH software uses an interactive design procedure and
accesses a comprehensive database of components when generating a design.

8.2 Typical Applications

8.2.1 Buck Converter for 6-V to 42-V Input and 3.3-V at 5-A Output
PWRGD PWRGD PULL UP

R8
6V to 42V U1 TP10 TP9
1.00k
VIN 2 2 10
VIN PWRGD
TP1 C4
1

1 C11 3 1
GND
+ EN BOOT L1
3.3V @ 5A
R1
J2 DNP C10 C3 C1 C2 5 9 0.1µF 1
365k RT/CLK SW VOUT
4.7µF 4.7µF 4.7µF 4.7µF TP5 744325550 TP6 TP7
SS/TR 4 6 5.5µH 2 GND
SS/TR FB FB
2

3
R3 R7

1
TP2 243k 7 8 49.9 J1
COMP GND D1 TP8
PAD + C12
GND PDS760-13
C13 R4 TPS54541DPR C6 C7 DNPC9 DNP
16.9k 100µF 100µF 47µF GND
0.01µF C8 TP4
2 GND

2
GND 1 47pF
1

2
R5
C5 31.6k
J4 4700pF
2 R2
EN
1 88.7k FB
GND GND
GND
J3 R6
10.2k
TP3

GND
2 SS/TR GND
SS/TR
GND 1

J5

GND

Figure 46. 3.3-V Output TPS54541 Design Example

8.2.1.1 Design Requirements

This guide illustrates the design of a high-frequency switching regulator using ceramic output capacitors. A few
parameters must be known to start the design process. These requirements are typically determined at the
system level. Calculations can be done with WEBENCH or the excel spreadsheet (SLVC452) located on the
product page. TI designed this example to the known parameters listed in Table 1.

Table 1. Design Parameters

PARAMETER VALUE
Output Voltage 3.3 V
Transient Response 1.25 A to 3.75 A load step ΔVOUT = 4 %
Maximum Output Current 5A
Input Voltage 12 V nominal 6 V to 42 V
Output Voltage Ripple 0.5% of VOUT
Start Input Voltage (rising VIN) 5.75 V
Stop Input Voltage (falling VIN) 4.5 V

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8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Selecting the Switching Frequency

Choose a switching frequency for the regulator. Typically, a designer uses the highest switching frequency
possible because this produces the smallest solution size. High-switching frequency allows for lower-value
inductors and smaller-output capacitors compared to a power supply that switches at a lower frequency. The
switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input
voltage, the output voltage, and the frequency-foldback protection.
Use Equation 12 and Equation 13 to calculate the upper limit of the switching frequency for the regulator.
Choose the lower value result from the two equations. Switching frequencies higher than these values results in
pulse skipping or the lack of overcurrent protection during a short circuit.
The typical minimum on time, tonmin, is 135 ns for the TPS54541 device. For this example, the output voltage is
3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of
10.3 mΩ, typical switch resistance of 87 mΩ and 5-A load, from Equation 12 the maximum switch frequency to
avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits, use
Equation 13 to determine the maximum switching frequency for frequency foldback protection. With a current-
limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz.
For this design, TI chose a lower-switching frequency of 400 kHz to operate below the calculated maximums. To
determine the timing resistance for a given switching frequency, use Equation 10 or the curve in Figure 6.
Figure 46 shows resistor R3, which sets the switching frequency . For 400-kHz operation, the closest standard
value resistor is 243 kΩ.
1 æ 5 A x 10.3 mW + 3.3 V + 0.52 V ö
fSW(max skip) = ´ ç ÷ = 680 kHz
135ns è 42 V - 5 A x 87 mW + 0.52 V ø (28)
8 æ 6.3 A x 10.3 mW + 0.1 V + 0.52 V ö
fSW(shift) = ´ ç ÷ = 960 kHz
135 ns è 42 V - 6.3 A x 87 mW + 0.52 V ø (29)
92417
RT (kW) = = 244 kW
400 (kHz)0.991 (30)

8.2.1.2.2 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 31.
KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The
inductor ripple current is filtered by the output capacitor. Choosing high inductor ripple currents impacts the
selection of the output capacitor because the output capacitor must have a ripple current rating equal to or
greater than the inductor ripple current. The inductor ripple value is at the discretion of the designer, but the
following guidelines may be used.
For designs using low-ESR output capacitors such as ceramics, use a value as high as KIND = 0.3. When using
higher-ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current is part of the
current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable
PWM operation. In a wide input voltage regulator, choose a relatively large inductor ripple current. This provides
sufficient ripple current with the input voltage at the minimum.
For this design example, KIND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS
current and saturation current ratings of the inductor not be exceeded. See Equation 33 and Equation 34 for the
RMS and peak inductor current. For this design, the RMS inductor current is 5 A and the peak inductor current is
5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A and an RMS
current rating of 10 A. This inductor also has a typical inductance of 5.5 µH at no load and 4.8 µH at 5-A load.
Lastly, the inductor has a DCR of 10.3 mΩ.
As the equation set demonstrates, lower-ripple currents reduce the output voltage ripple of the regulator but
require a larger value of inductance. Selecting higher-ripple currents increases the output voltage ripple of the
regulator but allow for a lower-inductance value.

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The current flowing through the inductor is the inductor ripple current plus the output current. During powerup,
faults, or transient load conditions, the inductor current can increase above the peak inductor current level
calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative design approach is to choose an inductor with a saturation
current rating equal to or greater than the switch current limit of the TPS54541 device, which is nominally 7.5 A.
VIN(max ) - VOUT VOUT 42 V – 3.3 V 3.3 V
LO(min ) = ´ = ´ = 5.1 µH
IOUT ´ KIND VIN(max ) ´ ƒSW 5 A ´ 0.3 42 V ´ 400 kHz
(31)
spacer
VOUT ´ (VIN(max ) - VOUT ) 3.3 V ´ (42 V – 3.3 V)
IRIPPLE = = = 1.58 A
VIN(max ) ´ LO ´ ƒSW 42 V ´ 4.8 µH ´ 400 kHz
(32)
spacer

( )ö÷
2
æV
ç OUT ´ VIN(max ) - VOUT
2
1 1 æ 3.3 V ´ (42 V – 3.3 V ) ö
IL(rms ) = (IOUT ) + (5 A ) +
2 2
´ ç ÷ = ´ ç ÷ = 3.5 A
12 ç VIN(max ) ´ LO ´ ƒSW ç ÷
÷ 12 è 42 V ´ 4.8 µH ´ 400 kHz ø
è ø
(33)
spacer
IRIPPLE 1.58 A
IL(peak ) = IOUT + = 5A + = 5.79 A
2 2 (34)

8.2.1.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the following:
• The modulator pole
• The output voltage ripple
• How the regulator responds to a large change in load current
Select the output capacitance based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor must to
supply the increased load current until the regulator responds to the load step. A regulator does not respond
immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The
regulator usually requires two or more clock cycles for the control loop to sense the change in output voltage and
adjust the peak switch current in response to the higher load. The output capacitance must be large enough to
supply the difference in current for two clock cycles to maintain the output voltage within the specified range.
Equation 35 shows the minimum output capacitance necessary, where ΔIOUT is the change in output current, ƒsw
is the switching frequency of the regulators and ΔVOUT is the allowable change in the output voltage. For this
example, the transient load response is specified as a 4% change in VOUT for a load step from 1.25 A to 3.75 A.
ΔIOUT is 3.75 A – 1.25 A = 2.5 A and ΔVOUT = 0.04 × 3.3 V = 0.13 V. These values provide a minimum
capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage
change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and
tantalum capacitors have higher ESR that must be included in load step calculations.
The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to
low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can
produce an output voltage overshoot when the load current rapidly decreases. Figure 51 shows a typical load
step response. The excess energy absorbed in the output capacitor increases the voltage on the capacitor. The
capacitor must be sized to maintain the output voltage during these transient periods. Equation 36 calculates the
minimum capacitance required to keep the output voltage overshoot to a desired value, where LO is the value of
the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the peak output
voltage and Vi is the initial voltage. For this example, the worst case load step is from 3.75 A to 1.25 A. The
output voltage increases during this load transition and the stated maximum in our specification is 4% of the
output voltage. This makes Vf = 1.04 × 3.3 V = 3.43 V. VI is the initial capacitor voltage which is the nominal
output voltage of 3.3 V. The values in Equation 36 yield a minimum capacitance of 68 μF.

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Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,
where ƒsw is the switching frequency, VORIPPLE is the maximum allowable output voltage ripple, and IRIPPLE is the
inductor ripple current. Equation 37 yields 30 μF.
Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 38 indicates the equivalent ESR should be less than 10 mΩ.
The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within
regulation tolerance during a load transient.
Capacitance de-ratings for aging, temperature, and DC bias increases this minimum value. For this example, two
100-μF 6.3-V type X5R ceramic capacitors with 2 mΩ of ESR are used. The derated capacitance is 130 µF, well
above the minimum required capacitance of 95 µF.
Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor
reliability, especially non ceramic capacitors. Some capacitor data sheets specify the Root Mean Square (RMS)
value of the maximum ripple current. Equation 39 can calculate the RMS ripple current that the output capacitor
must support. For this example, Equation 39 yields 460 mA.
2 ´ DIOUT 2 ´ 2.5 A
COUT > = = 95 mF
fSW ´ DVOUT 400 kHz x 0.13 V (35)

COUT > LO x
((I ) - (I ) ) = 4.8 mH x (3.75 A - 1.25 A ) = 68 mF
OH
2
OL
2 2 2

((V ) - (V ) )
f
2
I
2
(3.43 V - 3.3 V ) 2 2
(36)
1 1 1 1
COUT > ´ = x = 30 mF
8 ´ fSW æ VORIPPLE ö 8 x 400 kHz æ 16 mV ö
ç ÷ ç 1.58 A ÷
è IRIPPLE ø è ø (37)
V 16 mV
RESR < ORIPPLE = = 10 mW
IRIPPLE 1.58 A (38)

ICOUT(rms) =
(
VOUT ´ VIN(max ) - VOUT )= 3.3 V ´ (42 V - 3.3 V )
= 460 mA
12 ´ VIN(max ) ´ LO ´ fSW 12 ´ 42 V ´ 4.8 mH ´ 400 kHz
(39)

8.2.1.2.4 Catch Diode

The TPS54541 device requires an external catch diode between the SW pin and GND. The selected diode must
have a reverse voltage rating equal to or greater than VIN(max). The peak current rating of the diode must be
greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due
to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.
Typically, diodes with higher voltage and current ratings have higher forward voltages. TI recommends a diode
with a minimum of 42-V reverse voltage to allow input voltage transients up to the rated voltage of the TPS54541
device.
For the example design, the PDS760 Schottky diode is selected for its lower forward voltage and good thermal
characteristics compared to smaller devices. The typical forward voltage of the PDS760 is 0.52 V at 5 A and
25°C.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher
switching frequencies, consider the AC losses of the diode. The AC losses of the diode are due to the charging
and discharging of the junction capacitance and reverse recovery charge. Equation 40 calculates the total power
dissipation, including conduction losses and AC losses of the diode.
The PDS760 diode has a junction capacitance of 180 pF. Using Equation 40, the total loss in the diode at the
nominal input voltage is 1.89 W.

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If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a
diode, which has a low leakage current and slightly higher forward voltage drop.
2
(VIN - VOUT ) ´ IOUT ´ V ƒd C j ´ ƒSW ´ (VIN + Vƒ d)
PD = + =
VIN 2
(12 V - 3.3 V) ´ 5 A´ 0.52 V 180pF ´ 400kHz ´ (12 V + 0.52 V)2
+ = 1.89 W
12 V 2 (40)

8.2.1.2.5 Input Capacitor

The TPS54541 device requires a high-quality ceramic-type X5R or X7R input decoupling capacitor with at least 3
μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective
capacitance includes any loss of capacitance due to DC bias effects. The voltage rating of the input capacitor
must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater
than the maximum input current ripple of the TPS54541 device. Use Equation 41 to calculate the input ripple
current.
The value of a ceramic capacitor varies significantly with temperature and the DC bias applied to the capacitor.
The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more
stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor
must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC
bias across a capacitor increases.
For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients
up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V,
16 V, 25 V, 50 V, or 100 V. This example uses four 4.7-μF 50-V capacitors in parallel. Table 2 shows several
choices of high-voltage capacitors.
The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage
ripple occurs at 50% duty cycle and can be calculated using Equation 42. Using the design example values, IOUT
= 5 A, CIN = 18.8 μF, ƒSW = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of
2.5 A.

ICI(rms ) = IOUT x
VOUT
x
(V
IN(min ) - VOUT ) = 5A 3.3 V
´
(6 V - 3.3 V )
= 2.5 A
VIN(min ) VIN(min ) 6V 6V
(41)
I ´ 0.25 5 A ´ 0.25
DVIN = OUT = = 170 mV
CIN ´ fSW 18.8 mF ´ 400 kHz (42)

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Table 2. Capacitor Types

VENDOR VALUE (μF) EIA Size VOLTAGE (V) DIALECTRIC COMMENTS
1 to 2.2 100
1210 GRM32 series
1 to 4.7 50
Murata
1 100
1206 GRM31 series
1 to 2.2 50
1 to 1.8 50
2220
1 to 1.2 100
Vishay VJ X7R series
1 to 3.9 50
2225
1 to 1.8 100
X7R
1 to 2.2 100
1812 C series C4532
1.5 to 6.8 50
TDK
1 to 2.2 100
1210 C series C3225
1 to 3.3 50
1 to 4.7 50
1210
1 100
AVX X7R dielectric series
1 to 4.7 50
1812
1 to 2.2 100

8.2.1.2.6 Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time for the output voltage to reach its nominal
programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This capacitor
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54541 device reach the current limit or excessive current draw from the input power supply may cause the
input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 43 can be used to find the minimum slow\-start time, Tss,
necessary to charge the output capacitor, COUT, from 10% to 90% of the output voltage, VOUT, with an average
slow start current of ISSavg. In the example, to charge the effective output capacitance of 130 µF up to 3.3 V with
an average current of 1 A requires a 0.3-ms slow-start time.
When the slow-start time is known, the slow-start capacitor value can be calculated using Equation 5. For the
example circuit, the slow-start time is not critical because the output capacitor value is two-times 100 μF which
does not require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary
value of 3.5 ms which requires a 9.3-nF slow-start capacitor calculated with Equation 44. For this design, the
next larger standard value of 10 nF is used.
Cout ´ Vout ´ 0.8
tss >
Issavg (43)
TSS (ms) ´ ISS (µA) 1.7 µA
CSS (nF) = = 3.5 ms ´ = 9.3 nF
VREF (V) ´ 0.8 (0.8 V ´ 0.8 ) (44)

8.2.1.2.7 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins. TI recommends a ceramic
capacitor with X5R or better grade dielectric. The capacitor must have a 10 V or higher voltage rating.

8.2.1.2.8 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54541 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the supply must turn on and
start switching when the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it
must continue until the input voltage falls below 4.5 V (UVLO stop).

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Programmable UVLO threshold voltages are set using the resistor divider of RUVLO1 and RUVLO2 between VIN and
ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values. For the example
application, a 365 kΩ between VIN and EN (RUVLO1) and a 88.7 kΩ between EN and ground (RUVLO2) are required
to produce the 5.75-V and 4.5-V start and stop voltages.
V - VSTOP 5.75 V - 4.5 V
RUVLO1 = START = = 368 kW
IHYS 3.4 mA (45)
VENA 1.2 V
RUVLO2 = = = 88.7 kW
VSTART - VENA 5.75 V - 1.2 V
+ I1 + 1.2 mA
RUVLO1 365 kW (46)

8.2.1.2.9 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.
Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input
current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the
accuracy of the output voltage. If the value of R6 is less than 800 kΩ, this requirement is satisfied. Choosing
higher-resistor values decreases quiescent current and improves efficiency at low-output currents but may also
introduce noise immunity problems.
V - 0.8 V æ 3.3 V - 0.8 V ö
RHS = RLS x OUT = 10.2 kW x ç ÷ = 31.9 kW
0.8 V è 0.8 V ø (47)

8.2.1.2.10 Compensation
There are several methods to design compensation for DC-DC regulators. The method is simple to calculate and
ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is
ignored, the actual crossover frequency is lower than the crossover frequency in the calculations. This method
assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least
ten-times greater the modulator pole.
To get started, calculate the modulator pole, ƒp(mod), and the ESR zero, ƒz1 using Equation 48 and Equation 49.
For COUT, use a derated value of 130 μF. Use equations Equation 50 and Equation 51 to estimate a starting
point for the crossover frequency, ƒco. For the example, design, ƒp(mod) is 1850 Hz and ƒz(mod) is 610 kHz.
Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of
modulator pole and half of the switching frequency. Equation 50 yields 34 kHz and Equation 51 gives 19 kHz.
Use the geometric mean value of Equation 50 and Equation 51 for an initial crossover frequency. For this
example, after lab measurement, the crossover frequency target increased to 30 kHz for an improved transient
response.
Next, calculate the compensation components. A resistor in series with a capacitor creates a compensating zero.
In parallel to these two components, a capacitor forms the compensating pole.
IOUT(max ) 5A
fP(mod) = = = 1850 Hz
2 ´ p ´ VOUT ´ COUT 2 ´ p ´ 3.3 V ´ 130 mF (48)
1 1
f Z(mod) = = = 610 kHz
2 ´ p ´ RESR ´ COUT 2 ´ p ´ 1 mW ´ 130 mF (49)
fco1 = fp(mod) x f z(mod) = 1850 Hz x 610 kHz = 34 kHz
(50)
fSW 400 kHz
fco2 = fp(mod) x = 1850 Hz x = 19 kHz
2 2 (51)
To determine the compensation resistor, R4, use Equation 52. The typical power stage transconductance, gmps,
is 17 A/V. The output voltage, VO, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8
V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use
Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5100 pF for
compensating capacitor C5. 4700 pF is used for this design.

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æ 2 ´ p ´ ƒco ´ COUT ö æ VOUT ö æ 2 ´ p ´ 30 kHz ´ 130 µF ö æ 3.3 V ö

R4 = ç ÷ ´ ç ÷ = ç ÷ ´ ç 0.8 V ´ 350 µA / V ÷ = 17 kW
ç gmps ÷ V
è REF x gm ea ø è 17 A / V ø è ø
è ø
(52)
1 1
C5 = = = 5100 pF
2 ´ p ´ R4 x fp(mod) 2 ´ p ´ 16.9 kW x 1850 Hz (53)
A compensation pole can be implemented by adding capacitor C8 in parallel with the series combination of R4
and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole.
The value of C8 is 47 pF for this design example.
C x RESR 130 mF x 1 mW
C8 = OUT = = 15 pF
R4 16.9 kW (54)
1 1
C8 = = = 47 pF
R4 ´ ƒsw ´ p 16.9 kW ´ 400 kHz ´ p (55)

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8.2.1.2.11 Power Dissipation Estimate

The following formulas estimate the TPS54541 power dissipation under CCM operation. Do not use these
equations if the device is operating in DCM.
The power dissipation of the IC includes conduction loss (PCOND), switching loss (PSW), gate drive loss (PGD), and
supply current (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.
æV ö 5V
PCOND = (IOUT ) ´ RDS(on ) ´ ç OUT ÷ = 5 A 2 ´ 87 mW ´
2
= 0.958 W
è VIN ø 12 V (56)
spacer
PSW = VIN ´ fSW ´ IOUT ´ trise = 12 V ´ 400 kHz ´ 5 A ´ 4.9 ns = 0.118 W (57)
spacer
PGD = VIN ´ QG ´ fSW = 12 V ´ 3nC ´ 400 kHz = 0.014 W (58)
spacer
PQ = VIN ´ IQ = 12 V ´ 146 mA = 0.0018 W

where (for Equation 56, Equation 57, Equation 58, and Equation 59)
• IOUT is the output current (A)
• RDS(on) is the on-resistance of the high-side MOSFET (Ω)
• VOUT is the output voltage (V)
• VIN is the input voltage (V)
• ƒsw is the switching frequency (Hz)
• trise is the SW pin voltage rise time and can be estimated by trise = VIN x 0.16 ns/V + 3 ns
• QG is the total gate charge of the internal MOSFET
• IQ is the operating nonswitching supply current (59)
Therefore,
PTOT = PCOND + PSW + PGD + PQ = 0.958 W + 0.118 W + 0.014 W + 0.0018 W = 1.092 W (60)
For given TA,
TJ = TA + RTH ´ PTOT (61)
For given TJ(MAX) = 150°C
TA (max ) = TJ(max ) - RTH ´ PTOT

where (for Equation 60, Equation 61, and Equation 62)

• PTOT is the total device power dissipation (W)
• TA is the ambient temperature (°C)
• TJ is the junction temperature (°C)
• RTH is the thermal resistance from junction to ambient for a given PCB layout (°C/W)
• TJ(MAX) is maximum junction temperature (°C)
• TA(MAX) is maximum ambient temperature (°C) (62)
Additional power loss occurs in the regulator circuit due to the inductor ac and dc losses and the catch diode and
PCB trace resistance impacting the overall efficiency of the regulator.

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8.2.1.2.12 Safe Operating Area

Figure 47 shows the safe operating area (SOA) of a typical design, through Figure 50 for 3.3-V, 5-V, and 12-V
outputs and varying amounts of forced air flow. The temperature-derating curves represent the conditions at
which the internal components and external components are at or below the maximum operating temperatures of
the manufacturer. Derating limits apply to devices soldered directly to a double-sided PCB with 2-oz copper,
similar to the EVM. Pay attention to the other components chosen for the design, especially the catch diode. In
most applications, the thermal performance is limited by the catch diode. When operating at high-duty cycles or
in the high end of the switching frequency range, the thermal performance of the TPS54541 can be the limiting
factor.

90 90

80 80

70 70

60 60
TA (ƒC)

TA (ƒC)
50 50
6V 8V
40 40
12 V 12 V
30 24 V 30 24 V
36 V 36 V
20 20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT (Amps) C056 IOUT (Amps) C057

Figure 47. 3.3-V Outputs Figure 48. 5-V Outputs

90 90

80 80

70 70

60 60
TA (ƒC)

TA (ƒC)

fsw = 800 kHz

50 50
400 LFM
18 V
40 40 200 LFM
24 V 100 LFM
30 30
36 V Nat Conv
20 20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
IOUT (Amps) C058 IOUT (Amps) C048

Figure 49. 12-V Outputs Figure 50. Air Flow Conditions

VIN = 36 V, VO = 12 V, fsw = 800 kHz

8.2.1.2.13 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current
is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input
current draw is 260 μA with no load.

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8.2.1.3 Application Curves

Measurements are taken with standard EVM using a 12-V input, 3.3-V output, and 5-A load unless otherwise
noted.

10 V/div
IOUT
1 A/div

VIN

VOUT ±3.3V offset

10 mV/div
100 mV/div

VOUT ±3.3V offset

Time = 100 Ps/div Time = 4 ms/div

Figure 51. Load Transient Figure 52. Line Transient (8 V to 40 V)

VIN
5 V/div
2 V/div

EN

VOUT
2 V/div

Time = 20 ms/div
Figure 53. Start-up With VIN Figure 54. Start-up With EN

SW
10 V/div

10 V/div

SW
500 mA/div
1 A/div

IL

IL
10 mV/div

10 mV/div

VOUT ± AC Coupled
VOUT ± AC Coupled

IOUT = 100 mA

Time = 4 Ps/div Time = 4 Ps/div

Figure 55. Output Ripple CCM Figure 56. Output Ripple DCM

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SW

10 V/div
10 V/div

SW

1 A/div
200 mA/div

IL
IL

200 mV/div
10 mV/div

VOUT ± AC Coupled

No Load
VIN ± AC Coupled

Time = 1 ms/div Time = 4 Ps/div

Figure 57. Output Ripple PSM Figure 58. Input Ripple CCM

SW

2 V/div
10 V/div

IL SW
500 mA/div

200 mA/div

IL
10 mV/div

VOUT = 5 V
20 mV/div

VIN ± AC Coupled No Load

IOUT = 100 mA VIN = 5.5 V EN Floating

Time = 4 Ps/div Time = 40 Ps/div

Figure 59. Input Ripple DCM Figure 60. Low Dropout Operation

IOUT = 100 mA IOUT = 1 A

EN Floating EN Floating
2 V/div
2 V/div

VIN VIN

VOUT VOUT

Time = 40 ms/div Time = 40 ms/div

Figure 61. Low Dropout Operation Figure 62. Low Dropout Operation

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100 100

95 90
80
90
70
Efficiency (%)

Efficiency (%)
85 60
80 50

75 40
30
70 VIN
VIN ==77VV VIN
VIN == 77VV
VIN
VIN ==12
12VV 20 VIN
VIN == 12
12VV
65 VIN ==24
VIN 24VV 10 VOUT = ñ sU •SW = 400 kHz VIN == 24
VIN 24VV
VOUT = ñ sU •SW = 400 kHz VIN ==36
VIN 36VV VIN == 36
VIN 36VV
60 0
0 1 2 3 4 5 0.001 0.01 0.1 1
Output Current (A) C001 Output Current (A) C002

Figure 63. Efficiency vs Load Current Figure 64. Light Load Efficiency

100 100

95 90
80
90
70
Efficiency (%)

Efficiency (%)
85 60
80 50

75 40
30
70 VIN
VIN =
=66VV VIN
VIN == 66 V
V
VIN
VIN = 12 V 20 VIN
VIN == 12
12 VV
65 VIN = 24 V
VIN 10 VIN == 24
VIN 24 VV
VOUT = 3.3 sU •SW = 400 kHz VOUT = 3.3 sU •SW = 400 kHz
VIN =
VIN = 36
36 V
V VIN == 36
VIN 36 VV
60 0
0 1 2 3 4 5 0.001 0.01 0.1 1
Output Current (A) C003 Output Current (A) C006

Figure 65. Efficiency vs Load Current Figure 66. Light Load Efficiency

100 60 180
50 150
95
40 120
90 30 90
20 60
Efficiency (%)

85
Gain (dB)

Phase (£)
10 30
0 0
80
±10 ±30
75 ±20 ±60
V IN = 18 V
18in VIN = 12 V
±30 ±90
70 VOUT = 3.3 V
Series1
V ±40 ±120
IN = 24 V IOUT = 5 A Gain
65 ±50 fSW = 400 kHz ±150
VOUT = 12 V, fsw = 800 kHz Series3 Phase
V IN = 36 V ±60 ±180
60 10 100 1k 10k 100k 1M
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Frequency (Hz) C064

IO - Output Current (A) C024

Figure 67. Efficiency vs Output Current Figure 68. Overall Loop Frequency Response

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0.10 0.10
0.08 VIN = 12 V 0.08
VOUT = 3.3 V

Output Voltage Deviation (%)

Output Voltage Deviation (%)

0.06 fsw = 400 kHz 0.06

0.04 0.04
0.02 0.02
0.00 0.00
±0.02 ±0.02
±0.04 ±0.04
±0.06 ±0.06
±0.08 ±0.08
±0.10 ±0.10
0 1 2 3 4 5 0 5 10 15 20 25 30 35 40 45
Output Current (A) C065 Input Voltage (V) C066

Figure 69. Regulation vs Load Current Figure 70. Regulation vs Input Voltage

8.2.2 Inverting Buck-Boost Topology for Positive Input to Negative Output

The TPS54541 can be used to convert a positive input voltage to a negative output voltage. An example
application is an amplifier requiring a negative power supply. For a more detailed example, see SLVA317.
VIN +
Cin
Cboot
Lo
VIN BOOT SW GND
Cd R1
GND +
R2 Co
TPS54541
FB
VOUT
EN

SS/TR COMP
RT/CLK Rcomp

Czero Cpole
CSS RT

Figure 71. TPS54541 Inverting Power Supply Based on the Application Note, SLVA317

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8.2.3 Split-Rail Topology for Positive Input to Negative and Positive Output
The TPS54541 can be used to convert a positive input voltage to a split rail positive and negative output voltage
by using a coupled inductor. An example application is an amplifier requiring a split rail positive and negative
voltage power supply. For a more detailed example, see SLVA369.

VOPOS
+
VIN + Copos
Cin
Cboot
GND
VIN BOOT SW
Lo
Cd R1
+
GND Coneg
TPS54541 R2
FB VONEG
EN
SS/TR COMP
RT/CLK Rcomp

Czero Cpole
CSS RT

Figure 72. TPS54541 Split Rail Power Supply Based on the Application Note, SLVA369

9 Power Supply Recommendations

The design of the device is for operation from an power supply range between 4.5 V and 42 V. The power supply
voltage must remain within this range. If the power supply is more distant than a few inches from the TPS54541
converter, the circuit may require additional bulk capacitance besides the ceramic bypass capacitors. An
electrolytic capacitor with a value of 100 µF is a typical choice.

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10 Layout

10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast-
changing currents or voltages that interact with stray inductance or parasitic capacitance to generate noise or
degrade performance. To reduce parasitic effects, bypass the VIN pin to ground with a low-ESR ceramic bypass-
capacitor with X5R or X7R dielectric. Minimize the loop area formed by the bypass-capacitor connections, the
VIN pin, and the anode of the catch diode. See Figure 73 for a PCB layout example. Tie the GND pin directly to
the power pad under the IC and the power pad.
Connect the power pad to internal PCB ground planes using multiple vias directly under the IC. Route the SW
pin to the cathode of the catch diode and to the output inductor. Because the SW connection is the switching
node, locate the catch diode and output inductor close to the SW pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. For operation at full rated load, ensure the top-side ground
area provides adequate heat dissipating area. The RT/CLK pin is sensitive to noise so locate and rout the RT
resistor as close as possible to the IC with minimal lengths of trace, respectively. The additional external
components are placed approximately as shown. Obtaining acceptable performance with alternate PCB layouts
is possible, however this layout produces good results and TI intends it as a guideline.

10.2 Layout Example

VOUT

Output
Capacitor Output
Topside Inductor
Ground Route Boot Capacitor
Area Catch
Trace on another layer to
provide wide path for Diode
topside ground

Input
Bypass
Capacitor BOOT PWRGD
VIN
VIN SW

EN GND

UVLO SS/TR COMP

Adjust
Resistors FB
RT/CLK Compensation
Resistor
Network
Divider

Thermal VIA
Soft-Start Frequency
Capacitor Set Resistor Signal VIA

Figure 73. PCB Layout Example

10.3 Estimated Circuit Area

Boxing in the components in the design of Figure 46 the estimated printed circuit board area is 1.025 in2 (661
mm2). This area does not include test points or connectors.

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.1.2 Development Support

For the TPS54540, TPS54541, and TPS54541-Q1 family Excel design tool, see SLVC452.
For the WEBENCH Design Center, go to www.ti.com/WEBENCH.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation, see the following:
• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317
• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369
• Evaluation Module for the TPS54541 Step-Down Converter, SLVU990
• Creating a Universal Car Charger for USB Devices From the TPS54240 and TPS2511, SLVA464
• Creating GSM /GPRS Power Supply from TPS54260, SLVA412

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS54541DPRR ACTIVE WSON DPR 10 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
& no Sb/Br) 54541
TPS54541DPRT ACTIVE WSON DPR 10 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
& no Sb/Br) 54541

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 5-Feb-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54541DPRR WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS54541DPRT WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Feb-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54541DPRR WSON DPR 10 3000 367.0 367.0 35.0
TPS54541DPRT WSON DPR 10 250 210.0 185.0 35.0

Pack Materials-Page 2
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