Vlsi Report
Vlsi Report
1.0 : VLSI
Architecture Design
Behavioral / Functional
Design
Physical design
Fabrication
INTRODUCTION TO HDL
3.0 : HDL
gates, simple 1-bit dynamic and static memories. They can be used to build up
larger designs to simulate at the circuit level, to design performance critical circuit.
Verilog and VHDL are the two primary HDLs used in VLSI
design, each with its strengths and weaknesses. This section
provides a comparative analysis of Verilog and VHDL, focusing
on aspects such as:
Usage: Verilog is often preferred for its ease of use and familiarity
among designers, especially in industry settings where
productivity and efficiency are paramount. VHDL, on the other
hand, is favored in academic and military contexts for its rigorous
language constructs and formal verification capabilities.
Design Methodologies
Advantages:
advantages:
Verilog offers several tools for managing simulation, such as the ability to start and
stop the simulation, selectively monitor operations, test the design for temporal
limitations, and more. Though Verilog has a wide range of these constructs.
5.0 : PARAMETERS
According to Verilog, a parameter is a constant value stated inside a module's
structure. The constant value represents wiring, range of variables, timing values, etc.
You can specify and modify the parameter values to fit the test or design
environment. These modifications take effect at instantiation and are frozen.
Neither testing nor synthesis can modify the assigned values.
Two types of parameters are of use in modules: specparam and defparam.
Specparam : Parameters related to timings, time delays, rise and fall times, etc., are
technology- specific and used during simulation. Parameter values can be assigned
or overridden with the keyword “specparam” preceding the assignments.
Defparam: Parameters related to design, bus width, and register size are of a
different category. They are related to the size or dimension of a specific design;
they are technology-independent. Assignment or overriding is with assignments
following the keyword “defparam”.
Module Paths: Module Path delays are assigned in Verilog within the keywords
specify and endspecify. The statements within these keywords constitute a specify
block.
Module paths can be specified in different ways inside a specify block.
Parallel connection: Every path delay statement has a source field and a destination
field.
A parallel connection is specified by the symbol => and is used as shown below.
Usage: ( <source_field> => <destination_field>) = <delay_value>;
In a parallel connection, each bit in source field connects to its corresponding bit in
the destination field.
If the source and the destination fields are vectors, they must have the same number of
bits; otherwise, there is a mismatch. Thus, a parallel connection specifies delays from
each bit in source to each bit in destination.
Example: Parallel Connection
(a => out) = 9; //bit-to-bit connection. Both a and out are single-bit
// vector connection. Both a and out are 4-bit vectors a[2:0], out[2:0] a is source field,
out is destination field.
Full connection
A full connection is specified by the symbol *> and is used as shown below.
Usage: ( <source_field> *> <destination_field>) = <delay_value>;
In a full connection, each bit in the source field connects to every bit in the
destination field. If the source and the destination are vectors, then they need not
have the same number of bits. A full connection describes the delay between each
bit of the source and every bit in the destination.
Example:
Figure below illustrates a case of all possible paths from
a 2-bit vector A to another 2-bit vector B; the specification implies 4 pa