UART

• Computer must be able to communicate with other

computers in modern multiprocessor distributed
systems
• One cost effective way to communicate is to send
and receive data bits serially
• The 8051 microcontroller has a serial data
communication circuit that uses register SBUF to
hold data
• SCON controls data communication
• Reg. PCON control data rates and pins RXD &
TXD connect to serial data n/w
 P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2)
P0.3(AD3)
P1.5 6 (8031) 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
 Data transmission

• Transmission of serial data bits begins any time ,data is

written to SBUF.
• TI is set to a 1 when the data has been transmitted and
signifies that SBUF is empty (for transmission purpose)
and that another data byte can be sent .
• If the program fails to wait for the TI flag and
overwrites SBUF while a previous data bytes is in the
process of being transmitted, the result will be
unpredictable .
 Data reception
• Reception of serial data will begine if the receive enable
bit (REN)in SCON is set –1 for all modes
• In addition for mode 0 only RI must be cleared to 0
also.
• Receive interrupt flag RI is set after data has been
received in ll modes, setting REN is the only direct
program control that limits the reception of unexpected
dta;the requirement that RI also be 0 for mode 0 prevents
the reception of new data until the program has dealt
with the old data and reset RI.
 Baud Rate Generator (BRG)
• Independent Baud Rate Generator integrated into UART
• Core of the BRG is a 16-bit baud rate divisor value that
works in a similar manner as Timer 1
• If baud rate generator is used, Timer 1 can be used for
other timing functions
• The UART can use either Timer 1 or the baud rate
generator output

(T1 uses PCLK)

(BRG uses OSCCLK)

Mode - 0
In Mode 0, a write to SBUF will initiate a
transmission. At the end of the transmission,
TI (SCON.1) is set, which must be cleared in
software.
 Double buffering must be disabled in this
mode. Reception is initiated by clearing RI
(SCON.0).
Synchronous serial transfer occurs and RI will
be set again at the end of the transfer. When
RI is cleared, the reception of the next
character will begin.
Refer to Figure 10-5 for timing.
Mode-1
 Reception is initiated by detecting a 1-to-0 transition on
RxD. RxD is sampled at a rate 16 times the programmed
baud rate.
 When a transition is detected, the divide-by-16 counter is
immediately reset. Each bit time is thus divided into 16
counter states.
 At the 7th, 8th, and 9th counter states, the bit detector
samples the value of RxD. The value accepted is the value
that was seen in at least 2 of the 3 samples. This is done for
noise rejection.
 If the value accepted during the first bit time is not 0, the
receive circuits are reset and the receiver goes back to
looking for another 1-to-0 transition. This provides
rejection of false start bits. If the start bit proves valid, it is
shifted into the input shift register, and reception of the rest
of the frame will proceed.
• The signal to load SBUF and RB8, and to
set RI, will be generated if, and only if, the
following conditions are met at the time the
final shift pulse is generated: RI = 0 and
either SM2=0 or the received stop bit =1. If
either of these two conditions is not met, the
received frame is lost. If both conditions are
met, the stop bit goes into RB8, the 8 data
bits go into SBUF, and RI is activated.
Mode 2&3
• Reception is the same as in Mode 1.
• The signal to load SBUF and RB8, and to
set RI, will be generated if, and only if, the
following conditions are met at the time the
final shift pulse is generated.
• (a) RI = 0, and (b) Either SM2 = 0, or the
received 9th data bit = 1. If either of these
conditions is not met, the received frame is
lost, and RI is not set. If both conditions are
met, the received 9th data bit goes into
RB8, and the first 8 data bits go into SBUF.
 Multiprocessor
communications
• UART modes 2 and 3 have a special provision for
multiprocessor communications. In these modes, 9
data bits are received or transmitted.
• When data is received, the 9th bit is stored in RB8.
The UART can be programmed such that when
the stop bit is received, the serial port interrupt
will be activated only if RB8 = 1.
• This feature is enabled by setting bit SM2 in
SCON. One way to use this feature in
multiprocessor systems is as follows
• When the master processor wants to transmit a block of data
to one of several slaves, it first sends out an address byte
which identifies the target slave.
• An address byte differs from a data byte in that the 9th bit is
1 in an address byte and 0 in a data byte. With SM2 = 1, no
slave will be interrupted by a data byte.
• An address byte, however, will interrupt all slaves, so that
each slave can examine the received byte and see if it is
being addressed. The addressed slave will clear its SM2 bit
and prepare to receive the data bytes that follow. The slaves
that weren’t being addressed leave their SM2 bits set and go
on about their business, ignoring the subsequent data bytes.

• Note that SM2 has no effect in Mode 0, and must be ‘0’ in

Mode 1.
 Automatic address recognition
• Automatic address recognition is a feature which allows
the UART to recognize certain addresses in the serial bit
stream by using hardware to make the comparisons.
• This feature saves a great deal of software overhead by
eliminating the need for the software to examine every
serial address which passes by the serial port.
• This feature is enabled by setting the SM2 bit in SCON. In
the 9 bit UART modes (mode 2 and mode 3), the Receive
Interrupt flag (RI) will be automatically set when the
received byte contains either the “Given” address or the
“Broadcast” address. The 9 bit mode requires that the 9th
information bit is a 1 to indicate that the received
information is an address and not data.
• Using the Automatic Address Recognition feature allows a
master to selectively communicate with one or more slaves
by invoking the Given slave address or addresses.
• All of the slaves may be contacted by using the Broadcast
address. Two special Function Registers are used to define
the slave’s address, SADDR, and the address mask,
SADEN. SADEN is used to define which bits in the
SADDR are to be used and which bits are “don’t care”.
• The SADEN mask can be logically ANDed with the
SADDR to create the “Given” address which the master
will use for addressing each of the slaves. Use of the Given
address allows multiple slaves to be recognized while
excluding others. The following examples will help to
show the versatility of this scheme:
• In the above example SADDR is the same and the
SADEN data is used to differentiate between the
two slaves. Slave 0 requires a 0 in bit 0 and it
ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0
is ignored. A unique address for Slave 0 would be
1100 0010 since slave 1 requires a 0 in bit 1. A
unique address for slave 1 would be 1100 0001
since a 1 in bit 0 will exclude slave 0. Both slaves
can be selected at the same time by an address
which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for
slave 1). Thus, both could be addressed with 1100
0000.