FPGA Based Design Lab (EE-

429L) (Fall - 2024)

Lab Report # 04

Submitted By:

Name: Muhammad Abdullah

Roll No: 215143

Submitted To:
Engr. Bakht Muhammad Khan

Department of Electrical Engineering

Air University Aerospace and Aviation Campus,
Kamra
 EXPERIMENT NO 04

Implement and investigate half adder, full adder, half Subtractor and full
Subtractor at different abstraction level Verilog coding using Nexys A7
development Board
Objective:
 Verify that the Xilinx tools are up and running
 Introduce you to the Xilinx Vivado software.
 Become familiar with Verilog coding and use of the Vivado tool.
 Be able to synthesize and implement Verilog designs to FPGAs.

Equipment’s:
Following are the lab equipment’s that will be used in this lab. These
equipment’sinclude
Hardware tools:
• FPGA kit (Nexys7 DDR2™ FPGA,Xilinx)
• USB cable
Software tools:
 Vivado 2018.2 should be installed in PC’s or Laptop

OVERVIEW

Half adder:
An adder is a digital logic circuit in electronics that implements addition of numbers. In many
computers and other types of processors, adders are used to calculate addresses, similar operations
and table indices in the ALU and also in other parts of the processors. These can be built for many
numerical representations like excess-3 or binary coded decimal. Adders are classified into two
types: half adder and full adder. The half adder circuit has two inputs: A and B, which add two
input digits and generate a carry and sum.

Full adder
If you want to add two or more bits together it becomes slightly harder. In this case, we
need to create a full adder circuit. The difference between a full adder and a half adder
we looked at is that a full adder accepts inputs A and B plus a carry-in (CN-1) giving
outputs Q and CN. Once we have a full adder, then we can string eight of them together to
create a byte-wide adder and cascade the carry bit from one adder to the next. The logic
table for a full adder is slightly more complicated than the tables we have used before,
because now we have 3 input bits.
 LAB TASKS
Task#01: Construct a project within Vivado, assigning 'Your Name' as the project title
and 'Logic_Name' as the Module name, and proceed to develop a Verilog code for the subsequent operation:
Full Subtractor circuit

 Verilog Code & Constraint file:

 Test Bench:
  Timing Diagram:

 RTL Schematic & Hardware Results:

Task#02: Establish a project in Vivado, labeling it 'Your Name' and the Module as
'Logic_Name,' then formulate and evaluate a Verilog code (Structural) for the subsequent operations:"

1. 4-bit’s binary adder circuit by cascading 4 blocks of full adder logic

  Verilog Code:

Test Bench:

 Constraint file:
  Timing Diagram:

 RTL Schematic:

 Hardware Results:

2. 4-bit’s binary Subtractor circuit by cascading 4 blocks of full Subtractor logic

 Verilog Code:
 RTL Schematic:

 Timing Diagram:

 Constraint file, Test Bench & Hardware Results:

Task#03: Construct a project within Vivado, assigning 'Your Name' as the project title
and 'Logic_Name' as the Module name, and proceed to develop a Verilog code for the subsequent operation:

 Binary Adder - Subtractor circuit

Where there is a single control input (Selection Line)

 Verilog code
 Constraint file ( .xdc)

 RTL Schematic Diagram

 Test bench

 Timing Diagram

 Hardware Results
 Truth Table
A B Sel Result CarryOut Operation
0010 0001 0 0011 0 Addition
0011 0001 1 0010 0 Subtraction
0100 0011 0 0111 0 Addition
0101 0011 1 0010 0 Subtraction
1001 0110 1 0011 0 Subtraction

ANALYSIS QUESTIONS:

1. How half adder is different from full adder circuit?

Ans: A half adder performs the addition of two single-bit binary numbers, producing a sum and a
carry output, but it cannot account for any carry input from previous additions. In contrast, a full
adder adds three single-bit binary numbers (two operands and a carry-in), generating a sum and a
carry output.
2. How we can implement 8-bit full adder using 1-bit full adders or 1-bit half adders?
Ans: An 8-bit full adder can be implemented by cascading eight 1-bit full adders, connecting the
carry output of each bit to the carry input of the next. Starting with the least significant bit, the first
1-bit full adder’s carry-in is set to 0. Each 1-bit full adder then adds the corresponding bits of the two
8-bit numbers, along with the carry from the previous adder, producing an 8-bit sum and a final
carry-out. Half adders alone aren’t suitable, as they lack a carry-in input, which is necessary for
multi-bit addition.
3. Enlist some applications of half and full subtractor ?
Ans:
Applications of Half Adder
a) Simple binary addition: Adding the least significant bits of two binary numbers.

b) Digital measuring devices: Used in basic digital measurement circuits due to their simple
design.

c) Early stages of digital circuit design: Their simplicity makes them suitable for initial design
phases.
Applications of Full Adder
a) Arithmetic Logic Unit (ALU): The core component for performing addition operations in a
CPU.
b) Complex binary addition: Adding multiple binary digits, including handling carry bits from
previous additions.

c) Memory address generation: Calculating memory addresses in a computer system

d) Program counter incrementing: Incrementing the program counter during execution

e) Digital calculators: Used in the internal circuitry of calculators to perform binary addition

CONCLUSION:

1. Half Adder
 Conclusion: A Half Adder is a basic combinational logic circuit used for adding two single-bit
binary numbers. It has two inputs (A, B) and two outputs (Sum, Carry). The Half Adder can only
add two bits, producing a sum and a carry-out if necessary, but it cannot account for carry-in
from previous calculations.
 Truth Table:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
 Applications:
a) Digital Circuits: Used in simple arithmetic operations within digital systems, such as adders
for calculators or processors.
b) Binary Additions: Fundamental in more complex circuits like ALUs (Arithmetic Logic
Units).
2. Full Adder
 Conclusion: The Full Adder is an extension of the Half Adder. It adds three bits, including a
carry-in from a previous stage. The Full Adder has three inputs (A, B, Carry-in) and two outputs
(Sum and Carry-out). It handles carry propagation and is used for adding multi-bit numbers.
 Truth Table:
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
 A B Cin Sum Cout
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 Applications:
a) Binary Addition: Core component in binary arithmetic operations in microprocessors and
ALUs.
b) Digital Calculators: Used in circuits of calculators for multi-bit addition.
c) Signal Processing: Used in digital signal processors (DSP) for combining data.
3. Half Subtractor
 Conclusion: A Half Subtractor is a combinational logic circuit used to subtract two single-bit
binary numbers. It has two inputs (Minuend, Subtrahend) and two outputs (Difference, Borrow).
It does not handle borrow input from previous operations.
 Truth Table:
A B Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
 Applications:
a) Binary Subtraction: Used in simple subtraction operations within digital systems.
b) Digital Subtractors: Can be used in digital systems such as simple calculators.
c) Basic Arithmetic Units: In processors for low-level subtraction.
4. Full Subtractor
 Conclusion: A Full Subtractor extends the Half Subtractor by incorporating a borrow-in bit. It
can subtract three bits, including the borrow from a previous calculation. The Full Subtractor has
three inputs (Minuend, Subtrahend, Borrow-in) and two outputs (Difference, Borrow-out).
 Truth Table:
 A B Bin Difference Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 0
 Applications:
a) Binary Subtraction: Critical for multi-bit binary subtraction, especially in ALUs (Arithmetic
Logic Units).
b) Arithmetic and Logic Units (ALUs): Core to subtraction operations within processors.
c) Digital Subtractors: Used in systems where borrowing is necessary, such as in signed binary
subtraction.