January 20, 2021
CS 303 Logic and Digital System Design – Final Exam
Q1) (15 pts) Schoolbook division is a bit-wise division, realized as follows:
1 0 1 1 0 1 1 1 0
- 0 0 0 0 1 1 1
1 0 1 1
- 1 1 0
1 0 1 0
- 1 1 0
1 0 0 1
- 1 1 0
1 1
This is an example division operation of a 6-bit number divided by a 3-bit
number. Quotient is 7 and remainder is 3, where divisor is 6 and dividend is
45. We can verify that 45 = 7*6+3.
Design a combinational circuit that divides an unsigned 3-bit number with
an unsigned 2-bit number. Show your design steps clearly and draw the
circuit. (Assume that division by 0 is not defined)
Quotient C = ⎣A/B⎦
Remainder D = A%B
1
Q2) (15 pts) Consider the sequential circuit with three D flip-flops (X2, X1, X0)
below.
a) (10 pts) Fill the following state table.
Current state Next state
X2(t) X1(t) X0(t) X2(t+1) X1(t+1) X0(t+1)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
b) (5 pts) Assume that the output of the circuit is (X2 X1 X0)2. Explain what
this circuit does?
2
3) (20 pts) A pattern matching circuit accepts an arbitrary length binary
sequence A and outputs 1 (X) every time it detects a certain pattern. Design a
pattern-matching circuit that detects a sequence “101”. This circuit allows
overlaps and outputs another bit (Y) indicating if the output is a result of an
overlap. An example sequence and its corresponding outputs are shown below.
A 1 0 1 0 1 1 0 1 0 1 0 1 1 1 0 1 1
X 0 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 0
Y 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0
Show your design steps clearly and draw the circuit.
3
4) (15 pts) Hardware pipelining is a common method to achieve faster clock
frequencies by dividing operations into multiple stages, which are separated by
registers. Consider the following figure and table show a 2-stage pipelined
circuit and the latencies of each stage (in pico seconds). The propagation delay
and setup time of intermediate registers are 10 ps and 10 ps, respectively.
Stage I Stage II
200 ps 100 ps
a) (10 pts) Find the maximum clock frequency that can be applied to the circuit.
b) (5 pts) We want to improve the clock frequency of the circuit by further
pipelining only one of the stages. Assuming that we can halve the latency of
each stage, which stage must be selected? What is the new maximum clock
frequency?
4
5) (15 pts) Assume that you have an FPGA that is utilizing 3:1 (three 1-bit inputs
and one 1-bit output) LUT structures.
Can you implement the Boolean function F(x, y, z, t) = Σ(0, 1, 2, 7, 11, 12, 13,
14) using LUT structures in the FPGA? If yes, draw the circuit (only with LUTs)
and determine what each LUT implements (show your design steps clearly).
5
6) (20 pts) Assume that you have access to only the following type of dual port
memory IC:
- 9-bit write address
- 9-bit read address
- 16-bit input data
- 16-bit output data
- 1-bit write enable
- 1-bit read enable
a) (10 pts) You are required to construct a dual port memory circuit with the
following properties (using given memory IC and any building blocks you want):
- 10-bit write address
- 10-bit read address
- 32-bit input data
- 32-bit output data
- 1-bit write enable
- 1-bit read enable
Draw your circuit (show your design steps clearly).
b) (10 pts) You are required to construct a single port memory circuit with the
following properties (using given memory IC and any building blocks you want):
- 10-bit write/read address
- 32-bit input data
- 32-bit output data
- 1-bit write enable
- 1-bit read enable
Draw your circuit (show your design steps clearly).
