PGT104 – Digital Electronics

PGT104 – Digital Electronics

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 Part 4 – Combinational Logic Circuits

Disclaimer:
•Most of the contents (if not all) are extracted from resources
available for Digital Fundamentals 10th Edition

PGT104 – Digital Electronics

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 Half-Adder
Basic rules of binary addition are performed by a
Inputs Outputs
half adder, which has two binary inputs (A and
A B Cout S
B) and two binary outputs (Carry out and Sum). 0 0
0 0
0 1 0 1
The inputs and outputs can be summarized on a 1 0 0 1
truth table. 1 1 1 0

The logic symbol and equivalent circuit are:

S S
A S
A
Cout
B Cout B

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 Full-Adder
Inputs Outputs
A B Cin Cout S
By contrast, a full adder has three binary
0 0 0 0 0
inputs (A, B, and Carry in) and two binary 0 0 1 0 1
outputs (Carry out and Sum). The truth table 0 1 0 0 1
summarizes the operation. 0 1 1 1 0
1 0 0 0 1
A full-adder can be constructed from two 1 0 1 1 0
half adders as shown: 1 1 0 1 0
1 1 1 1 1
S S
A A S A S Sum
S
B B Cout B Cout A S
B
C
Cin Cin out

Cout
Symbol
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 Full-Adder S S 0 Sum
1 A S 1 A S
Example
0 B Cout 0 B Cout 1

For the given inputs, determine 1 Cout

the intermediate and final outputs 1
of the full adder.
The first half-adder has inputs of 1 and 0;
therefore the Sum =1 and the Carry out = 0.
The second half-adder has inputs of 1 and 1; therefore the
Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry
out = 1.

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Full-Adder

Notice that the result from the previous example can be

read directly on the truth table for a full adder.

Inputs Outputs
A B Cin Cout S
S S 0 Sum
0 0 0 0 0 1 A S 1 A S
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 0 B Cout 0 B Cout 1
1 0 0 0 1
1 0 1 1 0 1 Cout
1 1 0 1 0
1 1 1 1 1 1

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 Parallel Adders
Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A4 B4 A3 B3 A2 B2 A1 B1

C0

A B Cin A B Cin A B Cin A B Cin

Cout S Cout S Cout S Cout S

C4
C3 C2 C1
S S S S

The output carry (C4) is not ready until it propagates through all of the
full adders. This is called ripple carry, delaying the addition process.

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 Parallel Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a carry in (labeled (C0) and a Carry out (labeled C4).
S
1 1
Binary 2 2 4-bit
number A 3 3 sum
4 4
1
Binary 2
number B 3
4
Input Output
C0 C4
carry carry

The 74LS283 is an example. It features look-ahead carry, which adds

logic to minimize the output carry delay. For the 74LS283, the
maximum delay to the output carry is 17 ns.

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 Comparators
The function of a comparator is to compare the magnitudes of two
binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?
Example
AND the outputs of four XNOR gates.
A1
B1
A2
B2 Output
A3
B3
A4
B4

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 Comparators
IC comparators provide outputs to indicate which of the numbers is
larger or if they are equal. The bits are numbered starting at 0, rather
than 1 as in the case of adders. Cascading inputs are provided to
expand the comparator to larger numbers.

COMP
A0 0
A1 A
A2
A3 3
Cascading A>B A>B
A=B A=B Outputs
inputs
A<B A<B
B0 0
B1 A
The IC shown is the
B2
B3 3 4-bit 74LS85.

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Comparators
IC comparators can be expanded using the cascading inputs as
shown. The lowest order comparator has a HIGH on the A = B input.
LSBs MSBs

A0 COMP A4 COMP
A1 0 A5 0
A2 A A6 A
A3 A7
3 3
A>B A>B A>B A>B
+5.0 V A=B A=B A=B A=B Outputs
A<B A<B A<B A<B
B0 0 B4 0
B1 A B5 A
B2 B6
B3 3 B7 3

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Decoders
A decoder is a logic circuit that detects the presence of a specific
combination of bits at its input. Two simple decoders that detect the
presence of the binary code 0011 are shown. The first has an active
HIGH output; the second has an active LOW output.

A0 A0
A1 X A1 X

A2 A2

A3 A3

Active HIGH decoder for 0011 Active LOW decoder for 0011

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 Decoders

Assume the output of the decoder shown is a

Try This!
logic 1. What are the inputs to the decoder?

A0 = 0
A1 = 1
1
A2 = 0
A3 = 1

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 Decoders
IC decoders have multiple outputs to decode any
combination of inputs. For example the binary-to-decimal
decoder shown here has 16 outputs – one for each
combination of binary inputs.
Bin/Dec
0
For the input shown, 1
2
Try This! what is the output? 3
4
1 A0 5
6
4-bit binary 1 A1 7 Decimal
input 0 A2 8 outputs
9
1 A3 10
11
12
13
14
15

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Decoders
X/Y
0
A specific integrated circuit 1
decoder is the 74HC154 (shown as 2
3
a 4-to-16 decoder). It includes two 4

active LOW chip select lines which A0 1

5
6
must be at the active level to enable A1 2 7
A2
the outputs. These lines can be used A3
4
8
8
9
to expand the decoder to larger 10
11
inputs. 12
13
14
CS1 & 15
CS2 EN
74HC154

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 Checkpoint
• Another decoder IC is 74LS138
– a 3-8 decoder (active low output)
– 3 'enable' bits (G1 - active high, /G2A & /G2B –
active low)
• Let a 3-bit counter (output C2C1C0) to be used
as input to a 74LS138 IC
– assume all enable bits asserted
– sketch the output if counter is counting up

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 BCD/DEC
Decoders 0
(1)
(2)
1
(3)
2
(15) (4)
BCD-to-decimal decoders accept a binary A0 1 3
(14) (5)
coded decimal input and activate one of ten A1 2 4
A2 (13) 4 5
(6)
possible decimal digit indications. (12)
8 (7)
A3 6
(9)
7
Assume the inputs to the 74HC42 (10)
8
(11)
Example decoder are the sequence 0101, 0110, 9
0011, and 0010. Describe the output.
74HC42

All lines are HIGH except for one active output, which
is LOW. The active outputs are 5, 6, 3, and 2 in that
order.

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 BCD Decoder/Driver
Another useful decoder is the 74LS47. This is a BCD-to-
seven segment display with active LOW outputs.
VCC

(16)
BCD/7-seg
The a-g outputs are BI/RBO
(4)
BI/RBO
(13)
designed for much (7)
1
a
(12)
b
higher current than most BCD
(1)
2
c
(11)
Outputs
(2)
devices (hence the word inputs
(6)
4
d
(10) to seven
8 (9) segment
driver in the name). (3)
e
(15) device
LT LT f
(5) (14)
RBI RBI g

74LS47 (8)

GND

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BCD Decoder/Driver
Here the 7447A is an connected to an LED seven segment
display. Notice the current limiting resistors, required to
prevent overdriving the LED display.
+5.0 V
1.0 kW
+5.0 V
74LS47 16
R's = MAN72
BCD/7-seg
3 VCC 330 W 3, 9, 14
LT a 13 1 a
4
BI/RBO b 12 13 b
5 RBI 11 10
c c
6 A 10 8
d d
2 B e 9 7 e
BCD
input 1 C f 15 2 f
g 14 11 g
7
D
GND
8

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BCD Decoder/Driver
The 74LS47 features leading zero suppression, which
blanks unnecessary leading zeros but keeps significant
zeros as illustrated here. The BI/RBO output is connected
to the RBI input of the next decoder.
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

Blanked Blanked Depending on the display type, current

limiting resistors may be required.

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 BCD Decoder/Driver
Trailing zero suppression blanks unnecessary trailing
zeros to the right of the decimal point as illustrated here.
The RBI input is connected to the BI/RBO output of the
following decoder.
0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0

RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1 RBI LT 8 4 2 1

74LS47 74LS47 74LS47 74LS47

g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO g f e d c b a BI/RBO

1 0 0

Decimal Blanked Blanked

point

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 Encoders
An encoder accepts an active logic level on one of its
inputs and converts it to a coded output, such as BCD or
binary.
1
The decimal to BCD is an encoder A0
with an input for each of the ten 2

decimal digits and four outputs that 3

A1
represent the BCD code for the active
4
digit. The basic logic diagram is 5 A2
6
shown. There is no zero input 7
because the outputs are all LOW 8
A3
when the input is zero. 9

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Encoders
Show how the decimal-to-BCD encoder converts the
decimal number 3 into a BCD 0011.
Example The top two OR gates have ones as indicated with
the red lines. Thus the output is 0111.

1 0 1
A0
2 0
1
3 1
A1

4 0
5 0 0
6
0
0 A2
7
8 0 0
A3
0
9

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 Encoders
The 74HC147 is an example of an IC encoder. It is has ten
active-LOW inputs and converts the active input to an
active-LOW BCD output. V CC

(16)
This device is offers additional (11)
HPRI/BCD
1
flexibility in that it is a priority (12)
2
(13)
encoder. This means that if more (1)
3
1
(9)
4 (7)
than one input is active, the one Decimal (2) 5
2
(6)
BCD
input (3) 4 output
with the highest order decimal (4)
6
8 (14)
7
digit will be active. (5)
8
(10) 9
(8)
74HC147
The next slide shows an application … GND

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 VCC
Encoders R7 R8 R9

Keyboard
7 8 9
encoder HPRI/BCD
1
R4 R5 R6 2
3
1
4 2
5 4 BCD complement of
6
4 5 6 7
8 key press
8
9

R1 R2 R3 74HC147

1 2 3

R0
The zero line is not needed by the
0 encoder, but may be used by other
circuits to detect a key press.

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 Checkpoint
• Gray code (reflected binary code)
– only 1 bit changes between 2 successive value
– very useful for error detection/correction

2-bit Gray 3-bit Gray

Code Code
00 000
01 001
11 011
10 010
110
111
101
100

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 Code converters

There are various code converters that change one code to

another. Two examples are the four bit binary-to-Gray
converter and the Gray-to-binary converter.
Show the conversion of binary 0111 to Gray and back.
Try This! 0 1 LSB
1 0
LSB
0 1
1 0

1 1 1 1

0 0
0 MSB 0 MSB
Binary-to-Gray Gray-to-Binary

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 Multiplexers
A multiplexer (MUX) selects one data line from two or
more input lines and routes data from the selected line to
the output. The particular data line that is selected is
determined by the select inputs.
MUX
Two select lines are shown 0
S0 0
Data 1
here to choose any of the select S1
1
four data inputs.
D0 0 Data
Try This! Data
D1 1 output
D 2
inputs D2
Which data line is selected 3 3
if S1S0 = 10?

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 Demultiplexers
A demultiplexer (DEMUX) performs the opposite function
from a MUX. It switches data from one input line to two or
more data lines depending on the select inputs.
The 74LS138 was introduced
DEMUX
previously as a decoder but can also A0
Y
0
Data
serve as a DEMUX. When select A1
Y
1

Y
connected as a DEMUX, data is lines A2 2

Data
Y
applied to one of the enable inputs, 3

Y
outputs
and routed to the selected output Enable G1 4

Y
G2A
5

line depending on the select inputs

G2B
Y
6

variables. Note that the outputs are Y

7

active-LOW as illustrated in the 74LS138

following example…

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 A0
A1
Demultiplexers
A2
Determine the outputs, given the
inputs shown. G1
Try This! G2A LOW
The output logic is opposite to the input G2B LOW
because of the active-LOW convention. (Red
shows the selected line). Y0
DEMUX Y1
Y
Data A0 0

Y2
Y
select A1 1

Y
lines A2 2

Data
Y3
Y
Y4
3

Y
outputs
Enable G1 4

Y
G2A
5
Y5
inputs Y
G2B 6

Y6
Y
7

74LS138 Y7
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 Quiz

For the full-adder shown, assume the input bits are as shown
with A = 0, B = 0, Cin = 1. The Sum and Cout will be
a. Sum = 0 Cout = 0
S S Sum
0 A S A S
b. Sum = 0 Cout = 1
0 B Cout B Cout
c. Sum = 1 Cout = 0
1
d. Sum = 1 Cout = 1 Cout

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 Quiz

The output will be LOW if

a. A < B A1
B1
b. A > B A2 Output
B2
c. both a and b are A3
correct B3
A4
d. A = B B4

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 Quiz

If you expand two 4-bit comparators to accept two 8-bit

numbers, the output of the least significant comparator is
a. equal to the final output
b. connected to the cascading inputs of the most
significant comparator
c. connected to the output of the most significant
comparator
d. not used

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 Quiz

Assume you want to decode the binary number 0011 with an

active-LOW decoder. The missing gate should be
a. an AND gate A0
X
b. an OR gate
A1
?
A2
c. a NAND gate
A3
d. a NOR gate

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 Quiz

Assume you want to decode the binary number 0011 with an

active-HIGH decoder. The missing gate should be
a. an AND gate A0
X
b. an OR gate
A1
?
A2
c. a NAND gate
A3
d. a NOR gate

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 Quiz

The 74138 is a 3-to-8 decoder. Together, two of these ICs can

be used to form one 4-to-16 decoder. To do this, connect
a. one decoder to the LSBs of the input; the other
decoder to the MSBs of the input
b. all chip select lines to ground
c. all chip select lines to their active levels
d. one chip select line on each decoder to the input MSB

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 Quiz

The decimal-to-binary encoder shown does not have a zero

input. This is because
a. when zero is the input, 1
A0
all lines should be LOW 2
3
A1
b. zero is not important
4
5 A2
c. zero will produce 6
7
illegal logic levels 8
A3
9
d. another encoder is used
for zero

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 Quiz

If the data select lines of the MUX are S1S0 = 11, the output
will be
a. LOW MUX
S0 0
Data
b. HIGH select S1
1

c. equal to D0 D0 0 Data
D1 1 output
Data
D 2
d. equal to D3 inputs D2
3 3

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 Quiz

The 74138 decoder can also be used as

a. an encoder
b. a DEMUX
c. a MUX
d. none of the above

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