Adder

dder
• Addition is the most commonly used arithmetic
operation. It often is the speed-limiting
speed element as well.
Therefore, careful optimization of the Adder is of the
utmost importance. This optimization can proceed
either at the logic or circuit level. ‘Typical logic-level
optimizations try to rear range the Boolean equations so
that a faster or smaller circuit is obtained.
 The Binary Adder
A B

C in Fu ll C ou t
add er

S um

S = A  B  Ci

= ABCi + A BC i + AB Ci + A B C
Co = AB + B Ci + ACi
27
 Express Sum and Carry as a function of P, G, D

Define 3 new variables which ONLY depend on A, B

Generate (G) = AB
Propagate (P) = A  B
Delete = A B

We can also derive expressions for S and C o based on D and P

Note that we will be sometimes using an alternate definition for
Propagate (P) = A + B
 A Better Structure: The Mirror Adder
VDD

VD D VDD A

A B B A B Ci B
K ill
"0 "-P r op ag ate A Ci
Co
Ci S
A Ci
"1 "-P r op ag ate G e ne r ate
A B B A B Ci A

2 4 tran s isto rs
 The Mirror Adder
•The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the
carry-generation circuitry.
•When laying out the cell, the most critical issue is the
minimization of the capacitance at node Co. The reduction of
the diffusion capacitances is particularly important.
•The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
•The transistors connected to Ci are placed closest to the
output. Only the transistors in the carry stage have to be
optimized for optimal speed. All transistors in the sum stage
can be minimal size.
 Ripple Carry Adder
• To add multiple ‘n’ bits binary sequence, multiples
cascaded full adders can be used which can generate a
carry bit and be applied to the next stage full adder as
an input till the last stage of full adder. This appears as
carry-bit
bit ripples to the next stage, hence it is known as
“Ripple carry adder”.
• Worst case delay = [(n-1) 1) full adder * carry propagation
delay of each adder] + sum propagation delay of each
full adder
• Half Adders can be used to add two one bit binary
numbers. It is also possible to create a logical circuit
using multiple full adders to add N-bit
N binary
numbers.Each full adder inputs a Cin, which is
the Cout of the previous adder. This kind of adder is
a Ripple Carry Adder,, since each carry bit "ripples" to
the next full adder. The first (and only the first) full
adder may be replaced by a half adder.The block
diagram of 4-bit
bit Ripple Carry Adder is shown here below
 The Ripple-Carry
Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2 Co,3

FA FA FA FA
( Ci,1)

S0 S1 S2 S3

Worst case delay linear with the number of bits

td = O(N)

tadder = (N
N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit

 Inversion Property

A B A B

Ci FA Co Ci FA Co

S S
 Minimize Critical Path by Reducing Inverting Stages

Even cell Odd cell

A0 B0 A1 B1 A2 B2 A3 B3

Ci,0 Co,0 Co,1 Co,2 Co,3

FA FA FA FA

S0 S1 S2 S3

Exploit Inversion Property

 Carry-Bypass
Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci ,0 C o,0 C o ,1 Co,2 Co,3
FA FA FA FA

P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o ,0 Co,1 C o,2
FA FA FA FA

Multiplexer
Co,3

Idea: If (P0 and P1 and P2 and P3 = 1)

then C o3 = C 0, else “kill” or “generate”.
 A carry-skip adder (also known as a carry-bypass adder) is
an adder implementation that improves the delay of a ripple-
carry adder with little effort compared to other adders. The
improvement of the worst-case case delay is achieved by using
several carry-skip adders to form a block-carry-skip adder.

The idea behind a Carry-Skip

Skip Adder (CSA) is to reduce the
length of this critical path by giving the carry path a shortcut if
all bits in a block would propagate a carry. A block-wide
propagate signal is easy to compute, and each block can
calculate its own propagate signal simultaneously.
 Carry-Bypass
Bypass Adder (cont.)
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup tsetup Setup Setup Setup
tbypass

Carry Carry Carry Carry

propagation propagation propagation propagation

Sum Sum Sum tsum Sum

M bits

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

Carry Ripple versus Carry Bypass

tp
r ipp le a dd e r

b y pa ss a dd e r

4 ..8
N
The first block will calculate a carry in the first bit, and will propagate the carry through
bits 1, 2, and 3. At this point, the first block carry-out
carry signal is valid. The propagate select
signals are already valid, since it is 2-3 gate delays and the carry signal is 4 gate delays.
The carry-in multiplexer for bits 8-11 gets the carry signal from the carry-out of bit 3
since bits 4-7 would propagate a carry. Note that this takes 1 gate delay, while a normal
RCA would take 4 gate delays. Each block will add 1 gate delay to the carry signal.

If the MSB killed carry propagation, then that would cause the last CSA block to ripple
carry the input, which would take another 4 gate delays. This setup of a ‘LSB generate’
and a ‘MSB kill’ is the new worst case.

The source of the critical path is the same between the RCA and CSA, but the critical
path is different. If an arbitrary block generated a carry by itself, the carry will always
propagate to the next block. However, if the second block generates a carry itself, or kills
the carry, than that is the end of the critical path.
path If the second block propagates the carry,
then we see the advantage of the CSA architecture.
architecture Also, when the term "critical path" is
used, it generally implies that you are considering a set of inputs that will cause the
worst-case delay.
 Carry-Select
Select Adder
Setup

P ,G

"0" "0" Carry Propagation

"1" "1" Carry Propagation

C o, k-1 M ultiplexer C o,k+ 3

Ca rry Vector

Sum Generation
Carry select Adder (CSA) is one of the fastest adders used in many data processors to
perform fast arithmetic functions. The carry select adder partitions the adder into
several groups, each of which performs two additions in parallel using dual RCA’s.
One copy evaluates the carry chain assuming the block carry-in is ‘0’, while the other
assumes it to be ‘1’. Once the carry signals are finally computed, the correct sum and
carry-out signals will be simply selected by a set of multiplexers.
Carry Select Adder is one of the adders used in many data processing processors to
perform arithmetic functions. Carry select adder is used to increase the speed of a
parallel adder that expands area in favor of speed. CSLA is used in many
computational systems to alleviate the problem of propagation delay by
independently generating multiple carriers and then select a carry to generate the
sum.
The problem raised in CSLA is that it is not area efficient because it uses multiple
pairs of Ripple carry adders to generate the partial sum and carry which are selected
by the multiplexer.
• In a ripple-carry adder every full-adder
full cell has to wait
for the incoming carry before an outgoing carry can be
generated. One way to get around this linear
dependency is to anticipate both possible values of the
carry input and evaluate the result for both possibilities
in advance once the value of the incoming carry is
known, the correct result is easily selected with a simple
multiplexer stage. An implementation of this idea,
appropriately called the carry-select
carry adder
 Linear Carry Select Adder
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7
,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S0–3 S4–7 S8–11 S12–15
 Carry Select Adder: Critical Path
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup Setup Setup Setup

0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1 1-Carry 1 1-Carry 1 1-Carry 1 1-Carry

Multiplexer Multiplexer Multiplexer Multiplexer

Ci,0 Co,3 Co,7
,7 Co,11 Co,15

Sum Generation Sum Generation Sum Generation Sum Generation

S0–3 S4–7 S8–11 S12–15

47
 Square Root Carry Select
Bi t 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19

S etu p S etu p Se tup S etu p

(1)

" 0" Car ry " 0" C arr y " 0" C arr y " 0" C arry
" 0" "0" " 0" " 0"
(1)

"1" C arry "1" C arry " 1" Car ry " 1" C arr y
"1" " 1" " 1" "1"
(3) (3) (4) (5) (6) (7)
(4) (5) (6) (7)
M ultiplexe r M ultiplexe r M ul tip lexe r Mul tip lexe r M ux
C i, 0
(8)
S u m Gen er ation S um G en erati on S um G en erati on S um G en eration Sum

S 0 -1 S2 -4 S 5 -8 S 9 -1 3 S 1 4 -1 9 (9)
• Consider the multiplexer gate in the last adder stage[ 16 bit carry
select adder] . The inputs to this multiplier are the two carry chains
of the blocks and block multiplexer signal from the previous stage.
A major mismatch between the arrival times of the singles can be
observed. The results of the carry chains of the blocks are stable
before the mux signal arrives. It makes sense to equalise the delay
through both paths.
• This can be achieved by adding more bits to the the subsequent
stages in the adder, requiring more time for the generation of the
carry signals. Eg.. The first stage can add 2 bits , the second contains
3, third has 4 and ...
Delay calculation
Assume that an N bit adder contains P stages, and the first stage adds M bits. An additional
bit is added to each subsequent stage. Then the following relation holds.

If M<<N, then the equation becomes

 Adder Delays - Comparison
50

40 Ripple adder
tp (in unit delays)

30

Linear select
20

10
Square root select

0
0 20 40 60
N
 LookAhead - Basic Idea
A0, B0 A1, B1 ••• AN-1, BN-1

Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1

S0 S1 ••• SN-1

C o k = f A k B k Co  k – 1  = G k + P k Co  k – 1
 Carry lookahead Adder
A carry-look
look ahead adder (CLA) is a type of adder used in digital logic. A carry-look
carry ahead adder
improves speed by reducing the amount of time required to determine carry bits. The carry-look
carry
ahead adder calculates one or more carry bits before the sum, which reduces the wait time to
calculate the result of the larger value bits
To reduce the computation time, there are faster ways to add two binary numbers by using carry
lookahead adders.
They work by creating two signals P and G known to be Carry Propagator and Carry Generator.
The carry propagator is propagated to the next level whereas the carry generator is used to
generate the output carry regardless of input carry
 Look-Ahead:
Ahead: Topology

Expanding Lookahead equations: VDD

C o k = G k + P k Gk – 1 + P k – 1 Co  k – 2  G3

G2

G1
All the way:
G0
C o k = G k + Pk  G k – 1 + P k – 1  + P 1  G 0 + P0 Ci  0   
Ci,0
Co,3

P0

P1

P2

P3
 Carry Lookahead Trees

Co  0 = G 0 + P 0 Ci  0
C o 1 = G 1 + P 1 G 0 + P 1 P 0 Ci 0
C o 2 = G 2 + P 2 G 1 + P 2 P 1 G 0 + P 2 P 1 P 0 C i 0
=  G 2 + P 2 G 1 +  P2 P 1   G 0 + P 0 Ci  0  = G 2:1 + P 2:1 C o 0

Can continue building the tree hierarchically.

Multipliers
The Binary Multiplication
 The Binary Multiplication

1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0

0 0 0 0 0 0 Partial products

+ 1 0 1 0 1 0

1 1 1 0 0 1 1 1 0 Result
The Array Multiplier
 The Array Multiplier
X3 X2 X1 X0 Y0

X3 X2 X1 X0 Y1 Z0

HA FA FA HA

X3 X2 X1 X0 Y2 Z1

FA FA FA HA

X3 X2 X1 X0 Y3 Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3
The MxN Array Multiplier—Critical
Multiplier Path

HA FA FA HA

FA FA FA HA Critical Path 1
Critical Path 2

FA FA FA HA
 Carry-Save
Save Multiplier
HA HA HA HA

HA FA FA FA

HA FA FA FA

HA FA FA HA

Ve c tor M e rg ing A d de r
Multiplier Floorplan
 Shifter
• The shift .operation is another essential arithmetic
operation that requires adequate hardware support. It is
used extensively in floating-point
point units, scalers, and
multiplications by constant numbers. The latter can be -
implemented as a combination of add and shift operations.
Shifting a data word left or right over a constant amount is a
trivial hardware operation and is implemented by the
appropriate signal wiring. A programmable shifter. on the
other hand, is more complex and requires. active circuitry.
In essence, such a shifter is nothing less than an intricate
multiplexer circuit A simple one bit left-right shifter is shown
in Figure
 The Binary Shifter
Right nop Left

Ai Bi

Ai-1 Bi-1

Bit-Slice i

...

72
 Barrel Shifter
• It consists of an array of transistors. in which the number of
rows equals the word length of the data, and the number of
columns equals the maximum -shift width. In this case. both
are set equal to four. The control wires are routed diagonally
through the array. A major advantage of this shifter is that
the signal has to pass through at most one transmission
gate. In other words, the propagation delay is theoretically
constant and independent of the shift value or shifter size.
This is not true in reality. however, because the capacitance
at the input of the buffers rises linearly with the maximum
shift width.
75
• An important property of this circuit is that the layout size is not
dominated by the active transistors as ,in the case of all other
arithmetic circuits, but by the number of wires running through the
cell. More specifically.. the size of the cell is bounded by the pitch of
the metal wires.
• Another important consideration when selecting a shifter is the
format in which the shift value must
m be presented. From the
schematic diagram, we see that the barrel shifter needs a control
wire for every shift bit. For example, a four-bit
four shifter needs four
control signals. To shift over three bits, the signals Sh3.:Sh0 take on
the value 1000. Only one of the signals is high. In a processor the
required shift value normally comes in an encoded binary format,
which is substantially more- compact
 4x4 barrel shifter
A3

A2

A1

A0

Sh0 Sh 1 S h2 Sh3
B uffer
Widthbarrel ~ 2 pm M

78
 Logarithmic Shifter
• While the barrel shifter implements the whole shifter as a
single array of pass transistors, the logarithmic shifter uses a
staged approach. The total shift value is decomposed into
shifts over powers of two. A shifter With a maximum shift
width of M consists of a log2M stages, where the ith stage
either shift over 2^k or passes the data unchanged. An
example of a shifter with a maximum shift value of seven
hits is shown in Figure . For instance, to shift over five bits,
the first stage is set to shift mood. the second to pass mode.
and the last stage again to shift. Notice that the control
word for the shifter is already encoded, and no separate
decoder is required
• In general we conclude that a barrel shifter is
appropriate for smaller shifters. For larger shift values.
the logarithmic shifter becomes more effective, in terms
of both area and speed. Furthermore. the logarithmic
shifter is easily parameterized. allowing for automatic
generation. The most important concept of this section
is that the exploitation of regularity in an arithmetic
operator can lead to dense and high-speed
high circuit
implementations.
81
 0-7
7 bit Logarithmic Shifter

A
3
Out3

A
2
Out2

A
1
Out1

A
0
Out0

82