digital electronics 2022
digital electronics 2022
727 + 1 = 730
Because octal contains 0 to 7 and after 1 in 727 normally it converts to 728 but octal
doesn’t contain 8 , So it starts from 0 and one increase into 2. So, the next number in the
sequence is 730.
(b) What do you mean by a positive logic system and negative logic system?
Ans:- PositiveLogic: In a positive logic system, a binary 1 (or high) represents a
TRUE or ON state, and a binary 0 (or low) represents a FALSE or OFF state.
This is the more common and intuitive way of representing binary values in
most digital systems. In positive logic, high voltage levels often correspond to
logic 1, and low voltage levels correspond to logic 0.
Negative Logic: In a negative logic system, the interpretation is reversed. A
binary 0 represents a TRUE or ON state, and a binary 1 represents a FALSE or
OFF state. This can be somewhat counterintuitive compared to positive logic
but is used in specific applications and scenarios.
(c)Subtract using 9’s complement : 745.81 – 436.62?
Ans:-
(d)The following operation is correct for at least one number system. Find
the correct number system :
1234 + 5432 = 6666 .
(e) What is tri-state logic?
Ans:- Tri-state logic, also known as three-state logic, is a digital logic circuit
that has three output states instead of the usual two (0 and 1) found in binary
logic. The three output states in tri-state logic are:
(f) What are the fastest logic family and the slowest logic family?
Ans:- Emitter-coupled-logic (ECL) is a BJT logic family that is generally
considered the fastest logic available. ECL achieves its high-speed
operation by employing a relatively small voltage swing and preventing
the transistors from entering the saturation region.
Bipolar Transistor-Transistor Logic (TTL): While TTL was once a popular logic
family, it's considered slower than many modern alternatives. It operates at
higher power levels and is not as fast as ECL or other high-speed logic families.
Analog Quantities:
Digital Quantity:
So, to summarize:
That means, in 4-bit gray code, (4-1) or 3-bit code is reflected against the axis drawn
after (24-1)th or 8th row. The bits of 4-bit gray code is considered as G4G3G2G1. Now
from the conversion table
G4=∑m(8,9,10,11,12,13,14,15),
G3=∑m(4,5,6,7,8,9,10,11),
G2=∑m(2,3,4,5,10,11,12,13),
G1=∑m(1,2,5,6,9,10,13,14)
From above SOPs, let us draw K-maps for G4, G3, G2 and G1.
3(c) Reduce the following expression using K-map and implement it in AOI
logic as well as in NOR logic : F = IIM(0,1,2,3,4,7)
Ans:- Alright, let's simplify this expression using a Karnaugh Map (K-map). The given
expression is F = Σ(0,1,2,3,4,7).
000 1
001 1
010 1
011 1
100 1
101 0
110 X
111 1
X represents "don't care" conditions.
Now, let's implement this expression in AND-OR-INVERT (AOI) logic and NOR logic.
4(a) Reduce the following expression and implement it using universal logic gate :
Σm(1,5,6,12,13,14)+d(2,4).
Ans:- let's simplify the given expression and then implement it using universal logic gates.
ABCD F
0001 1
0101 1
0110 1
1100 1
1101 1
1110 1
0010 0
ABCD F
0100 0
A'B'CD' + ABCD
Now, let's implement it using universal logic gates. Universal gates include NAND gates and
NOR gates, which can be used to implement any other logic gate.
1. F=(A’B’CD’+ABCD)’
2. Implement the simplified expression using NOR gates.
4(b) Use a multiplexer to implement the logic function F = A⊕B⊕C .
Ans:-
Use the select lines of the multiplexer to represent the binary values of ABC (e.g., S1
= A, S0 = B). The output of the multiplexer will be the desired logic function �F.
000 00 0
001 01 1
010 10 1
011 11 0
100 00 1
101 01 0
110 10 0
111 11 1
The connections to the multiplexer inputs would be based on the expressions for
each term in the XOR function.
5(b)Design the conversion circuit for S-R flip-flop to J-K flip-flop.
Step 1 − The excitation table for the conversion of SR flip-flop into JK flip-flop
is given below −
J K Qn Qn+1 S R S R
0 0 0 0 0 0 0 X
0 1
0 0 1 1 0 0 X 0
1 0
0 1 0 0 0 0 0 X
0 1
0 1 1 0 0 1 0 1
1 0 0 1 1 0 1 0
1 0 1 1 0 0 X 0
1 0
1 1 0 1 1 0 1 0
1 1 1 0 0 1 0 1
R = KQn
Step 3 − Finally, draw the logic diagram of JK flip flop by using SR flip flop,
which is shown in figure-3 below.
Ans:- Counter: A counter is a digital circuit that counts the number of clock pulses or
events. It can increment or decrement its count based on the clock input. Counters are used to
generate sequences of binary numbers, and they find applications in various tasks like
frequency division, timekeeping, and addressing memory locations.
There are different types of counters, including binary counters, up/down counters, and ring
counters. Binary counters, for example, simply count in binary from 0 to 2^n-1, where n is
the number of bits.
Shift Register: A shift register is a digital circuit that stores and shifts data serially. It holds a
sequence of bits and shifts them left or right based on the clock input. Shift registers are used
for tasks such as data storage, parallel-to-serial or serial-to-parallel conversion, and creating
delay lines.
There are various types of shift registers, including serial-in-parallel-out (SIPO), parallel-in-
serial-out (PISO), serial-in-serial-out (SISO), and parallel-in-parallel-out (PIPO). The type of
shift register used depends on the specific application requirements.
6(b)With the neat diagrams, explain the working of the following types of shift
registers:
(i) Serial-in, serial out
(ii) Serial-in, parallel out
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as a Serial-In Serial-Out shift register. Since there is
only one output, the data leaves the shift register one bit at a time in a serial pattern, thus the
name Serial-In Serial-Out Shift Register. The logic circuit given below shows a serial-in
serial-out shift register. The circuit consists of four D flip-flops which are connected in a
serial manner. All these flip-flops are synchronous with each other since the same clock
signal is applied to each flip-flop.
(ii)Serial-In Parallel-Out Shift Register (SIPO)
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as the Serial-In Parallel-Out shift register. The logic
circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four
D flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock
signal to all 4 flip flops in order to RESET them. The output of the first flip-flop is connected
to the input of the next flip flop and so on. All these flip-flops are synchronous with each
other since the same clock signal is applied to each flip-flop.
Excitation table of T FF
If there is a change in the output state of a flip flop (i.e. 0 to 1 or 1 to 0), then the
corresponding T value becomes 1 otherwise 0.
6. Find a simplified equation using k map –
Here we are finding the minimal Boolean expression for each Flip Flop input T
using k map.
Simplified equation for K map